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[AArch64] Add SVE conditional integer unary patterns
This patch adds patterns to match conditional unary operations on integers. At the moment we rely on combine to merge separate arithmetic and vcond_mask operations, and since the latter doesn't accept zero operands, we miss out on the opportunity to use the movprfx /z alternative. (This alternative is tested by the ACLE patches though.) 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org> gcc/ * config/aarch64/aarch64-sve.md (*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_2): New pattern. (*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_any): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/cond_unary_1.c: New test. * gcc.target/aarch64/sve/cond_unary_1_run.c: Likewise. * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. * gcc.target/aarch64/sve/cond_unary_2_run.c: Likewise. * gcc.target/aarch64/sve/cond_unary_3.c: Likewise. * gcc.target/aarch64/sve/cond_unary_3_run.c: Likewise. * gcc.target/aarch64/sve/cond_unary_4.c: Likewise. * gcc.target/aarch64/sve/cond_unary_4_run.c: Likewise. Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org> From-SVN: r274476
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
7eeb5982c3
commit
3c9f496337
@ -1,3 +1,10 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* config/aarch64/aarch64-sve.md
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(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_2): New pattern.
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(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_any): Likewise.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_COND_FP_ABS_CMP): New iterator.
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@ -1454,6 +1454,45 @@
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"<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
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)
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;; Predicated integer unary arithmetic, merging with the first input.
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(define_insn "*cond_<optab><mode>_2"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(SVE_INT_UNARY:SVE_I
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(match_operand:SVE_I 2 "register_operand" "0, w"))
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(match_dup 2)]
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UNSPEC_SEL))]
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"TARGET_SVE"
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"@
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<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>
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movprfx\t%0, %2\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
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[(set_attr "movprfx" "*,yes")]
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)
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;; Predicated integer unary arithmetic, merging with an independent value.
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;;
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;; The earlyclobber isn't needed for the first alternative, but omitting
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;; it would only help the case in which operands 2 and 3 are the same,
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;; which is handled above rather than here. Marking all the alternatives
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;; as earlyclobber helps to make the instruction more regular to the
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;; register allocator.
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(define_insn "*cond_<optab><mode>_any"
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[(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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(SVE_INT_UNARY:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w, w"))
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(match_operand:SVE_I 3 "aarch64_simd_reg_or_zero" "0, Dz, w")]
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UNSPEC_SEL))]
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"TARGET_SVE && !rtx_equal_p (operands[2], operands[3])"
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"@
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<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype>
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movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype>
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movprfx\t%0, %3\;<sve_int_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
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[(set_attr "movprfx" "*,yes,yes")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Logical inverse
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;; -------------------------------------------------------------------------
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@ -1,3 +1,15 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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* gcc.target/aarch64/sve/cond_unary_1.c: New test.
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* gcc.target/aarch64/sve/cond_unary_1_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_2_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_3.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_3_run.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_4.c: Likewise.
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* gcc.target/aarch64/sve/cond_unary_4_run.c: Likewise.
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2019-08-14 Bob Duff <duff@adacore.com>
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* gnat.dg/alignment15.adb: New testcase.
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44
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c
Normal file
44
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c
Normal file
@ -0,0 +1,44 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define abs(A) ((A) < 0 ? -(A) : (A))
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#define neg(A) (-(A))
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#define DEF_LOOP(TYPE, OP) \
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void __attribute__ ((noipa)) \
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test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict pred, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = pred[i] ? OP (a[i]) : a[i]; \
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}
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#define TEST_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* XFAILed because the ?: gets canonicalized so that the operation is in
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the false arm. */
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/* { dg-final { scan-assembler-not {\tsel\t} { xfail *-*-* } } } */
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27
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1_run.c
Normal file
27
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1_run.c
Normal file
@ -0,0 +1,27 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_unary_1.c"
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#define N 99
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#define TEST_LOOP(TYPE, OP) \
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{ \
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TYPE r[N], a[N], pred[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
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pred[i] = (i % 7 < 4); \
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asm volatile ("" ::: "memory"); \
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} \
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test_##TYPE##_##OP (r, a, pred, N); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (pred[i] ? OP (a[i]) : a[i])) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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43
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c
Normal file
43
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c
Normal file
@ -0,0 +1,43 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define abs(A) ((A) < 0 ? -(A) : (A))
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#define neg(A) (-(A))
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#define DEF_LOOP(TYPE, OP) \
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void __attribute__ ((noipa)) \
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test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict b, \
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TYPE *__restrict pred, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = pred[i] ? OP (a[i]) : b[i]; \
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}
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#define TEST_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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28
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2_run.c
Normal file
28
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2_run.c
Normal file
@ -0,0 +1,28 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_unary_2.c"
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#define N 99
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#define TEST_LOOP(TYPE, OP) \
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{ \
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TYPE r[N], a[N], b[N], pred[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
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b[i] = (i % 9) * (i % 7 + 1); \
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pred[i] = (i % 7 < 4); \
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asm volatile ("" ::: "memory"); \
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} \
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test_##TYPE##_##OP (r, a, b, pred, N); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (pred[i] ? OP (a[i]) : b[i])) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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43
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c
Normal file
43
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c
Normal file
@ -0,0 +1,43 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define abs(A) ((A) < 0 ? -(A) : (A))
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#define neg(A) (-(A))
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#define DEF_LOOP(TYPE, OP) \
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void __attribute__ ((noipa)) \
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test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict pred, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = pred[i] ? OP (a[i]) : 5; \
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}
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#define TEST_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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27
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3_run.c
Normal file
27
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3_run.c
Normal file
@ -0,0 +1,27 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_unary_3.c"
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#define N 99
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#define TEST_LOOP(TYPE, OP) \
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{ \
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TYPE r[N], a[N], pred[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
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pred[i] = (i % 7 < 4); \
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asm volatile ("" ::: "memory"); \
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} \
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test_##TYPE##_##OP (r, a, pred, N); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (pred[i] ? OP (a[i]) : 5)) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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47
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c
Normal file
47
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c
Normal file
@ -0,0 +1,47 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define abs(A) ((A) < 0 ? -(A) : (A))
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#define neg(A) (-(A))
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#define DEF_LOOP(TYPE, OP) \
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void __attribute__ ((noipa)) \
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test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a, \
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TYPE *__restrict pred, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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r[i] = pred[i] ? OP (a[i]) : 0; \
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}
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#define TEST_TYPE(T, TYPE) \
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T (TYPE, abs) \
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T (TYPE, neg)
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#define TEST_ALL(T) \
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TEST_TYPE (T, int8_t) \
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TEST_TYPE (T, int16_t) \
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TEST_TYPE (T, int32_t) \
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TEST_TYPE (T, int64_t)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
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/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
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|
||||
/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.b, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */
|
||||
|
||||
/* Really we should be able to use MOVPRFX /z here, but at the moment
|
||||
we're relying on combine to merge a SEL and an arithmetic operation,
|
||||
and the SEL doesn't allow the "false" value to be zero when the "true"
|
||||
value is a register. */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
27
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4_run.c
Normal file
27
gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4_run.c
Normal file
@ -0,0 +1,27 @@
|
||||
/* { dg-do run { target { aarch64_sve_hw } } } */
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include "cond_unary_4.c"
|
||||
|
||||
#define N 99
|
||||
|
||||
#define TEST_LOOP(TYPE, OP) \
|
||||
{ \
|
||||
TYPE r[N], a[N], pred[N]; \
|
||||
for (int i = 0; i < N; ++i) \
|
||||
{ \
|
||||
a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
|
||||
pred[i] = (i % 7 < 4); \
|
||||
asm volatile ("" ::: "memory"); \
|
||||
} \
|
||||
test_##TYPE##_##OP (r, a, pred, N); \
|
||||
for (int i = 0; i < N; ++i) \
|
||||
if (r[i] != (pred[i] ? OP (a[i]) : 0)) \
|
||||
__builtin_abort (); \
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
TEST_ALL (TEST_LOOP)
|
||||
return 0;
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user