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sse.md (define_mode_iterator VF2_AVX512VL): New.
gcc/ * config/i386/sse.md (define_mode_iterator VF2_AVX512VL): New. (define_mode_attr sseintvecmode2): New. (define_insn "ufix_truncv2dfv2si2<mask_name>"): Add masking. (define_insn "fix_truncv4dfv4si2<mask_name>"): New. (define_insn "ufix_truncv4dfv4si2<mask_name>"): Ditto. (define_insn "<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"): Ditto. (define_insn "fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"): Ditto. (define_insn "ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"): Ditto. Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com> Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com> Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com> Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com> Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com> Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com> Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com> From-SVN: r214090
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@ -1,3 +1,26 @@
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2014-08-18 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/i386/sse.md
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(define_mode_iterator VF2_AVX512VL): New.
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(define_mode_attr sseintvecmode2): New.
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(define_insn "ufix_truncv2dfv2si2<mask_name>"): Add masking.
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(define_insn "fix_truncv4dfv4si2<mask_name>"): New.
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(define_insn "ufix_truncv4dfv4si2<mask_name>"): Ditto.
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(define_insn
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"<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"):
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Ditto.
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(define_insn "fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"):
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Ditto.
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(define_insn "ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"):
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Ditto.
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2014-08-18 Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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@ -228,6 +228,9 @@
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(define_mode_iterator VF_512
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[V16SF V8DF])
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(define_mode_iterator VF2_AVX512VL
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[V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
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;; All vector integer modes
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(define_mode_iterator VI
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[(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")
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@ -523,6 +526,10 @@
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(V32HI "V32HI") (V64QI "V64QI")
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(V32QI "V32QI") (V16QI "V16QI")])
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(define_mode_attr sseintvecmode2
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[(V8DF "XI") (V4DF "OI") (V2DF "TI")
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(V8SF "OI") (V4SF "TI")])
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(define_mode_attr sseintvecmodelower
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[(V16SF "v16si") (V8DF "v8di")
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(V8SF "v8si") (V4DF "v4di")
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@ -4235,15 +4242,67 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "OI")])
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(define_insn "fix_truncv4dfv4si2"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
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"TARGET_AVX"
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"vcvttpd2dq{y}\t{%1, %0|%0, %1}"
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(define_insn "ufix_truncv2dfv2si2<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(vec_concat:V4SI
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(unsigned_fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
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(const_vector:V2SI [(const_int 0) (const_int 0)])))]
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"TARGET_AVX512VL"
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"vcvttpd2udq{x}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "vex")
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(set_attr "prefix" "evex")
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(set_attr "mode" "TI")])
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(define_insn "fix_truncv4dfv4si2<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
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"TARGET_AVX || (TARGET_AVX512VL && TARGET_AVX512F)"
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"vcvttpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_evex")
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(set_attr "mode" "OI")])
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(define_insn "ufix_truncv4dfv4si2<mask_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unsigned_fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
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"TARGET_AVX512VL && TARGET_AVX512F"
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"vcvttpd2udq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_evex")
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(set_attr "mode" "OI")])
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(define_insn "<fixsuffix>fix_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>"
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[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
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(any_fix:<sseintvecmode>
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(match_operand:VF2_AVX512VL 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")))]
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"TARGET_AVX512DQ && <round_saeonly_mode512bit_condition>"
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"vcvttpd2<fixsuffix>qq\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecmode2>")])
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(define_insn "fix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"
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[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
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(unspec:<sseintvecmode>
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[(match_operand:VF2_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")]
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UNSPEC_FIX_NOTRUNC))]
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"TARGET_AVX512DQ && <round_mode512bit_condition>"
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"vcvtpd2qq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecmode2>")])
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(define_insn "ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>"
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[(set (match_operand:<sseintvecmode> 0 "register_operand" "=v")
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(unspec:<sseintvecmode>
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[(match_operand:VF2_AVX512VL 1 "nonimmediate_operand" "<round_constraint>")]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512DQ && <round_mode512bit_condition>"
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"vcvtpd2uqq\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseintvecmode2>")])
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(define_expand "avx_cvttpd2dq256_2"
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[(set (match_operand:V8SI 0 "register_operand")
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(vec_concat:V8SI
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