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pa.c: Use a register name...
* pa.c: Use a register name, not a raw immediate in branch,
compare/clear, sub, subb, uaddcm and vshd instructions.
* pa.md: Likewise.
From-SVN: r26404
This commit is contained in:
Jeffrey A Law
Jeff Law
parent
f24d52e1ab
commit
3b5e5fb33f
@ -10,6 +10,12 @@ Tue Apr 13 05:04:59 1999 Richard Earnshaw (rearnsha@arm.com)
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Tue Apr 13 02:11:11 1999 Jeffrey A Law (law@cygnus.com)
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* pa.c: Use a register name, not a raw immediate in branch,
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compare/clear, sub, subb, uaddcm and vshd instructions.
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* pa.md: Likewise.
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* pa.md, pa.h, ee.asm, ee_fp.asm, lib2funcs.asm: Likewise.
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* pa.c: Use a register name, not a raw immediate in "bv" instructions.
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* pa.md, pa.h, ee.asm, ee_fp.asm, lib2funcs.asm: Likewise.
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@ -4472,7 +4472,7 @@ output_cbranch (operands, nullify, length, negated, insn)
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else
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strcat (buf, "%S3");
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if (useskip)
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strcat (buf, " %2,%r1,0");
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strcat (buf, " %2,%r1,%%r0");
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else if (nullify)
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strcat (buf, ",n %2,%r1,%0");
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else
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@ -4494,7 +4494,7 @@ output_cbranch (operands, nullify, length, negated, insn)
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strcat (buf, "%S3");
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else
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strcat (buf, "%B3");
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strcat (buf, ",n %2,%r1,.+12\n\tbl %0,0");
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strcat (buf, ",n %2,%r1,.+12\n\tb %0");
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}
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/* Handle short backwards branch with an unfilled delay slot.
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Using a comb;nop rather than comiclr;bl saves 1 cycle for both
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@ -4519,9 +4519,9 @@ output_cbranch (operands, nullify, length, negated, insn)
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else
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strcat (buf, "%B3");
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if (nullify)
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strcat (buf, " %2,%r1,0\n\tbl,n %0,0");
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strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
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else
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strcat (buf, " %2,%r1,0\n\tbl %0,0");
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strcat (buf, " %2,%r1,%%r0\n\tb %0");
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}
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break;
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@ -4654,7 +4654,7 @@ output_bb (operands, nullify, length, negated, insn, which)
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else
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strcat (buf, "<");
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if (useskip)
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strcat (buf, " %0,%1,1,0");
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strcat (buf, " %0,%1,1,%%r0");
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else if (nullify && negated)
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strcat (buf, ",n %0,%1,%3");
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else if (nullify && ! negated)
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@ -4682,9 +4682,9 @@ output_bb (operands, nullify, length, negated, insn, which)
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else
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strcat (buf, ">=");
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if (negated)
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strcat (buf, ",n %0,%1,.+12\n\tbl %3,0");
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strcat (buf, ",n %0,%1,.+12\n\tb %3");
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else
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strcat (buf, ",n %0,%1,.+12\n\tbl %2,0");
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strcat (buf, ",n %0,%1,.+12\n\tb %2");
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}
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/* Handle short backwards branch with an unfilled delay slot.
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Using a bb;nop rather than extrs;bl saves 1 cycle for both
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@ -4715,13 +4715,13 @@ output_bb (operands, nullify, length, negated, insn, which)
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else
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strcat (buf, ">=");
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if (nullify && negated)
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strcat (buf, " %0,%1,1,0\n\tbl,n %3,0");
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strcat (buf, " %0,%1,1,%%r0\n\tbn %3");
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else if (nullify && ! negated)
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strcat (buf, " %0,%1,1,0\n\tbl,n %2,0");
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strcat (buf, " %0,%1,1,%%r0\n\tbn %2");
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else if (negated)
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strcat (buf, " %0,%1,1,0\n\tbl %3,0");
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strcat (buf, " %0,%1,1,%%r0\n\tb %3");
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else
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strcat (buf, " %0,%1,1,0\n\tbl %2,0");
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strcat (buf, " %0,%1,1,%%r0\n\tb %2");
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}
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break;
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@ -4792,7 +4792,7 @@ output_bvb (operands, nullify, length, negated, insn, which)
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else
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strcat (buf, "<");
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if (useskip)
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strcat (buf, " %0,1,0");
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strcat (buf, " %0,1,%%r0");
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else if (nullify && negated)
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strcat (buf, ",n %0,%3");
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else if (nullify && ! negated)
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@ -4820,9 +4820,9 @@ output_bvb (operands, nullify, length, negated, insn, which)
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else
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strcat (buf, ">=");
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if (negated)
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strcat (buf, ",n %0,.+12\n\tbl %3,0");
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strcat (buf, ",n %0,.+12\n\tb %3");
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else
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strcat (buf, ",n %0,.+12\n\tbl %2,0");
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strcat (buf, ",n %0,.+12\n\tb %2");
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}
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/* Handle short backwards branch with an unfilled delay slot.
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Using a bb;nop rather than extrs;bl saves 1 cycle for both
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@ -4853,13 +4853,13 @@ output_bvb (operands, nullify, length, negated, insn, which)
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else
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strcat (buf, ">=");
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if (nullify && negated)
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strcat (buf, " %0,1,0\n\tbl,n %3,0");
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strcat (buf, " %0,1,%%r0\n\tbn %3");
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else if (nullify && ! negated)
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strcat (buf, " %0,1,0\n\tbl,n %2,0");
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strcat (buf, " %0,1,%%r0\n\tbn %2");
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else if (negated)
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strcat (buf, " %0,1,0\n\tbl %3,0");
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strcat (buf, " %0,1,%%r0\n\tb %3");
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else
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strcat (buf, " %0,1,0\n\tbl %2,0");
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strcat (buf, " %0,1,%%r0\n\tb %2");
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}
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break;
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@ -4928,7 +4928,7 @@ output_dbra (operands, insn, which_alternative)
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if (dbr_sequence_length () != 0
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&& ! forward_branch_p (insn)
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&& nullify)
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return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
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return "addib,%N2,n %1,%0,.+12\n\tb %3";
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/* Handle short backwards branch with an unfilled delay slot.
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Using a addb;nop rather than addi;bl saves 1 cycle for both
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taken and untaken branches. */
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@ -4941,9 +4941,9 @@ output_dbra (operands, insn, which_alternative)
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/* Handle normal cases. */
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if (nullify)
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return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
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return "addi,%N2 %1,%0,%0\n\tb,n %3";
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else
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return "addi,%N2 %1,%0,%0\n\tbl %3,0";
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return "addi,%N2 %1,%0,%0\n\tb %3";
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}
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else
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abort();
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@ -4957,9 +4957,9 @@ output_dbra (operands, insn, which_alternative)
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output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
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output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
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if (get_attr_length (insn) == 24)
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return "comb,%S2 0,%4,%3\n\tfldws -16(%%r30),%0";
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return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
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else
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return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(%%r30),%0";
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return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
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}
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/* Deal with gross reload from memory case. */
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else
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@ -4970,7 +4970,7 @@ output_dbra (operands, insn, which_alternative)
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if (get_attr_length (insn) == 12)
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return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
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else
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return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
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return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
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}
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}
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@ -5035,7 +5035,7 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
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if (dbr_sequence_length () != 0
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&& ! forward_branch_p (insn)
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&& nullify)
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return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
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return "movb,%N2,n %1,%0,.+12\n\tb %3";
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/* Handle short backwards branch with an unfilled delay slot.
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Using a movb;nop rather than or;bl saves 1 cycle for both
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@ -5048,9 +5048,9 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
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return "movb,%C2 %1,%0,%3%#";
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/* Handle normal cases. */
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if (nullify)
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return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
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return "or,%N2 %1,%%r0,%0\n\tb,n %3";
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else
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return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
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return "or,%N2 %1,%%r0,%0\n\tb %3";
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}
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else
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abort();
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@ -5063,9 +5063,9 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
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the FP register from MEM from within the branch's delay slot. */
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output_asm_insn ("stw %1,-16(%%r30)",operands);
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if (get_attr_length (insn) == 12)
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return "comb,%S2 0,%1,%3\n\tfldws -16(%%r30),%0";
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return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
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else
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return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(%%r30),%0";
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return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
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}
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/* Deal with gross reload from memory case. */
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else if (which_alternative == 2)
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@ -5073,17 +5073,17 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
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/* Reload loop counter from memory, the store back to memory
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happens in the branch's delay slot. */
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if (get_attr_length (insn) == 8)
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return "comb,%S2 0,%1,%3\n\tstw %1,%0";
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return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
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else
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return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
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return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
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}
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/* Handle SAR as a destination. */
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else
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{
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if (get_attr_length (insn) == 8)
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return "comb,%S2 0,%1,%3\n\tmtsar %r1";
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return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
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else
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return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tmtsar %r1";
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return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
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}
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}
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@ -5157,7 +5157,7 @@ output_millicode_call (insn, call_dest)
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output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
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/* Get our return address into %r31. */
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output_asm_insn ("blr 0,%%r31", xoperands);
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output_asm_insn ("blr %%r0,%%r31", xoperands);
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/* Jump to our target address in %r29. */
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output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
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@ -5415,7 +5415,7 @@ output_call (insn, call_dest)
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output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
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/* Get the return address into %r31. */
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output_asm_insn ("blr 0,%%r31", xoperands);
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output_asm_insn ("blr %%r0,%%r31", xoperands);
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/* Branch to our target which is in %r1. */
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output_asm_insn ("bv %%r0(%%r1)", xoperands);
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@ -5823,17 +5823,17 @@ output_parallel_movb (operands, length)
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/* Nothing in the delay slot, fake it by putting the combined
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insn (the copy or add) in the delay slot of a bl. */
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if (GET_CODE (operands[1]) == CONST_INT)
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return "bl %2,0\n\tldi %1,%0";
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return "b %2\n\tldi %1,%0";
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else
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return "bl %2,0\n\tcopy %1,%0";
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return "b %2\n\tcopy %1,%0";
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}
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else
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{
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/* Something in the delay slot, but we've got a long branch. */
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if (GET_CODE (operands[1]) == CONST_INT)
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return "ldi %1,%0\n\tbl %2,0";
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return "ldi %1,%0\n\tb %2";
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else
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return "copy %1,%0\n\tbl %2,0";
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return "copy %1,%0\n\tb %2";
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}
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}
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@ -5858,12 +5858,12 @@ output_parallel_addb (operands, length)
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{
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/* Nothing in the delay slot, fake it by putting the combined
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insn (the copy or add) in the delay slot of a bl. */
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return "bl %3,0\n\tadd%I1 %1,%0,%0";
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return "b %3\n\tadd%I1 %1,%0,%0";
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}
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else
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{
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/* Something in the delay slot, but we've got a long branch. */
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return "add%I1 %1,%0,%0\n\tbl %3,0";
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return "add%I1 %1,%0,%0\n\tb %3";
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}
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}
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@ -3478,7 +3478,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(neg:DI (match_operand:DI 1 "register_operand" "r")))]
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""
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"sub 0,%R1,%R0\;subb 0,%1,%0"
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"sub %%r0,%R1,%R0\;subb %%r0,%1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "8")])
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@ -3486,7 +3486,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "register_operand" "r")))]
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""
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"sub 0,%1,%0"
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"sub %%r0,%1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "4")])
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@ -3504,7 +3504,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(not:DI (match_operand:DI 1 "register_operand" "r")))]
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""
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"uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
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"uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
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[(set_attr "type" "unary")
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(set_attr "length" "8")])
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@ -3512,7 +3512,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(not:SI (match_operand:SI 1 "register_operand" "r")))]
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""
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"uaddcm 0,%1,%0"
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"uaddcm %%r0,%1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "4")])
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@ -3877,7 +3877,7 @@
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(match_operand:SI 2 "arith32_operand" "q,n")))]
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""
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"@
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vshd 0,%1,%0
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vshd %%r0,%1,%0
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extru %1,%P2,%L2,%0"
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[(set_attr "type" "shift")
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(set_attr "length" "4")])
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