mirror of
git://gcc.gnu.org/git/gcc.git
synced 2025-04-05 10:30:55 +08:00
or1k: gcc: initial support for openrisc
2018-11-09 Stafford Horne <shorne@gmail.com> Richard Henderson <rth@twiddle.net> Joel Sherrill <joel@rtems.org> * common/config/or1k/or1k-common.c: New file. * config/or1k/*: New. * config.gcc (or1k*-*-*): New. * configure.ac (or1k*-*-*): New test for openrisc tls. * configure: Regenerated. * doc/install.texi: Document OpenRISC triplets. * doc/invoke.texi: Document OpenRISC arguments. * doc/md.texi: Document OpenRISC. Co-Authored-By: Joel Sherrill <joel@rtems.org> Co-Authored-By: Richard Henderson <rth@twiddle.net> From-SVN: r265963
This commit is contained in:
Stafford Horne
Stafford Horne
parent
1d6ff15057
commit
3965b35f34
@ -1,3 +1,16 @@
|
||||
2018-11-09 Stafford Horne <shorne@gmail.com>
|
||||
Richard Henderson <rth@twiddle.net>
|
||||
Joel Sherrill <joel@rtems.org>
|
||||
|
||||
* common/config/or1k/or1k-common.c: New file.
|
||||
* config/or1k/*: New.
|
||||
* config.gcc (or1k*-*-*): New.
|
||||
* configure.ac (or1k*-*-*): New test for openrisc tls.
|
||||
* configure: Regenerated.
|
||||
* doc/install.texi: Document OpenRISC triplets.
|
||||
* doc/invoke.texi: Document OpenRISC arguments.
|
||||
* doc/md.texi: Document OpenRISC.
|
||||
|
||||
2018-11-09 Richard Earnshaw <rearnsha@arm.com>
|
||||
|
||||
* config/arm/arm-cpus.in (arm7tdmi): Add an alias for arm7tdmi-s.
|
||||
|
||||
41
gcc/common/config/or1k/or1k-common.c
Normal file
41
gcc/common/config/or1k/or1k-common.c
Normal file
@ -0,0 +1,41 @@
|
||||
/* Common hooks for OpenRISC
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config.h"
|
||||
#include "system.h"
|
||||
#include "coretypes.h"
|
||||
#include "diagnostic-core.h"
|
||||
#include "tm.h"
|
||||
#include "common/common-target.h"
|
||||
#include "common/common-target-def.h"
|
||||
#include "opts.h"
|
||||
#include "flags.h"
|
||||
|
||||
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
|
||||
static const struct default_options or1k_option_optimization_table[] =
|
||||
{
|
||||
/* Enable section anchors by default at -O1 or higher. */
|
||||
{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
|
||||
{ OPT_LEVELS_NONE, 0, NULL, 0 }
|
||||
};
|
||||
|
||||
#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
||||
#define TARGET_OPTION_OPTIMIZATION_TABLE or1k_option_optimization_table
|
||||
|
||||
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
||||
@ -484,6 +484,9 @@ nios2-*-*)
|
||||
nvptx-*-*)
|
||||
cpu_type=nvptx
|
||||
;;
|
||||
or1k*-*-*)
|
||||
cpu_type=or1k
|
||||
;;
|
||||
powerpc*-*-*spe*)
|
||||
cpu_type=powerpcspe
|
||||
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
|
||||
@ -2490,6 +2493,48 @@ nvptx-*)
|
||||
tm_file="${tm_file} nvptx/offload.h"
|
||||
fi
|
||||
;;
|
||||
or1k*-*-*)
|
||||
tm_file="elfos.h ${tm_file}"
|
||||
tmake_file="${tmake_file} or1k/t-or1k"
|
||||
# Force .init_array support. The configure script cannot always
|
||||
# automatically detect that GAS supports it, yet we require it.
|
||||
gcc_cv_initfini_array=yes
|
||||
|
||||
# Handle --with-multilib-list=...
|
||||
or1k_multilibs="${with_multilib_list}"
|
||||
if test "$or1k_multilibs" = "default"; then
|
||||
or1k_multilibs="mcmov,msoft-mul,msoft-div"
|
||||
fi
|
||||
or1k_multilibs=`echo $or1k_multilibs | sed -e 's/,/ /g'`
|
||||
for or1k_multilib in ${or1k_multilibs}; do
|
||||
case ${or1k_multilib} in
|
||||
mcmov | msext | msfimm | \
|
||||
mhard-div | mhard-mul | \
|
||||
msoft-div | msoft-mul )
|
||||
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
|
||||
;;
|
||||
*)
|
||||
echo "--with-multilib-list=${with_multilib_list} not supported."
|
||||
exit 1
|
||||
esac
|
||||
done
|
||||
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
|
||||
|
||||
case ${target} in
|
||||
or1k*-*-linux*)
|
||||
tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h"
|
||||
tm_file="${tm_file} or1k/linux.h"
|
||||
;;
|
||||
or1k*-*-elf*)
|
||||
tm_file="${tm_file} newlib-stdint.h or1k/elf.h"
|
||||
extra_options="${extra_options} or1k/elf.opt"
|
||||
;;
|
||||
or1k*-*-rtems*)
|
||||
tm_file="${tm_file} newlib-stdint.h or1k/rtems.h rtems.h"
|
||||
tmake_file="${tmake_file} or1k/t-rtems"
|
||||
;;
|
||||
esac
|
||||
;;
|
||||
pdp11-*-*)
|
||||
tm_file="${tm_file} newlib-stdint.h"
|
||||
use_gcc_stdint=wrap
|
||||
|
||||
55
gcc/config/or1k/constraints.md
Normal file
55
gcc/config/or1k/constraints.md
Normal file
@ -0,0 +1,55 @@
|
||||
;; Constraint definitions for OpenRISC
|
||||
;; Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
;; Contributed by Stafford Horne
|
||||
|
||||
;; This file is part of GCC.
|
||||
|
||||
;; GCC is free software; you can redistribute it and/or modify it
|
||||
;; under the terms of the GNU General Public License as published
|
||||
;; by the Free Software Foundation; either version 3, or (at your
|
||||
;; option) any later version.
|
||||
|
||||
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
;; License for more details.
|
||||
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Constraints
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
; We use:
|
||||
; c - sibcall registers
|
||||
; I - constant signed 16-bit
|
||||
; K - constant unsigned 16-bit
|
||||
; M - constant signed 16-bit shifted left 16-bits (l.movhi)
|
||||
; O - constant zero
|
||||
|
||||
(define_register_constraint "c" "SIBCALL_REGS"
|
||||
"Registers which can hold a sibling call address")
|
||||
|
||||
;; Immediates
|
||||
(define_constraint "I"
|
||||
"A signed 16-bit immediate in the range -32768 to 32767."
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, -32768, 32767)")))
|
||||
|
||||
(define_constraint "K"
|
||||
"An unsigned 16-bit immediate in the range 0 to 0xffff."
|
||||
(and (match_code "const_int")
|
||||
(match_test "IN_RANGE (ival, 0, 65535)")))
|
||||
|
||||
(define_constraint "M"
|
||||
"A shifted signed 16-bit constant suitable for l.movhi."
|
||||
(and (match_code "const_int")
|
||||
(match_test "(ival & 0xffff) == 0
|
||||
&& (ival >> 31 == -1 || ival >> 31 == 0)")))
|
||||
|
||||
(define_constraint "O"
|
||||
"The constant zero"
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival == 0")))
|
||||
42
gcc/config/or1k/elf.h
Normal file
42
gcc/config/or1k/elf.h
Normal file
@ -0,0 +1,42 @@
|
||||
/* Target Newlib Definitions for OpenRISC.
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
Contributed by Stafford Horne.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef GCC_OR1K_ELF_H
|
||||
#define GCC_OR1K_ELF_H
|
||||
|
||||
#undef LIB_SPEC
|
||||
#define LIB_SPEC "--start-group -lc -lor1k " \
|
||||
"%{mboard=*:-lboard-%*; :-lboard-or1ksim} --end-group"
|
||||
|
||||
#undef LINK_SPEC
|
||||
#define LINK_SPEC "%{h*} \
|
||||
%{static:-Bstatic} \
|
||||
%{shared:-shared} \
|
||||
%{symbolic:-Bsymbolic} \
|
||||
%{!static:%{rdynamic:-export-dynamic}} \
|
||||
--entry=0x100"
|
||||
|
||||
#undef STARTFILE_SPEC
|
||||
#define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
|
||||
|
||||
#undef ENDFILE_SPEC
|
||||
#define ENDFILE_SPEC "crtend.o%s"
|
||||
|
||||
#endif /* GCC_OR1K_ELF_H */
|
||||
33
gcc/config/or1k/elf.opt
Normal file
33
gcc/config/or1k/elf.opt
Normal file
@ -0,0 +1,33 @@
|
||||
; OpenRISC command line options for newlib binaries
|
||||
|
||||
; Copyright (C) 2010-2018 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 3, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
; See the GCC internals manual (options.texi) for a description of
|
||||
; this file's format.
|
||||
|
||||
; Please try to keep this file in ASCII collating order.
|
||||
|
||||
mboard=
|
||||
Target RejectNegative Joined
|
||||
Configure board specific runtime.
|
||||
|
||||
mnewlib
|
||||
Target RejectNegative
|
||||
For compatibility, it's always newlib for elf now.
|
||||
|
||||
45
gcc/config/or1k/linux.h
Normal file
45
gcc/config/or1k/linux.h
Normal file
@ -0,0 +1,45 @@
|
||||
/* Linux Definitions for OpenRISC.
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
Contributed by Stafford Horne.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef GCC_OR1K_LINUX_H
|
||||
#define GCC_OR1K_LINUX_H
|
||||
|
||||
/* elfos.h should have already been included. Now just override
|
||||
any conflicting definitions and add any extras. */
|
||||
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
GNU_USER_TARGET_OS_CPP_BUILTINS ()
|
||||
|
||||
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-or1k.so.1"
|
||||
|
||||
#undef MUSL_DYNAMIC_LINKER
|
||||
#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-or1k.so.1"
|
||||
|
||||
#undef LINK_SPEC
|
||||
#define LINK_SPEC "%{h*} \
|
||||
%{static:-Bstatic} \
|
||||
%{shared:-shared} \
|
||||
%{symbolic:-Bsymbolic} \
|
||||
%{!static:%{!static-pie: \
|
||||
%{rdynamic:-export-dynamic} \
|
||||
%{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
|
||||
%{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
|
||||
|
||||
#endif /* GCC_OR1K_LINUX_H */
|
||||
38
gcc/config/or1k/or1k-protos.h
Normal file
38
gcc/config/or1k/or1k-protos.h
Normal file
@ -0,0 +1,38 @@
|
||||
/* Prototypes for OpenRISC functions used in the md file & elsewhere.
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
extern HOST_WIDE_INT or1k_initial_elimination_offset (int, int);
|
||||
extern void or1k_expand_prologue (void);
|
||||
extern void or1k_expand_epilogue (void);
|
||||
extern void or1k_expand_eh_return (rtx);
|
||||
extern rtx or1k_initial_frame_addr (void);
|
||||
extern rtx or1k_dynamic_chain_addr (rtx);
|
||||
extern rtx or1k_return_addr (int, rtx);
|
||||
extern void or1k_expand_move (machine_mode, rtx, rtx);
|
||||
extern void or1k_expand_compare (rtx *);
|
||||
extern void or1k_expand_call (rtx, rtx, rtx, bool);
|
||||
|
||||
#ifdef RTX_CODE
|
||||
void or1k_expand_atomic_compare_and_swap (rtx operands[]);
|
||||
void or1k_expand_atomic_compare_and_swap_qihi (rtx operands[]);
|
||||
void or1k_expand_atomic_exchange (rtx operands[]);
|
||||
void or1k_expand_atomic_exchange_qihi (rtx operands[]);
|
||||
void or1k_expand_atomic_op (rtx_code, rtx, rtx, rtx, rtx);
|
||||
void or1k_expand_atomic_op_qihi (rtx_code, rtx, rtx, rtx, rtx);
|
||||
#endif
|
||||
2183
gcc/config/or1k/or1k.c
Normal file
2183
gcc/config/or1k/or1k.c
Normal file
File diff suppressed because it is too large
Load Diff
392
gcc/config/or1k/or1k.h
Normal file
392
gcc/config/or1k/or1k.h
Normal file
@ -0,0 +1,392 @@
|
||||
/* Target Definitions for OpenRISC.
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
Contributed by Stafford Horne.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef GCC_OR1K_H
|
||||
#define GCC_OR1K_H
|
||||
|
||||
/* Names to predefine in the preprocessor for this target machine. */
|
||||
#define TARGET_CPU_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_define ("__OR1K__"); \
|
||||
builtin_define ("__OR1K_DELAY__"); \
|
||||
builtin_define ("__or1k__"); \
|
||||
if (TARGET_CMOV) \
|
||||
builtin_define ("__or1k_cmov__"); \
|
||||
builtin_assert ("cpu=or1k"); \
|
||||
builtin_assert ("machine=or1k"); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* Storage layout. */
|
||||
|
||||
#define DEFAULT_SIGNED_CHAR 1
|
||||
#define BITS_BIG_ENDIAN 0
|
||||
#define BYTES_BIG_ENDIAN 1
|
||||
#define WORDS_BIG_ENDIAN 1
|
||||
#define BITS_PER_WORD 32
|
||||
#define UNITS_PER_WORD 4
|
||||
#define POINTER_SIZE 32
|
||||
#define BIGGEST_ALIGNMENT 32
|
||||
#define STRICT_ALIGNMENT 1
|
||||
#define FUNCTION_BOUNDARY 32
|
||||
#define PARM_BOUNDARY 32
|
||||
#define STACK_BOUNDARY 32
|
||||
#define PREFERRED_STACK_BOUNDARY 32
|
||||
#define MAX_FIXED_MODE_SIZE 64
|
||||
|
||||
/* Layout of source language data types. */
|
||||
|
||||
#define INT_TYPE_SIZE 32
|
||||
#define SHORT_TYPE_SIZE 16
|
||||
#define LONG_TYPE_SIZE 32
|
||||
#define LONG_LONG_TYPE_SIZE 64
|
||||
#define FLOAT_TYPE_SIZE 32
|
||||
#define DOUBLE_TYPE_SIZE 64
|
||||
#define LONG_DOUBLE_TYPE_SIZE 64
|
||||
#define WCHAR_TYPE_SIZE 32
|
||||
|
||||
#undef SIZE_TYPE
|
||||
#define SIZE_TYPE "unsigned int"
|
||||
|
||||
#undef PTRDIFF_TYPE
|
||||
#define PTRDIFF_TYPE "int"
|
||||
|
||||
#undef WCHAR_TYPE
|
||||
#define WCHAR_TYPE "unsigned int"
|
||||
|
||||
/* Describing Relative Costs of Operations. */
|
||||
#define MOVE_MAX 4
|
||||
#define SLOW_BYTE_ACCESS 1
|
||||
|
||||
/* Register usage, class and contents. */
|
||||
|
||||
/* In OpenRISC there are 32 general purpose registers with the following
|
||||
designations:
|
||||
|
||||
r0 always 0
|
||||
r1 stack pointer
|
||||
r2 frame pointer (optional)
|
||||
r3 arg 0
|
||||
r4 arg 1
|
||||
r5 arg 2
|
||||
r6 arg 3
|
||||
r7 arg 4
|
||||
r8 arg 5
|
||||
r9 function call return link address
|
||||
r10 thread local storage
|
||||
r11 function return value & static chain
|
||||
r12 function return value high (upper 64-bit)
|
||||
r13 temporary (used in prologue and epilogue)
|
||||
r14 callee saved
|
||||
r15 temporary
|
||||
r16 callee saved & pic base register
|
||||
r17 temporary
|
||||
r18 callee saved
|
||||
r19 temporary
|
||||
r20 callee saved
|
||||
r21 temporary
|
||||
r22 callee saved
|
||||
r23 temporary
|
||||
r24 callee saved
|
||||
r25 temporary
|
||||
r26 callee saved
|
||||
r27 temporary
|
||||
r28 callee saved
|
||||
r29 temporary
|
||||
r30 callee saved
|
||||
r31 temporary
|
||||
|
||||
r32 soft argument pointer
|
||||
r33 soft frame pointer
|
||||
r34 SR[F] (bit) register
|
||||
|
||||
This ABI has no adjacent call-saved register, which means that
|
||||
DImode/DFmode pseudos cannot be call-saved and will always be
|
||||
spilled across calls. To solve this without changing the ABI,
|
||||
remap the compiler internal register numbers to place the even
|
||||
call-saved registers r16-r30 in 24-31, and the odd call-clobbered
|
||||
registers r17-r31 in 16-23. */
|
||||
|
||||
#define FIRST_PSEUDO_REGISTER 35
|
||||
|
||||
#define HW_TO_GCC_REGNO(X) \
|
||||
((X) < 16 || (X) > 31 ? (X) \
|
||||
: (X) & 1 ? ((X) - 16) / 2 + 16 \
|
||||
: ((X) - 16) / 2 + 24)
|
||||
|
||||
#define GCC_TO_HW_REGNO(X) \
|
||||
((X) < 16 || (X) > 31 ? (X) \
|
||||
: (X) < 24 ? ((X) - 16) * 2 + 17 \
|
||||
: ((X) - 24) * 2 + 16)
|
||||
|
||||
#define DBX_REGISTER_NUMBER(X) GCC_TO_HW_REGNO(X)
|
||||
|
||||
#define REGISTER_NAMES { \
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
|
||||
"r17", "r19", "r21", "r23", "r25", "r27", "r29", "r31", \
|
||||
"r16", "r18", "r20", "r22", "r24", "r26", "r28", "r30", \
|
||||
"?ap", "?fp", "?sr_f" }
|
||||
|
||||
#define FIXED_REGISTERS \
|
||||
{ 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1 }
|
||||
|
||||
/* Caller saved/temporary registers + args + fixed */
|
||||
#define CALL_USED_REGISTERS \
|
||||
{ 1, 1, 0, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1 }
|
||||
|
||||
/* List the order in which to allocate registers. Each register must
|
||||
be listed once, even those in FIXED_REGISTERS.
|
||||
|
||||
??? Note that placing REAL_PIC_OFFSET_TABLE_REGNUM (r16 = 24) first
|
||||
happens to make it most likely selected *as* the pic register when
|
||||
compiling without optimization, simply because the pic pseudo happens
|
||||
to be allocated with the lowest pseudo regno. */
|
||||
|
||||
#define REG_ALLOC_ORDER { \
|
||||
16, 17, 18, 19, 20, 21, 22, 23, /* r17-r31 (odd), non-saved */ \
|
||||
13, 15, /* non-saved */ \
|
||||
12, 11, /* non-saved return values */ \
|
||||
8, 7, 6, 5, 4, 3, /* non-saved argument regs */ \
|
||||
24, /* r16, saved, pic reg */ \
|
||||
25, 26, 27, 28, 29, 30, 31, /* r18-r31 (even), saved */ \
|
||||
14, /* r14, saved */ \
|
||||
2, /* saved hard frame pointer */ \
|
||||
9, /* saved return address */ \
|
||||
0, /* fixed zero reg */ \
|
||||
1, /* fixed stack pointer */ \
|
||||
10, /* fixed thread pointer */ \
|
||||
32, 33, 34, /* fixed ap, fp, sr[f], */ \
|
||||
}
|
||||
|
||||
enum reg_class
|
||||
{
|
||||
NO_REGS,
|
||||
SIBCALL_REGS,
|
||||
GENERAL_REGS,
|
||||
FLAG_REGS,
|
||||
ALL_REGS,
|
||||
LIM_REG_CLASSES
|
||||
};
|
||||
|
||||
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
||||
|
||||
#define REG_CLASS_NAMES { \
|
||||
"NO_REGS", \
|
||||
"SIBCALL_REGS", \
|
||||
"GENERAL_REGS", \
|
||||
"FLAG_REGS", \
|
||||
"ALL_REGS" }
|
||||
|
||||
/* The SIBCALL_REGS must be call-clobbered, and not used as a temporary
|
||||
in the epilogue. This excludes R9 (LR), R11 (STATIC_CHAIN), and
|
||||
R13 (PE_TMP_REGNUM). */
|
||||
#define SIBCALL_REGS_MASK 0x00ff95f8u
|
||||
|
||||
#define REG_CLASS_CONTENTS \
|
||||
{ { 0x00000000, 0x00000000 }, \
|
||||
{ SIBCALL_REGS_MASK, 0 }, \
|
||||
{ 0xffffffff, 0x00000003 }, \
|
||||
{ 0x00000000, 0x00000004 }, \
|
||||
{ 0xffffffff, 0x00000007 } \
|
||||
}
|
||||
|
||||
/* A C expression whose value is a register class containing hard
|
||||
register REGNO. In general there is more that one such class;
|
||||
choose a class which is "minimal", meaning that no smaller class
|
||||
also contains the register. */
|
||||
#define REGNO_REG_CLASS(REGNO) \
|
||||
((REGNO) >= SR_F_REGNUM ? FLAG_REGS \
|
||||
: (REGNO) < 32 && ((SIBCALL_REGS_MASK >> (REGNO)) & 1) ? SIBCALL_REGS \
|
||||
: GENERAL_REGS)
|
||||
|
||||
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
|
||||
do { \
|
||||
if (GET_MODE_CLASS (MODE) == MODE_INT \
|
||||
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
|
||||
(MODE) = word_mode; \
|
||||
} while (0)
|
||||
|
||||
/* A macro whose definition is the name of the class to which a valid
|
||||
base register must belong. A base register is one used in an
|
||||
address which is the register value plus a displacement. */
|
||||
#define BASE_REG_CLASS GENERAL_REGS
|
||||
|
||||
#define INDEX_REG_CLASS NO_REGS
|
||||
|
||||
/* Assembly definitions. */
|
||||
|
||||
#define ASM_APP_ON ""
|
||||
#define ASM_APP_OFF ""
|
||||
|
||||
#define ASM_COMMENT_START "# "
|
||||
|
||||
#define GLOBAL_ASM_OP "\t.global\t"
|
||||
#define TEXT_SECTION_ASM_OP "\t.section\t.text"
|
||||
#define DATA_SECTION_ASM_OP "\t.section\t.data"
|
||||
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
|
||||
#define SBSS_SECTION_ASM_OP "\t.section\t.sbss"
|
||||
|
||||
/* This is how to output an assembler line
|
||||
that says to advance the location counter
|
||||
to a multiple of 2**LOG bytes. */
|
||||
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
|
||||
do \
|
||||
{ \
|
||||
if ((LOG) != 0) \
|
||||
fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* This is used in crtstuff to create call stubs in the
|
||||
_init() and _fini() functions. Defining this here saves
|
||||
a few bytes created by the dummy call_xxx() functions. */
|
||||
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
|
||||
asm (SECTION_OP "\n" \
|
||||
" l.jal " #FUNC "\n" \
|
||||
" l.nop\n" \
|
||||
" .previous");
|
||||
|
||||
|
||||
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) (code == '#')
|
||||
|
||||
/* Calling convention definitions. */
|
||||
#define CUMULATIVE_ARGS int
|
||||
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
|
||||
do { (CUM) = 0; } while (0)
|
||||
|
||||
|
||||
/* Trampolines, for nested functions */
|
||||
#define TRAMPOLINE_SIZE 20
|
||||
#define TRAMPOLINE_ALIGNMENT 32
|
||||
|
||||
/* Pointer mode */
|
||||
#define Pmode SImode
|
||||
#define FUNCTION_MODE SImode
|
||||
#define STACK_POINTER_REGNUM SP_REGNUM
|
||||
#define FRAME_POINTER_REGNUM SFP_REGNUM
|
||||
#define HARD_FRAME_POINTER_REGNUM HFP_REGNUM
|
||||
#define STATIC_CHAIN_REGNUM RV_REGNUM
|
||||
|
||||
/* The register number of the arg pointer register, which is used to
|
||||
access the function's argument list. */
|
||||
#define ARG_POINTER_REGNUM AP_REGNUM
|
||||
|
||||
/* Position Independent Code. See or1k_init_pic_reg. */
|
||||
#define REAL_PIC_OFFSET_TABLE_REGNUM HW_TO_GCC_REGNO (16)
|
||||
|
||||
/* ??? Follow i386 in working around gimple costing estimation, which
|
||||
happens without properly initializing the pic_offset_table pseudo. */
|
||||
#define PIC_OFFSET_TABLE_REGNUM \
|
||||
(pic_offset_table_rtx ? INVALID_REGNUM : REAL_PIC_OFFSET_TABLE_REGNUM)
|
||||
|
||||
/* A C expression that is nonzero if REGNO is the number of a hard
|
||||
register in which function arguments are sometimes passed. */
|
||||
#define FUNCTION_ARG_REGNO_P(r) (r >= 3 && r <= 8)
|
||||
|
||||
#define MAX_REGS_PER_ADDRESS 1
|
||||
|
||||
/* The ELIMINABLE_REGS macro specifies a table of register pairs used to
|
||||
eliminate unneeded registers that point into the stack frame. Note,
|
||||
the only elimination attempted by the compiler is to replace references
|
||||
to the frame pointer with references to the stack pointer. */
|
||||
|
||||
#define ELIMINABLE_REGS \
|
||||
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
||||
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
|
||||
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
||||
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
|
||||
|
||||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||||
do { \
|
||||
(OFFSET) = or1k_initial_elimination_offset ((FROM), (TO)); \
|
||||
} while (0)
|
||||
|
||||
#define REGNO_OK_FOR_INDEX_P(REGNO) 0
|
||||
#define REGNO_OK_FOR_BASE_P(REGNO) ((REGNO) <= SFP_REGNUM)
|
||||
|
||||
/* If defined, the maximum amount of space required for outgoing
|
||||
arguments will be computed and placed into the variable
|
||||
'crtl->outgoing_args_size'. No space will be pushed
|
||||
onto the stack for each call; instead, the function prologue
|
||||
should increase the stack frame size by this amount. */
|
||||
#define ACCUMULATE_OUTGOING_ARGS 1
|
||||
|
||||
/* Stack layout and stack pointer usage. */
|
||||
|
||||
/* This plus ARG_POINTER_REGNUM points to the first word of incoming args. */
|
||||
#define FIRST_PARM_OFFSET(FNDECL) (0)
|
||||
|
||||
/* This plus STACK_POINTER_REGNUM points to the first work of outgoing args. */
|
||||
#define STACK_POINTER_OFFSET (0)
|
||||
|
||||
/* Define this macro if pushing a word onto the stack moves the stack
|
||||
pointer to a smaller address. */
|
||||
#define STACK_GROWS_DOWNWARD 1
|
||||
|
||||
#define FRAME_GROWS_DOWNWARD 1
|
||||
|
||||
/* An alias for a machine mode name. This is the machine mode that
|
||||
elements of a jump-table should have. */
|
||||
#define CASE_VECTOR_MODE SImode
|
||||
|
||||
#define STORE_FLAG_VALUE 1
|
||||
|
||||
/* Indicates how loads of narrow mode values are loaded into words. */
|
||||
#define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND)
|
||||
|
||||
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
|
||||
the stack pointer does not matter. */
|
||||
#define EXIT_IGNORE_STACK 1
|
||||
|
||||
/* Macros related to the access of the stack frame chain. */
|
||||
#define INITIAL_FRAME_ADDRESS_RTX or1k_initial_frame_addr ()
|
||||
#define DYNAMIC_CHAIN_ADDRESS or1k_dynamic_chain_addr
|
||||
#define RETURN_ADDR_RTX or1k_return_addr
|
||||
|
||||
/* Always pass the SYMBOL_REF for direct calls to the expanders. */
|
||||
#define NO_FUNCTION_CSE 1
|
||||
|
||||
/* Profiling */
|
||||
#define FUNCTION_PROFILER(FILE,LABELNO) (abort (), 0)
|
||||
|
||||
/* Dwarf 2 Support */
|
||||
#define DWARF2_DEBUGGING_INFO 1
|
||||
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
|
||||
#define DWARF_FRAME_RETURN_COLUMN LR_REGNUM
|
||||
|
||||
/* Describe how we implement __builtin_eh_return. */
|
||||
#define EH_RETURN_REGNUM HW_TO_GCC_REGNO (23)
|
||||
/* Use r25, r27, r29 and r31 (clobber regs) for exception data.
|
||||
Recall that these are remapped consecutively. */
|
||||
#define EH_RETURN_DATA_REGNO(N) \
|
||||
((N) < 4 ? HW_TO_GCC_REGNO (25) + (N) : INVALID_REGNUM)
|
||||
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM)
|
||||
|
||||
#endif /* GCC_OR1K_H */
|
||||
897
gcc/config/or1k/or1k.md
Normal file
897
gcc/config/or1k/or1k.md
Normal file
@ -0,0 +1,897 @@
|
||||
;; Machine description for OpenRISC
|
||||
;; Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
;; Contributed by Stafford Horne
|
||||
|
||||
;; This file is part of GCC.
|
||||
|
||||
;; GCC is free software; you can redistribute it and/or modify it
|
||||
;; under the terms of the GNU General Public License as published
|
||||
;; by the Free Software Foundation; either version 3, or (at your
|
||||
;; option) any later version.
|
||||
|
||||
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
;; License for more details.
|
||||
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; OpenRISC specific constraints, predicates and attributes
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(include "constraints.md")
|
||||
(include "predicates.md")
|
||||
|
||||
;; Register numbers
|
||||
(define_constants
|
||||
[(SP_REGNUM 1)
|
||||
(HFP_REGNUM 2)
|
||||
(LR_REGNUM 9)
|
||||
(TLS_REGNUM 10)
|
||||
(RV_REGNUM 11)
|
||||
(PE_TMP_REGNUM 13)
|
||||
(AP_REGNUM 32)
|
||||
(SFP_REGNUM 33)
|
||||
(SR_F_REGNUM 34)]
|
||||
)
|
||||
|
||||
(define_c_enum "unspec" [
|
||||
UNSPEC_SET_GOT
|
||||
UNSPEC_GOT
|
||||
UNSPEC_GOTOFF
|
||||
UNSPEC_TPOFF
|
||||
UNSPEC_GOTTPOFF
|
||||
UNSPEC_TLSGD
|
||||
UNSPEC_MSYNC
|
||||
])
|
||||
|
||||
(define_c_enum "unspecv" [
|
||||
UNSPECV_SET_GOT
|
||||
UNSPECV_LL
|
||||
UNSPECV_SC
|
||||
])
|
||||
|
||||
;; Instruction scheduler
|
||||
|
||||
; Most instructions are 4 bytes long.
|
||||
(define_attr "length" "" (const_int 4))
|
||||
|
||||
(define_attr "type"
|
||||
"alu,st,ld,control,multi"
|
||||
(const_string "alu"))
|
||||
|
||||
(define_attr "insn_support" "class1,sext,sfimm,shftimm" (const_string "class1"))
|
||||
|
||||
(define_attr "enabled" ""
|
||||
(cond [(eq_attr "insn_support" "class1") (const_int 1)
|
||||
(and (eq_attr "insn_support" "sext")
|
||||
(ne (symbol_ref "TARGET_SEXT") (const_int 0))) (const_int 1)
|
||||
(and (eq_attr "insn_support" "sfimm")
|
||||
(ne (symbol_ref "TARGET_SFIMM") (const_int 0))) (const_int 1)
|
||||
(and (eq_attr "insn_support" "shftimm")
|
||||
(ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)]
|
||||
(const_int 0)))
|
||||
|
||||
;; Describe a user's asm statement.
|
||||
(define_asm_attributes
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
(define_automaton "or1k")
|
||||
(define_cpu_unit "cpu" "or1k")
|
||||
(define_insn_reservation "alu" 1
|
||||
(eq_attr "type" "alu")
|
||||
"cpu")
|
||||
(define_insn_reservation "st" 1
|
||||
(eq_attr "type" "st")
|
||||
"cpu")
|
||||
(define_insn_reservation "ld" 3
|
||||
(eq_attr "type" "st")
|
||||
"cpu")
|
||||
(define_insn_reservation "control" 1
|
||||
(eq_attr "type" "control")
|
||||
"cpu")
|
||||
|
||||
; Define delay slots for any branch
|
||||
(define_delay (eq_attr "type" "control")
|
||||
[(eq_attr "type" "alu,st,ld") (nil) (nil)])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; nop instruction
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "nop"
|
||||
[(const_int 0)]
|
||||
""
|
||||
"l.nop")
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Arithmetic instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "addsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(plus:SI
|
||||
(match_operand:SI 1 "register_operand" "%r,r")
|
||||
(match_operand:SI 2 "reg_or_s16_operand" " r,I")))]
|
||||
""
|
||||
"@
|
||||
l.add\t%0, %1, %2
|
||||
l.addi\t%0, %1, %2")
|
||||
|
||||
(define_insn "mulsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(mult:SI
|
||||
(match_operand:SI 1 "register_operand" "%r,r")
|
||||
(match_operand:SI 2 "reg_or_s16_operand" " r,I")))]
|
||||
"!TARGET_SOFT_MUL"
|
||||
"@
|
||||
l.mul\t%0, %1, %2
|
||||
l.muli\t%0, %1, %2")
|
||||
|
||||
(define_insn "divsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(div:SI
|
||||
(match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))]
|
||||
"!TARGET_SOFT_DIV"
|
||||
"l.div\t%0, %1, %2")
|
||||
|
||||
(define_insn "udivsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(udiv:SI
|
||||
(match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))]
|
||||
"!TARGET_SOFT_DIV"
|
||||
"l.divu\t%0, %1, %2")
|
||||
|
||||
(define_insn "subsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(minus:SI
|
||||
(match_operand:SI 1 "reg_or_0_operand" "rO")
|
||||
(match_operand:SI 2 "register_operand" "r")))]
|
||||
""
|
||||
"l.sub\t%0, %r1, %2")
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Logical operators
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_code_iterator SHIFT [ashift ashiftrt lshiftrt])
|
||||
(define_code_attr shift_op [(ashift "ashl") (ashiftrt "ashr")
|
||||
(lshiftrt "lshr")])
|
||||
(define_code_attr shift_asm [(ashift "sll") (ashiftrt "sra")
|
||||
(lshiftrt "srl")])
|
||||
|
||||
(define_insn "<shift_op>si3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(SHIFT:SI (match_operand:SI 1 "register_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
|
||||
""
|
||||
"@
|
||||
l.<shift_asm>\t%0, %1, %2
|
||||
l.<shift_asm>i\t%0, %1, %2"
|
||||
[(set_attr "insn_support" "*,shftimm")])
|
||||
|
||||
(define_insn "rotrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
|
||||
(match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
|
||||
"TARGET_ROR"
|
||||
"@
|
||||
l.ror\t%0, %1, %2
|
||||
l.rori\t%0, %1, %2"
|
||||
[(set_attr "insn_support" "*,shftimm")])
|
||||
|
||||
(define_insn "andsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(and:SI
|
||||
(match_operand:SI 1 "register_operand" "%r,r")
|
||||
(match_operand:SI 2 "reg_or_u16_operand" " r,K")))]
|
||||
""
|
||||
"@
|
||||
l.and\t%0, %1, %2
|
||||
l.andi\t%0, %1, %2")
|
||||
|
||||
(define_insn "xorsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(xor:SI
|
||||
(match_operand:SI 1 "register_operand" "%r,r")
|
||||
(match_operand:SI 2 "reg_or_s16_operand" " r,I")))]
|
||||
""
|
||||
"@
|
||||
l.xor\t%0, %1, %2
|
||||
l.xori\t%0, %1, %2")
|
||||
|
||||
(define_insn "iorsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(ior:SI
|
||||
(match_operand:SI 1 "register_operand" "%r,r")
|
||||
(match_operand:SI 2 "reg_or_u16_operand" " r,K")))]
|
||||
""
|
||||
"@
|
||||
l.or\t%0, %1, %2
|
||||
l.ori\t%0, %1, %2")
|
||||
|
||||
(define_expand "one_cmplsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(xor:SI (match_operand:SI 1 "register_operand" "") (const_int -1)))]
|
||||
""
|
||||
"")
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Move instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_mode_iterator I [QI HI SI])
|
||||
(define_mode_iterator I12 [QI HI])
|
||||
|
||||
(define_mode_attr ldst [(QI "b") (HI "h") (SI "w")])
|
||||
(define_mode_attr zext_andi [(QI "0xff") (HI "0xffff")])
|
||||
|
||||
(define_expand "mov<I:mode>"
|
||||
[(set (match_operand:I 0 "nonimmediate_operand" "")
|
||||
(match_operand:I 1 "general_operand" ""))]
|
||||
""
|
||||
{
|
||||
or1k_expand_move (<MODE>mode, operands[0], operands[1]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; 8-bit, 16-bit and 32-bit moves
|
||||
|
||||
(define_insn "*mov<I:mode>_internal"
|
||||
[(set (match_operand:I 0 "nonimmediate_operand" "=r,r,r,r, m,r")
|
||||
(match_operand:I 1 "input_operand" " r,M,K,I,rO,m"))]
|
||||
"register_operand (operands[0], <I:MODE>mode)
|
||||
|| reg_or_0_operand (operands[1], <I:MODE>mode)"
|
||||
"@
|
||||
l.or\t%0, %1, %1
|
||||
l.movhi\t%0, hi(%1)
|
||||
l.ori\t%0, r0, %1
|
||||
l.xori\t%0, r0, %1
|
||||
l.s<I:ldst>\t%0, %r1
|
||||
l.l<I:ldst>z\t%0, %1"
|
||||
[(set_attr "type" "alu,alu,alu,alu,st,ld")])
|
||||
|
||||
;; Hi/Low moves for constant and symbol loading
|
||||
|
||||
(define_insn "movsi_high"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(high:SI (match_operand:SI 1 "high_operand" "")))]
|
||||
""
|
||||
"l.movhi\t%0, %h1"
|
||||
[(set_attr "type" "alu")])
|
||||
|
||||
(define_insn "*movsi_lo_sum_iori"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "losum_ior_operand" "")))]
|
||||
""
|
||||
"l.ori\t%0, %1, %L2"
|
||||
[(set_attr "type" "alu")])
|
||||
|
||||
(define_insn "*movsi_lo_sum_addi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "losum_add_operand" "")))]
|
||||
""
|
||||
"l.addi\t%0, %1, %L2"
|
||||
[(set_attr "type" "alu")])
|
||||
|
||||
;; 64-bit moves
|
||||
;; ??? The clobber that emit_move_multi_word emits is arguably incorrect.
|
||||
;; Consider gcc.c-torture/execute/20030222-1.c, where a reg-reg DImode
|
||||
;; move gets register allocated to a no-op move. At which point the
|
||||
;; we actively clobber the input.
|
||||
|
||||
(define_expand "movdi"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "")
|
||||
(match_operand:DI 1 "general_operand" ""))]
|
||||
""
|
||||
{
|
||||
if (MEM_P (operands[0]) && !const0_operand(operands[1], DImode))
|
||||
operands[1] = force_reg (DImode, operands[1]);
|
||||
})
|
||||
|
||||
(define_insn_and_split "*movdi"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,o,r")
|
||||
(match_operand:DI 1 "general_operand" " r,o,rO,n"))]
|
||||
"register_operand (operands[0], DImode)
|
||||
|| reg_or_0_operand (operands[1], DImode)"
|
||||
"#"
|
||||
""
|
||||
[(const_int 0)]
|
||||
{
|
||||
rtx l0 = operand_subword (operands[0], 0, 0, DImode);
|
||||
rtx l1 = operand_subword (operands[1], 0, 0, DImode);
|
||||
rtx h0 = operand_subword (operands[0], 1, 0, DImode);
|
||||
rtx h1 = operand_subword (operands[1], 1, 0, DImode);
|
||||
|
||||
if (reload_completed && reg_overlap_mentioned_p (l0, h1))
|
||||
{
|
||||
gcc_assert (!reg_overlap_mentioned_p (h0, l1));
|
||||
emit_move_insn (h0, h1);
|
||||
emit_move_insn (l0, l1);
|
||||
}
|
||||
else
|
||||
{
|
||||
emit_move_insn (l0, l1);
|
||||
emit_move_insn (h0, h1);
|
||||
}
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Sign Extending
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
;; Zero extension can always be done with AND and an extending load.
|
||||
|
||||
(define_insn "zero_extend<mode>si2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
|
||||
""
|
||||
"@
|
||||
l.andi\t%0, %1, <zext_andi>
|
||||
l.l<ldst>z\t%0, %1")
|
||||
|
||||
;; Sign extension in registers is an optional extension, but the
|
||||
;; extending load is always available. If SEXT is not available,
|
||||
;; force the middle-end to do the expansion to shifts.
|
||||
|
||||
(define_insn "extend<mode>si2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
|
||||
"TARGET_SEXT"
|
||||
"@
|
||||
l.ext<ldst>s\t%0, %1
|
||||
l.l<ldst>s\t%0, %1")
|
||||
|
||||
(define_insn "*extend<mode>si2_mem"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(sign_extend:SI (match_operand:I12 1 "memory_operand" "m")))]
|
||||
""
|
||||
"l.l<ldst>s\t%0, %1")
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Compare instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
;; OpenRISC supports these integer comparisons:
|
||||
;;
|
||||
;; l.sfeq[i] - equality, r r or r i
|
||||
;; l.sfne[i] - not equal, r r or r i
|
||||
;; l.sflt{s,u}[i] - less than, signed or unsigned, r r or r i
|
||||
;; l.sfle{s,u}[i] - less than or equal, signed or unsigned, r r or r i
|
||||
;; l.sfgt{s,u}[i] - greater than, signed or unsigned, r r or r i
|
||||
;; l.sfge{s,u}[i] - greater than or equal, signed or unsigned, r r or r i
|
||||
;;
|
||||
;; EQ,NE,LT,LTU,LE,LEU,GT,GTU,GE,GEU
|
||||
;; We iterate through all of these
|
||||
;;
|
||||
|
||||
(define_code_iterator intcmpcc [ne eq lt ltu gt gtu ge le geu leu])
|
||||
(define_code_attr insn [(ne "ne") (eq "eq") (lt "lts") (ltu "ltu")
|
||||
(gt "gts") (gtu "gtu") (ge "ges") (le "les")
|
||||
(geu "geu") (leu "leu") ])
|
||||
|
||||
(define_insn "*sf_insn"
|
||||
[(set (reg:BI SR_F_REGNUM)
|
||||
(intcmpcc:BI (match_operand:SI 0 "reg_or_0_operand" "rO,rO")
|
||||
(match_operand:SI 1 "reg_or_s16_operand" "r,I")))]
|
||||
""
|
||||
"@
|
||||
l.sf<insn>\t%r0, %1
|
||||
l.sf<insn>i\t%r0, %1"
|
||||
[(set_attr "insn_support" "*,sfimm")])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Conditional Store instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_expand "cstoresi4"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(if_then_else:SI
|
||||
(match_operator 1 "comparison_operator"
|
||||
[(match_operand:SI 2 "reg_or_0_operand" "")
|
||||
(match_operand:SI 3 "reg_or_s16_operand" "")])
|
||||
(match_dup 0)
|
||||
(const_int 0)))]
|
||||
""
|
||||
{
|
||||
or1k_expand_compare (operands + 1);
|
||||
PUT_MODE (operands[1], SImode);
|
||||
emit_insn (gen_rtx_SET (operands[0], operands[1]));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Being able to "copy" SR_F to a general register is helpful for
|
||||
;; the atomic insns, wherein the usual usage is to test the success
|
||||
;; of the compare-and-swap. Representing the operation in this way,
|
||||
;; rather than exposing the cmov immediately, allows the optimizers
|
||||
;; to propagate the use of SR_F directly into a branch.
|
||||
|
||||
(define_expand "sne_sr_f"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ne:SI (reg:BI SR_F_REGNUM) (const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn_and_split "*scc"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(match_operator:SI 1 "equality_comparison_operator"
|
||||
[(reg:BI SR_F_REGNUM) (const_int 0)]))]
|
||||
""
|
||||
"#"
|
||||
"reload_completed"
|
||||
[(set (match_dup 0) (const_int 1))
|
||||
(set (match_dup 0)
|
||||
(if_then_else:SI (match_dup 1)
|
||||
(match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_expand "mov<I:mode>cc"
|
||||
[(set (match_operand:I 0 "register_operand" "")
|
||||
(if_then_else:I (match_operand 1 "comparison_operator" "")
|
||||
(match_operand:I 2 "reg_or_0_operand" "")
|
||||
(match_operand:I 3 "reg_or_0_operand" "")))]
|
||||
""
|
||||
{
|
||||
rtx xops[3] = { operands[1], XEXP (operands[1], 0), XEXP (operands[1], 1) };
|
||||
or1k_expand_compare (xops);
|
||||
operands[1] = xops[0];
|
||||
})
|
||||
|
||||
(define_insn_and_split "*cmov<I:mode>"
|
||||
[(set (match_operand:I 0 "register_operand" "=r")
|
||||
(if_then_else:I
|
||||
(match_operator 3 "equality_comparison_operator"
|
||||
[(reg:BI SR_F_REGNUM) (const_int 0)])
|
||||
(match_operand:I 1 "reg_or_0_operand" "rO")
|
||||
(match_operand:I 2 "reg_or_0_operand" "rO")))]
|
||||
""
|
||||
{
|
||||
return (GET_CODE (operands[3]) == NE
|
||||
? "l.cmov\t%0, %r1, %r2"
|
||||
: "l.cmov\t%0, %r2, %r1");
|
||||
}
|
||||
"!TARGET_CMOV"
|
||||
[(const_int 0)]
|
||||
{
|
||||
rtx x;
|
||||
rtx label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
|
||||
|
||||
/* Generated a *cbranch pattern. */
|
||||
if (rtx_equal_p (operands[0], operands[2]))
|
||||
{
|
||||
PUT_CODE (operands[3], (GET_CODE (operands[3]) == NE) ? EQ : NE);
|
||||
x = gen_rtx_IF_THEN_ELSE (VOIDmode, operands[3], label, pc_rtx);
|
||||
emit_jump_insn (gen_rtx_SET (pc_rtx, x));
|
||||
emit_move_insn (operands[0], operands[1]);
|
||||
}
|
||||
else
|
||||
{
|
||||
x = gen_rtx_IF_THEN_ELSE (VOIDmode, operands[3], label, pc_rtx);
|
||||
emit_move_insn (operands[0], operands[1]);
|
||||
emit_jump_insn (gen_rtx_SET (pc_rtx, x));
|
||||
emit_move_insn (operands[0], operands[2]);
|
||||
}
|
||||
|
||||
emit_label (XEXP (label, 0));
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Branch instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_expand "cbranchsi4"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 0 "comparison_operator"
|
||||
[(match_operand:SI 1 "reg_or_0_operand" "")
|
||||
(match_operand:SI 2 "reg_or_s16_operand" "")])
|
||||
(label_ref (match_operand 3 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
{
|
||||
or1k_expand_compare (operands);
|
||||
})
|
||||
|
||||
(define_insn "*cbranch"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 1 "equality_comparison_operator"
|
||||
[(reg:BI SR_F_REGNUM) (const_int 0)])
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
{
|
||||
return (GET_CODE (operands[1]) == NE
|
||||
? "l.bf\t%0%#"
|
||||
: "l.bnf\t%0%#");
|
||||
}
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Jump instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "jump"
|
||||
[(set (pc) (label_ref (match_operand 0 "" "")))]
|
||||
""
|
||||
"l.j\t%0%#"
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
(define_insn "indirect_jump"
|
||||
[(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
||||
""
|
||||
"l.jr\t%0%#"
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Prologue & Epilogue
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_expand "prologue"
|
||||
[(const_int 1)]
|
||||
""
|
||||
{
|
||||
or1k_expand_prologue ();
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Expand epilogue as RTL
|
||||
(define_expand "epilogue"
|
||||
[(return)]
|
||||
""
|
||||
{
|
||||
or1k_expand_epilogue ();
|
||||
emit_jump_insn (gen_simple_return ());
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sibcall_epilogue"
|
||||
[(return)]
|
||||
""
|
||||
{
|
||||
or1k_expand_epilogue ();
|
||||
/* Placing a USE of LR here, rather than as a REG_USE on the
|
||||
sibcall itself, means that LR is not unnecessarily live
|
||||
within the function itself, which would force creation of
|
||||
a stack frame. */
|
||||
emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, LR_REGNUM)));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "simple_return"
|
||||
[(parallel [(simple_return) (use (match_dup 0))])]
|
||||
""
|
||||
{
|
||||
operands[0] = gen_rtx_REG (Pmode, LR_REGNUM);
|
||||
})
|
||||
|
||||
(define_insn "*simple_return"
|
||||
[(simple_return)
|
||||
(use (match_operand:SI 0 "register_operand" "r"))]
|
||||
""
|
||||
"l.jr\t%0%#"
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
(define_expand "eh_return"
|
||||
[(use (match_operand 0 "general_operand"))]
|
||||
""
|
||||
{
|
||||
or1k_expand_eh_return (operands[0]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; This is a placeholder, during RA, in order to create the PIC regiter.
|
||||
;; We do this so that we don't unconditionally mark the LR register as
|
||||
;; clobbered. It is replaced during prologue generation with the proper
|
||||
;; set_got pattern below. This works because the set_got_tmp insn is the
|
||||
;; first insn in the stream and that it isn't moved during RA.
|
||||
(define_insn "set_got_tmp"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
|
||||
""
|
||||
{
|
||||
gcc_unreachable ();
|
||||
})
|
||||
|
||||
;; The insn to initialize the GOT.
|
||||
(define_insn "set_got"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
|
||||
(clobber (reg:SI LR_REGNUM))]
|
||||
""
|
||||
{
|
||||
return ("l.jal\t8\;"
|
||||
" l.movhi\t%0, gotpchi(_GLOBAL_OFFSET_TABLE_-4)\;"
|
||||
"l.ori\t%0, %0, gotpclo(_GLOBAL_OFFSET_TABLE_+0)\;"
|
||||
"l.add\t%0, %0, r9");
|
||||
}
|
||||
[(set_attr "length" "16")
|
||||
(set_attr "type" "multi")])
|
||||
|
||||
;; Block memory operations from being scheduled across frame (de)allocation.
|
||||
(define_insn "frame_addsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(plus:SI
|
||||
(match_operand:SI 1 "register_operand" "%r,r")
|
||||
(match_operand:SI 2 "reg_or_s16_operand" " r,I")))
|
||||
(clobber (mem:BLK (scratch)))]
|
||||
"reload_completed"
|
||||
"@
|
||||
l.add\t%0, %1, %2
|
||||
l.addi\t%0, %1, %2")
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Atomic Operations
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
;; Note that MULT stands in for the non-existant NAND rtx_code.
|
||||
(define_code_iterator FETCHOP [plus minus ior xor and mult])
|
||||
|
||||
(define_code_attr fetchop_name
|
||||
[(plus "add")
|
||||
(minus "sub")
|
||||
(ior "or")
|
||||
(xor "xor")
|
||||
(and "and")
|
||||
(mult "nand")])
|
||||
|
||||
(define_code_attr fetchop_pred
|
||||
[(plus "reg_or_s16_operand")
|
||||
(minus "register_operand")
|
||||
(ior "reg_or_u16_operand")
|
||||
(xor "reg_or_s16_operand")
|
||||
(and "reg_or_u16_operand")
|
||||
(mult "reg_or_u16_operand")])
|
||||
|
||||
(define_expand "mem_thread_fence"
|
||||
[(match_operand:SI 0 "const_int_operand" "")] ;; model
|
||||
""
|
||||
{
|
||||
memmodel model = memmodel_base (INTVAL (operands[0]));
|
||||
if (model != MEMMODEL_RELAXED)
|
||||
emit_insn (gen_msync ());
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "msync"
|
||||
[(set (match_dup 0) (unspec:BLK [(match_dup 0)] UNSPEC_MSYNC))]
|
||||
""
|
||||
{
|
||||
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
||||
MEM_VOLATILE_P (operands[0]) = 1;
|
||||
})
|
||||
|
||||
(define_insn "*msync"
|
||||
[(set (match_operand:BLK 0 "" "")
|
||||
(unspec:BLK [(match_dup 0)] UNSPEC_MSYNC))]
|
||||
""
|
||||
"l.msync")
|
||||
|
||||
(define_insn "load_locked_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 1 "memory_operand" "m")] UNSPECV_LL))]
|
||||
""
|
||||
"l.lwa\t%0,%1"
|
||||
[(set_attr "type" "ld")])
|
||||
|
||||
(define_insn "store_conditional_si"
|
||||
[(set (reg:BI SR_F_REGNUM)
|
||||
(unspec_volatile:BI [(const_int 0)] UNSPECV_SC))
|
||||
(set (match_operand:SI 0 "memory_operand" "=m")
|
||||
(match_operand:SI 1 "reg_or_0_operand" "rO"))]
|
||||
""
|
||||
"l.swa\t%0,%r1"
|
||||
[(set_attr "type" "st")])
|
||||
|
||||
(define_expand "atomic_compare_and_swapsi"
|
||||
[(match_operand:SI 0 "register_operand") ;; bool output
|
||||
(match_operand:SI 1 "register_operand") ;; val output
|
||||
(match_operand:SI 2 "memory_operand") ;; memory
|
||||
(match_operand:SI 3 "reg_or_s16_operand") ;; expected
|
||||
(match_operand:SI 4 "reg_or_0_operand") ;; desired
|
||||
(match_operand:SI 5 "const_int_operand") ;; is_weak
|
||||
(match_operand:SI 6 "const_int_operand") ;; mod_s
|
||||
(match_operand:SI 7 "const_int_operand")] ;; mod_f
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_compare_and_swap (operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_compare_and_swap<mode>"
|
||||
[(match_operand:SI 0 "register_operand") ;; bool output
|
||||
(match_operand:I12 1 "register_operand") ;; val output
|
||||
(match_operand:I12 2 "memory_operand") ;; memory
|
||||
(match_operand:I12 3 "register_operand") ;; expected
|
||||
(match_operand:I12 4 "reg_or_0_operand") ;; desired
|
||||
(match_operand:SI 5 "const_int_operand") ;; is_weak
|
||||
(match_operand:SI 6 "const_int_operand") ;; mod_s
|
||||
(match_operand:SI 7 "const_int_operand")] ;; mod_f
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_compare_and_swap_qihi (operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_exchangesi"
|
||||
[(match_operand:SI 0 "register_operand") ;; output
|
||||
(match_operand:SI 1 "memory_operand") ;; memory
|
||||
(match_operand:SI 2 "reg_or_0_operand") ;; input
|
||||
(match_operand:SI 3 "const_int_operand")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_exchange (operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_exchange<mode>"
|
||||
[(match_operand:I12 0 "register_operand") ;; output
|
||||
(match_operand:I12 1 "memory_operand") ;; memory
|
||||
(match_operand:I12 2 "reg_or_0_operand") ;; input
|
||||
(match_operand:SI 3 "const_int_operand")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_exchange_qihi (operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_<fetchop_name>si"
|
||||
[(match_operand:SI 0 "memory_operand") ;; memory
|
||||
(FETCHOP:SI (match_dup 0)
|
||||
(match_operand:SI 1 "<fetchop_pred>")) ;; operand
|
||||
(match_operand:SI 2 "const_int_operand")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_<fetchop_name><mode>"
|
||||
[(match_operand:I12 0 "memory_operand") ;; memory
|
||||
(FETCHOP:I12 (match_dup 0)
|
||||
(match_operand:I12 1 "register_operand")) ;; operand
|
||||
(match_operand:SI 2 "const_int_operand")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_op_qihi (<CODE>, operands[0], operands[1], NULL, NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_fetch_<fetchop_name>si"
|
||||
[(match_operand:SI 0 "register_operand" "") ;; output
|
||||
(match_operand:SI 1 "memory_operand" "") ;; memory
|
||||
(FETCHOP:SI (match_dup 1)
|
||||
(match_operand:SI 2 "<fetchop_pred>" "")) ;; operand
|
||||
(match_operand:SI 3 "const_int_operand" "")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_fetch_<fetchop_name><mode>"
|
||||
[(match_operand:I12 0 "register_operand" "") ;; output
|
||||
(match_operand:I12 1 "memory_operand" "") ;; memory
|
||||
(FETCHOP:I12 (match_dup 1)
|
||||
(match_operand:I12 2 "<fetchop_pred>" "")) ;; operand
|
||||
(match_operand:SI 3 "const_int_operand" "")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_op_qihi (<CODE>, operands[1], operands[2],
|
||||
operands[0], NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_<fetchop_name>_fetchsi"
|
||||
[(match_operand:SI 0 "register_operand" "") ;; output
|
||||
(match_operand:SI 1 "memory_operand" "") ;; memory
|
||||
(FETCHOP:SI (match_dup 1)
|
||||
(match_operand:SI 2 "<fetchop_pred>" "")) ;; operand
|
||||
(match_operand:SI 3 "const_int_operand" "")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "atomic_<fetchop_name>_fetch<mode>"
|
||||
[(match_operand:I12 0 "register_operand" "") ;; output
|
||||
(match_operand:I12 1 "memory_operand" "") ;; memory
|
||||
(FETCHOP:I12 (match_dup 1)
|
||||
(match_operand:I12 2 "<fetchop_pred>" "")) ;; operand
|
||||
(match_operand:SI 3 "const_int_operand" "")] ;; model
|
||||
""
|
||||
{
|
||||
or1k_expand_atomic_op_qihi (<CODE>, operands[1], operands[2],
|
||||
NULL, operands[0]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Call Instructions
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
;; Leave these to last, as the modeless operand for call_value
|
||||
;; interferes with normal patterns.
|
||||
|
||||
(define_expand "call"
|
||||
[(call (match_operand 0) (match_operand 1))]
|
||||
""
|
||||
{
|
||||
or1k_expand_call (NULL, operands[0], operands[1], false);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sibcall"
|
||||
[(call (match_operand 0) (match_operand 1))]
|
||||
""
|
||||
{
|
||||
or1k_expand_call (NULL, operands[0], operands[1], true);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "call_value"
|
||||
[(set (match_operand 0) (call (match_operand 1) (match_operand 2)))]
|
||||
""
|
||||
{
|
||||
or1k_expand_call (operands[0], operands[1], operands[2], false);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "sibcall_value"
|
||||
[(set (match_operand 0) (call (match_operand 1) (match_operand 2)))]
|
||||
""
|
||||
{
|
||||
or1k_expand_call (operands[0], operands[1], operands[2], true);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "*call"
|
||||
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "r,s"))
|
||||
(match_operand 1))
|
||||
(clobber (reg:SI LR_REGNUM))]
|
||||
"!SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
l.jalr\t%0%#
|
||||
l.jal\t%P0%#"
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
(define_insn "*sibcall"
|
||||
[(call (mem:SI (match_operand:SI 0 "call_insn_operand" "c,s"))
|
||||
(match_operand 1))]
|
||||
"SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
l.jr\t%0%#
|
||||
l.j\t%P0%#"
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
(define_insn "*call_value"
|
||||
[(set (match_operand 0)
|
||||
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "r,s"))
|
||||
(match_operand 2)))
|
||||
(clobber (reg:SI LR_REGNUM))]
|
||||
"!SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
l.jalr\t%1%#
|
||||
l.jal\t%P1%#"
|
||||
[(set_attr "type" "control")])
|
||||
|
||||
(define_insn "*sibcall_value"
|
||||
[(set (match_operand 0)
|
||||
(call (mem:SI (match_operand:SI 1 "call_insn_operand" "c,s"))
|
||||
(match_operand 2)))]
|
||||
"SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
l.jr\t%1%#
|
||||
l.j\t%P1%#"
|
||||
[(set_attr "type" "control")])
|
||||
67
gcc/config/or1k/or1k.opt
Normal file
67
gcc/config/or1k/or1k.opt
Normal file
@ -0,0 +1,67 @@
|
||||
; OpenRISC command line options
|
||||
|
||||
; Copyright (C) 2010-2018 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 3, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
; See the GCC internals manual (options.texi) for a description of
|
||||
; this file's format.
|
||||
|
||||
; Please try to keep this file in ASCII collating order.
|
||||
|
||||
mhard-div
|
||||
Target RejectNegative InverseMask(SOFT_DIV)
|
||||
Use hardware divide instructions, use -msoft-div for emulation.
|
||||
|
||||
mhard-mul
|
||||
Target RejectNegative InverseMask(SOFT_MUL).
|
||||
Use hardware multiply instructions, use -msoft-mul for emulation.
|
||||
|
||||
mcmov
|
||||
Target RejectNegative Mask(CMOV)
|
||||
Allows generation of binaries which use the l.cmov instruction. If your target
|
||||
does not support this the compiler will generate the equivalent using set and
|
||||
branch.
|
||||
|
||||
mror
|
||||
Target RejectNegative Mask(ROR)
|
||||
Allows generation of binaries which use the l.rori instructions.
|
||||
|
||||
msext
|
||||
Target RejectNegative Mask(SEXT)
|
||||
Allows generation of binaries which use sign-extension instructions. If your
|
||||
target does not support this the compiler will use memory loads to perform sign
|
||||
extension.
|
||||
|
||||
msfimm
|
||||
Target RejectNegative Mask(SFIMM)
|
||||
Allows generation of binaries which use l.sf*i instructions. If your target
|
||||
does not support this the compiler will generate instructions to store the
|
||||
immediate to a register first.
|
||||
|
||||
mshftimm
|
||||
Target RejectNegative Mask(SHFTIMM)
|
||||
Allows generation of binaries which support shifts and rotate instructions
|
||||
supporting immediate arguments, for example l.rori.
|
||||
|
||||
msoft-div
|
||||
Target RejectNegative Mask(SOFT_DIV)
|
||||
Use divide emulation.
|
||||
|
||||
msoft-mul
|
||||
Target RejectNegative Mask(SOFT_MUL).
|
||||
Use multiply emulation.
|
||||
84
gcc/config/or1k/predicates.md
Normal file
84
gcc/config/or1k/predicates.md
Normal file
@ -0,0 +1,84 @@
|
||||
;; Predicate definitions for OpenRISC
|
||||
;; Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
;; Contributed by Stafford Horne
|
||||
|
||||
;; This file is part of GCC.
|
||||
|
||||
;; GCC is free software; you can redistribute it and/or modify it
|
||||
;; under the terms of the GNU General Public License as published
|
||||
;; by the Free Software Foundation; either version 3, or (at your
|
||||
;; option) any later version.
|
||||
|
||||
;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
;; License for more details.
|
||||
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Predicates
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_predicate "input_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "memory_operand")
|
||||
(and (match_code "const_int")
|
||||
(match_test "satisfies_constraint_I (op)
|
||||
|| satisfies_constraint_K (op)
|
||||
|| satisfies_constraint_M (op)"))))
|
||||
|
||||
(define_predicate "const0_operand"
|
||||
(and (match_code "const_int,const_wide_int,const_double,const_vector")
|
||||
(match_test "op == CONST0_RTX (mode)")))
|
||||
|
||||
(define_predicate "reg_or_0_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "const0_operand")))
|
||||
|
||||
(define_predicate "reg_or_u6_operand"
|
||||
(if_then_else (match_code "const_int")
|
||||
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x3f")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
(define_predicate "reg_or_u16_operand"
|
||||
(if_then_else (match_code "const_int")
|
||||
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0xffff")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
(define_predicate "reg_or_s16_operand"
|
||||
(if_then_else (match_code "const_int")
|
||||
(match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
(define_predicate "call_insn_operand"
|
||||
(ior (match_code "symbol_ref")
|
||||
(match_operand 0 "register_operand")))
|
||||
|
||||
(define_predicate "high_operand"
|
||||
(match_code "symbol_ref,label_ref,const,unspec"))
|
||||
|
||||
;; Return true for relocations that must use MOVHI+ADDI
|
||||
(define_predicate "losum_add_operand"
|
||||
(match_code "symbol_ref,label_ref,const,unspec"))
|
||||
|
||||
;; Return true for relocations that must use MOVHI+ORI
|
||||
(define_predicate "losum_ior_operand"
|
||||
(and (match_code "unspec")
|
||||
(match_test "XINT(op, 1) == UNSPEC_TLSGD")))
|
||||
|
||||
;; Return true for a "virtual" or "soft" register that will be
|
||||
;; adjusted to a "soft" or "hard" register during elimination.
|
||||
(define_predicate "virtual_frame_reg_operand"
|
||||
(match_code "reg")
|
||||
{
|
||||
unsigned regno = REGNO (op);
|
||||
return (regno != STACK_POINTER_REGNUM
|
||||
&& regno != HARD_FRAME_POINTER_REGNUM
|
||||
&& REGNO_PTR_FRAME_P (regno));
|
||||
})
|
||||
|
||||
(define_predicate "equality_comparison_operator"
|
||||
(match_code "ne,eq"))
|
||||
30
gcc/config/or1k/rtems.h
Normal file
30
gcc/config/or1k/rtems.h
Normal file
@ -0,0 +1,30 @@
|
||||
/* Target Newlib Definitions for OpenRISC.
|
||||
Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
Contributed by Joel Sherrill (joel.sherrill@OARcorp.com).
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Target OS builtins. */
|
||||
#undef TARGET_OS_CPP_BUILTINS
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_define ("__rtems__"); \
|
||||
builtin_define ("__USE_INIT_FINI__"); \
|
||||
builtin_assert ("system=rtems"); \
|
||||
} \
|
||||
while (0)
|
||||
22
gcc/config/or1k/t-or1k
Normal file
22
gcc/config/or1k/t-or1k
Normal file
@ -0,0 +1,22 @@
|
||||
# Target Makefile Fragment for OpenRISC
|
||||
# Copyright (C) 2018 Free Software Foundation, Inc.
|
||||
# Contributed by Stafford Horne.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published
|
||||
# by the Free Software Foundation; either version 3, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
# License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
comma=,
|
||||
MULTILIB_OPTIONS = $(subst $(comma), ,$(TM_MULTILIB_CONFIG))
|
||||
3
gcc/config/or1k/t-rtems
Normal file
3
gcc/config/or1k/t-rtems
Normal file
@ -0,0 +1,3 @@
|
||||
# RTEMS OR1K multilibs
|
||||
|
||||
# No custom multilibs defined
|
||||
12
gcc/configure
vendored
12
gcc/configure
vendored
@ -24391,6 +24391,18 @@ foo: .long 25
|
||||
tls_first_minor=20
|
||||
tls_as_opt='--fatal-warnings'
|
||||
;;
|
||||
or1k*-*-*)
|
||||
conftest_s='
|
||||
.section ".tdata","awT",@progbits
|
||||
foo: .long 25
|
||||
.text
|
||||
l.movhi r3, tpoffha(foo)
|
||||
l.add r3, r3, r10
|
||||
l.lwz r4, tpofflo(foo)(r3)'
|
||||
tls_first_major=2
|
||||
tls_first_minor=30
|
||||
tls_as_opt=--fatal-warnings
|
||||
;;
|
||||
powerpc-ibm-aix*)
|
||||
conftest_s='
|
||||
.extern __get_tpointer
|
||||
|
||||
@ -3473,6 +3473,18 @@ foo: .long 25
|
||||
tls_first_minor=20
|
||||
tls_as_opt='--fatal-warnings'
|
||||
;;
|
||||
or1k*-*-*)
|
||||
conftest_s='
|
||||
.section ".tdata","awT",@progbits
|
||||
foo: .long 25
|
||||
.text
|
||||
l.movhi r3, tpoffha(foo)
|
||||
l.add r3, r3, r10
|
||||
l.lwz r4, tpofflo(foo)(r3)'
|
||||
tls_first_major=2
|
||||
tls_first_minor=30
|
||||
tls_as_opt=--fatal-warnings
|
||||
;;
|
||||
powerpc-ibm-aix*)
|
||||
conftest_s='
|
||||
.extern __get_tpointer
|
||||
|
||||
@ -3269,6 +3269,10 @@ information have to.
|
||||
@item
|
||||
@uref{#nvptx-x-none,,nvptx-*-none}
|
||||
@item
|
||||
@uref{#or1k-x-elf,,or1k-*-elf}
|
||||
@item
|
||||
@uref{#or1k-x-linux,,or1k-*-linux}
|
||||
@item
|
||||
@uref{#powerpc-x-x,,powerpc*-*-*}
|
||||
@item
|
||||
@uref{#powerpc-x-darwin,,powerpc-*-darwin*}
|
||||
@ -4236,6 +4240,21 @@ the GCC sources.
|
||||
Use the @option{--disable-sjlj-exceptions} and
|
||||
@option{--enable-newlib-io-long-long} options when configuring.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
@anchor{or1k-x-elf}
|
||||
@heading or1k-*-elf
|
||||
The OpenRISC 1000 32-bit processor with delay slots.
|
||||
This configuration is intended for embedded systems.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
@anchor{or1k-x-linux}
|
||||
@heading or1k-*-linux
|
||||
The OpenRISC 1000 32-bit processor with delay slots.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
|
||||
@ -1010,6 +1010,11 @@ Objective-C and Objective-C++ Dialects}.
|
||||
@emph{Nvidia PTX Options}
|
||||
@gccoptlist{-m32 -m64 -mmainkernel -moptimize}
|
||||
|
||||
@emph{OpenRISC Options}
|
||||
@gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol
|
||||
-msoft-mul -msoft-div @gol
|
||||
-mcmov -mror -msext -msfimm -mshftimm}
|
||||
|
||||
@emph{PDP-11 Options}
|
||||
@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
|
||||
-mint32 -mno-int16 -mint16 -mno-int32 @gol
|
||||
@ -14984,6 +14989,7 @@ platform.
|
||||
* NDS32 Options::
|
||||
* Nios II Options::
|
||||
* Nvidia PTX Options::
|
||||
* OpenRISC Options::
|
||||
* PDP-11 Options::
|
||||
* picoChip Options::
|
||||
* PowerPC Options::
|
||||
@ -22762,6 +22768,68 @@ Generate code for use in OpenMP offloading: enables @option{-msoft-stack} and
|
||||
|
||||
@end table
|
||||
|
||||
@node OpenRISC Options
|
||||
@subsection OpenRISC Options
|
||||
@cindex OpenRISC Options
|
||||
|
||||
These options are defined for OpenRISC:
|
||||
|
||||
@table @gcctabopt
|
||||
|
||||
@item -mboard=@var{name}
|
||||
@opindex mboard
|
||||
Configure a board specific runtime. This will be passed to the linker for
|
||||
newlib board library linking. The default is @code{or1ksim}.
|
||||
|
||||
@item -mnewlib
|
||||
@opindex mnewlib
|
||||
For compatibility, it's always newlib for elf now.
|
||||
|
||||
@item -mhard-div
|
||||
@opindex mhard-div
|
||||
Generate code for hardware which supports divide instructions. This is the
|
||||
default.
|
||||
|
||||
@item -mhard-mul
|
||||
@opindex mhard-mul
|
||||
Generate code for hardware which supports multiply instructions. This is the
|
||||
default.
|
||||
|
||||
@item -mcmov
|
||||
@opindex mcmov
|
||||
Generate code for hardware which supports the conditional move (@code{l.cmov})
|
||||
instruction.
|
||||
|
||||
@item -mror
|
||||
@opindex mror
|
||||
Generate code for hardware which supports rotate right instructions.
|
||||
|
||||
@item -msext
|
||||
@opindex msext
|
||||
Generate code for hardware which supports sign-extension instructions.
|
||||
|
||||
@item -msfimm
|
||||
@opindex msfimm
|
||||
Generate code for hardware which supports set flag immediate (@code{l.sf*i})
|
||||
instructions.
|
||||
|
||||
@item -mshftimm
|
||||
@opindex mshftimm
|
||||
Generate code for hardware which supports shift immediate related instructions
|
||||
(i.e. @code{l.srai}, @code{l.srli}, @code{l.slli}, @code{1.rori}). Note, to
|
||||
enable generation of the @code{l.rori} instruction the @option{-mror} flag must
|
||||
also be specified.
|
||||
|
||||
@item -msoft-div
|
||||
@opindex msoft-div
|
||||
Generate code for hardware which requires divide instruction emulation.
|
||||
|
||||
@item -msoft-mul
|
||||
@opindex msoft-mul
|
||||
Generate code for hardware which requires multiply instruction emulation.
|
||||
|
||||
@end table
|
||||
|
||||
@node PDP-11 Options
|
||||
@subsection PDP-11 Options
|
||||
@cindex PDP-11 Options
|
||||
|
||||
@ -3003,6 +3003,31 @@ representing a supported PIC or TLS relocation.
|
||||
|
||||
@end table
|
||||
|
||||
@item OpenRISC---@file{config/or1k/constraints.md}
|
||||
@table @code
|
||||
@item I
|
||||
Integer that is valid as an immediate operand in an
|
||||
instruction taking a signed 16-bit number. Range
|
||||
@minus{}32768 to 32767.
|
||||
|
||||
@item K
|
||||
Integer that is valid as an immediate operand in an
|
||||
instruction taking an unsigned 16-bit number. Range
|
||||
0 to 65535.
|
||||
|
||||
@item M
|
||||
Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi})
|
||||
|
||||
@item O
|
||||
Zero
|
||||
|
||||
@ifset INTERNALS
|
||||
@item c
|
||||
Register usable for sibcalls.
|
||||
@end ifset
|
||||
|
||||
@end table
|
||||
|
||||
@item PDP-11---@file{config/pdp11/constraints.md}
|
||||
@table @code
|
||||
@item a
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user