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aarch64: Implement -moutline-atomics
* config/aarch64/aarch64.opt (-moutline-atomics): New. * config/aarch64/aarch64.c (aarch64_atomic_ool_func): New. (aarch64_ool_cas_names, aarch64_ool_swp_names): New. (aarch64_ool_ldadd_names, aarch64_ool_ldset_names): New. (aarch64_ool_ldclr_names, aarch64_ool_ldeor_names): New. (aarch64_expand_compare_and_swap): Honor TARGET_OUTLINE_ATOMICS. * config/aarch64/atomics.md (atomic_exchange<ALLI>): Likewise. (atomic_<atomic_op><ALLI>): Likewise. (atomic_fetch_<atomic_op><ALLI>): Likewise. (atomic_<atomic_op>_fetch<ALLI>): Likewise. * doc/invoke.texi: Document -moutline-atomics. testsuite/ * gcc.target/aarch64/atomic-op-acq_rel.c: Use -mno-outline-atomics. * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Likewise. * gcc.target/aarch64/atomic-op-acquire.c: Likewise. * gcc.target/aarch64/atomic-op-char.c: Likewise. * gcc.target/aarch64/atomic-op-consume.c: Likewise. * gcc.target/aarch64/atomic-op-imm.c: Likewise. * gcc.target/aarch64/atomic-op-int.c: Likewise. * gcc.target/aarch64/atomic-op-long.c: Likewise. * gcc.target/aarch64/atomic-op-relaxed.c: Likewise. * gcc.target/aarch64/atomic-op-release.c: Likewise. * gcc.target/aarch64/atomic-op-seq_cst.c: Likewise. * gcc.target/aarch64/atomic-op-short.c: Likewise. * gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Likewise. * gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: Likewise. * gcc.target/aarch64/sync-comp-swap.c: Likewise. * gcc.target/aarch64/sync-op-acquire.c: Likewise. * gcc.target/aarch64/sync-op-full.c: Likewise. From-SVN: r275968
This commit is contained in:
Richard Henderson
Richard Henderson
parent
33befddcb8
commit
3950b229a5
gcc
ChangeLog
config/aarch64
doc
testsuite
ChangeLog
gcc.target/aarch64
atomic-comp-swap-release-acquire.catomic-op-acq_rel.catomic-op-acquire.catomic-op-char.catomic-op-consume.catomic-op-imm.catomic-op-int.catomic-op-long.catomic-op-relaxed.catomic-op-release.catomic-op-seq_cst.catomic-op-short.catomic_cmp_exchange_zero_reg_1.catomic_cmp_exchange_zero_strong_1.csync-comp-swap.csync-op-acquire.csync-op-full.c
@ -20,6 +20,18 @@
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strong_zero_p for aarch64_track_speculation; unify some code paths;
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use aarch64_gen_compare_reg instead of open-coding.
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* config/aarch64/aarch64.opt (-moutline-atomics): New.
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* config/aarch64/aarch64.c (aarch64_atomic_ool_func): New.
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(aarch64_ool_cas_names, aarch64_ool_swp_names): New.
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(aarch64_ool_ldadd_names, aarch64_ool_ldset_names): New.
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(aarch64_ool_ldclr_names, aarch64_ool_ldeor_names): New.
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(aarch64_expand_compare_and_swap): Honor TARGET_OUTLINE_ATOMICS.
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* config/aarch64/atomics.md (atomic_exchange<ALLI>): Likewise.
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(atomic_<atomic_op><ALLI>): Likewise.
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(atomic_fetch_<atomic_op><ALLI>): Likewise.
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(atomic_<atomic_op>_fetch<ALLI>): Likewise.
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* doc/invoke.texi: Document -moutline-atomics.
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2019-09-19 Feng Xue <fxue@os.amperecomputing.com>
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* ipa-fnsummary.c (set_cond_stmt_execution_predicate): Do not compute
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@ -696,4 +696,17 @@ poly_uint64 aarch64_regmode_natural_size (machine_mode);
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bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT);
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struct atomic_ool_names
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{
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const char *str[5][4];
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};
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rtx aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
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const atomic_ool_names *names);
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extern const atomic_ool_names aarch64_ool_swp_names;
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extern const atomic_ool_names aarch64_ool_ldadd_names;
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extern const atomic_ool_names aarch64_ool_ldset_names;
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extern const atomic_ool_names aarch64_ool_ldclr_names;
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extern const atomic_ool_names aarch64_ool_ldeor_names;
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#endif /* GCC_AARCH64_PROTOS_H */
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@ -16867,6 +16867,82 @@ aarch64_emit_unlikely_jump (rtx insn)
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add_reg_br_prob_note (jump, profile_probability::very_unlikely ());
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}
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/* We store the names of the various atomic helpers in a 5x4 array.
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Return the libcall function given MODE, MODEL and NAMES. */
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rtx
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aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
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const atomic_ool_names *names)
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{
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memmodel model = memmodel_base (INTVAL (model_rtx));
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int mode_idx, model_idx;
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switch (mode)
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{
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case E_QImode:
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mode_idx = 0;
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break;
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case E_HImode:
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mode_idx = 1;
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break;
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case E_SImode:
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mode_idx = 2;
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break;
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case E_DImode:
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mode_idx = 3;
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break;
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case E_TImode:
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mode_idx = 4;
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break;
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default:
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gcc_unreachable ();
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}
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switch (model)
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{
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case MEMMODEL_RELAXED:
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model_idx = 0;
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break;
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case MEMMODEL_CONSUME:
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case MEMMODEL_ACQUIRE:
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model_idx = 1;
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break;
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case MEMMODEL_RELEASE:
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model_idx = 2;
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break;
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case MEMMODEL_ACQ_REL:
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case MEMMODEL_SEQ_CST:
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model_idx = 3;
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break;
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default:
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gcc_unreachable ();
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}
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return init_one_libfunc_visibility (names->str[mode_idx][model_idx],
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VISIBILITY_HIDDEN);
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}
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#define DEF0(B, N) \
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{ "__aarch64_" #B #N "_relax", \
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"__aarch64_" #B #N "_acq", \
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"__aarch64_" #B #N "_rel", \
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"__aarch64_" #B #N "_acq_rel" }
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#define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
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{ NULL, NULL, NULL, NULL }
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#define DEF5(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
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static const atomic_ool_names aarch64_ool_cas_names = { { DEF5(cas) } };
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const atomic_ool_names aarch64_ool_swp_names = { { DEF4(swp) } };
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const atomic_ool_names aarch64_ool_ldadd_names = { { DEF4(ldadd) } };
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const atomic_ool_names aarch64_ool_ldset_names = { { DEF4(ldset) } };
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const atomic_ool_names aarch64_ool_ldclr_names = { { DEF4(ldclr) } };
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const atomic_ool_names aarch64_ool_ldeor_names = { { DEF4(ldeor) } };
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#undef DEF0
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#undef DEF4
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#undef DEF5
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/* Expand a compare and swap pattern. */
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void
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@ -16913,6 +16989,17 @@ aarch64_expand_compare_and_swap (rtx operands[])
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newval, mod_s));
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cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
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}
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else if (TARGET_OUTLINE_ATOMICS)
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{
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/* Oldval must satisfy compare afterward. */
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if (!aarch64_plus_operand (oldval, mode))
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oldval = force_reg (mode, oldval);
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rtx func = aarch64_atomic_ool_func (mode, mod_s, &aarch64_ool_cas_names);
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rval = emit_library_call_value (func, NULL_RTX, LCT_NORMAL, r_mode,
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oldval, mode, newval, mode,
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XEXP (mem, 0), Pmode);
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cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
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}
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else
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{
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/* The oldval predicate varies by mode. Test it and force to reg. */
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@ -255,3 +255,6 @@ user-land code.
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TargetVariable
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long aarch64_stack_protector_guard_offset = 0
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moutline-atomics
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Target Report Mask(OUTLINE_ATOMICS) Save
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Generate local calls to out-of-line atomic operations.
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@ -186,16 +186,27 @@
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(match_operand:SI 3 "const_int_operand")]
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""
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{
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rtx (*gen) (rtx, rtx, rtx, rtx);
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/* Use an atomic SWP when available. */
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if (TARGET_LSE)
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gen = gen_aarch64_atomic_exchange<mode>_lse;
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{
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emit_insn (gen_aarch64_atomic_exchange<mode>_lse
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(operands[0], operands[1], operands[2], operands[3]));
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}
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else if (TARGET_OUTLINE_ATOMICS)
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{
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machine_mode mode = <MODE>mode;
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rtx func = aarch64_atomic_ool_func (mode, operands[3],
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&aarch64_ool_swp_names);
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rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL,
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mode, operands[2], mode,
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XEXP (operands[1], 0), Pmode);
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emit_move_insn (operands[0], rval);
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}
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else
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gen = gen_aarch64_atomic_exchange<mode>;
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emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
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{
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emit_insn (gen_aarch64_atomic_exchange<mode>
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(operands[0], operands[1], operands[2], operands[3]));
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}
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DONE;
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}
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)
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@ -280,6 +291,39 @@
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}
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operands[1] = force_reg (<MODE>mode, operands[1]);
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}
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else if (TARGET_OUTLINE_ATOMICS)
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{
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const atomic_ool_names *names;
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switch (<CODE>)
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{
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case MINUS:
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operands[1] = expand_simple_unop (<MODE>mode, NEG, operands[1],
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NULL, 1);
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/* fallthru */
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case PLUS:
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names = &aarch64_ool_ldadd_names;
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break;
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case IOR:
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names = &aarch64_ool_ldset_names;
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break;
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case XOR:
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names = &aarch64_ool_ldeor_names;
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break;
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case AND:
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operands[1] = expand_simple_unop (<MODE>mode, NOT, operands[1],
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NULL, 1);
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names = &aarch64_ool_ldclr_names;
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break;
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default:
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gcc_unreachable ();
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}
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machine_mode mode = <MODE>mode;
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rtx func = aarch64_atomic_ool_func (mode, operands[2], names);
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emit_library_call_value (func, NULL_RTX, LCT_NORMAL, mode,
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operands[1], mode,
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XEXP (operands[0], 0), Pmode);
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DONE;
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}
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else
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gen = gen_aarch64_atomic_<atomic_optab><mode>;
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@ -405,6 +449,40 @@
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}
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operands[2] = force_reg (<MODE>mode, operands[2]);
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}
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else if (TARGET_OUTLINE_ATOMICS)
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{
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const atomic_ool_names *names;
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switch (<CODE>)
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{
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case MINUS:
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operands[2] = expand_simple_unop (<MODE>mode, NEG, operands[2],
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NULL, 1);
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/* fallthru */
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case PLUS:
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names = &aarch64_ool_ldadd_names;
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break;
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case IOR:
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names = &aarch64_ool_ldset_names;
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break;
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case XOR:
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names = &aarch64_ool_ldeor_names;
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break;
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case AND:
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operands[2] = expand_simple_unop (<MODE>mode, NOT, operands[2],
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NULL, 1);
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names = &aarch64_ool_ldclr_names;
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break;
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default:
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gcc_unreachable ();
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}
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machine_mode mode = <MODE>mode;
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rtx func = aarch64_atomic_ool_func (mode, operands[3], names);
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rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL, mode,
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operands[2], mode,
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XEXP (operands[1], 0), Pmode);
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emit_move_insn (operands[0], rval);
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DONE;
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}
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else
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gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>;
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@ -494,7 +572,7 @@
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{
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/* Use an atomic load-operate instruction when possible. In this case
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we will re-compute the result from the original mem value. */
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if (TARGET_LSE)
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if (TARGET_LSE || TARGET_OUTLINE_ATOMICS)
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{
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rtx tmp = gen_reg_rtx (<MODE>mode);
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operands[2] = force_reg (<MODE>mode, operands[2]);
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@ -643,7 +643,8 @@ Objective-C and Objective-C++ Dialects}.
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-march=@var{name} -mcpu=@var{name} -mtune=@var{name} @gol
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-moverride=@var{string} -mverbose-cost-dump @gol
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-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{sysreg} @gol
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-mstack-protector-guard-offset=@var{offset} -mtrack-speculation }
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-mstack-protector-guard-offset=@var{offset} -mtrack-speculation @gol
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-moutline-atomics }
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@emph{Adapteva Epiphany Options}
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@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
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@ -15874,6 +15875,19 @@ be used by the compiler when expanding calls to
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@code{__builtin_speculation_safe_copy} to permit a more efficient code
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sequence to be generated.
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@item -moutline-atomics
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@itemx -mno-outline-atomics
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Enable or disable calls to out-of-line helpers to implement atomic operations.
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These helpers will, at runtime, determine if the LSE instructions from
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ARMv8.1-A can be used; if not, they will use the load/store-exclusive
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instructions that are present in the base ARMv8.0 ISA.
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This option is only applicable when compiling for the base ARMv8.0
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instruction set. If using a later revision, e.g. @option{-march=armv8.1-a}
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or @option{-march=armv8-a+lse}, the ARMv8.1-Atomics instructions will be
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used directly. The same applies when using @option{-mcpu=} when the
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selected cpu supports the @samp{lse} feature.
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@item -march=@var{name}
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@opindex march
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Specify the name of the target architecture and, optionally, one or
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@ -1,3 +1,23 @@
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2019-09-19 Richard Henderson <richard.henderson@linaro.org>
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* gcc.target/aarch64/atomic-op-acq_rel.c: Use -mno-outline-atomics.
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* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Likewise.
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* gcc.target/aarch64/atomic-op-acquire.c: Likewise.
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* gcc.target/aarch64/atomic-op-char.c: Likewise.
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* gcc.target/aarch64/atomic-op-consume.c: Likewise.
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* gcc.target/aarch64/atomic-op-imm.c: Likewise.
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* gcc.target/aarch64/atomic-op-int.c: Likewise.
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* gcc.target/aarch64/atomic-op-long.c: Likewise.
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* gcc.target/aarch64/atomic-op-relaxed.c: Likewise.
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* gcc.target/aarch64/atomic-op-release.c: Likewise.
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* gcc.target/aarch64/atomic-op-seq_cst.c: Likewise.
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* gcc.target/aarch64/atomic-op-short.c: Likewise.
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* gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Likewise.
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* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: Likewise.
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* gcc.target/aarch64/sync-comp-swap.c: Likewise.
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* gcc.target/aarch64/sync-op-acquire.c: Likewise.
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* gcc.target/aarch64/sync-op-full.c: Likewise.
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2019-09-19 Feng Xue <fxue@os.amperecomputing.com>
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* gcc.dg/ipa/pr91089.c: Add a new function and pattern.
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@ -7,7 +27,6 @@
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PR tree-optimization/91812
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* gcc.dg/torture/pr91812.c: New testcase.
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>>>>>>> .r275960
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2019-09-19 Tom Tromey <tromey@adacore.com>
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* gnat.dg/bias1.adb: New testcase.
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf" } */
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/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -mno-outline-atomics" } */
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#include "atomic-comp-swap-release-acquire.x"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8-a+nolse -O2" } */
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/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
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#include "atomic-op-acq_rel.x"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8-a+nolse -O2" } */
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/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
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#include "atomic-op-acquire.x"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8-a+nolse -O2" } */
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/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
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#include "atomic-op-char.x"
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-march=armv8-a+nolse -O2" } */
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/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "atomic-op-consume.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
int v = 0;
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "atomic-op-int.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
long v = 0;
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "atomic-op-relaxed.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "atomic-op-release.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "atomic-op-seq_cst.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "atomic-op-short.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -march=armv8-a+nolse" } */
|
||||
/* { dg-options "-O2 -march=armv8-a+nolse -mno-outline-atomics" } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */
|
||||
|
||||
int
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -march=armv8-a+nolse" } */
|
||||
/* { dg-options "-O2 -march=armv8-a+nolse -mno-outline-atomics" } */
|
||||
/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */
|
||||
|
||||
int
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -mno-outline-atomics" } */
|
||||
|
||||
#include "sync-comp-swap.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "sync-op-acquire.x"
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2" } */
|
||||
/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
|
||||
|
||||
#include "sync-op-full.x"
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user