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alpha.c (alpha_sr_alias_set): New variable.
* alpha.c (alpha_sr_alias_set): New variable.
(override_options): Set it.
(alpha_expand_prologue, alpha_expand_epilogue): Use it.
(mode_mask_operand): Fix signed-unsigned comparision warning.
(alpha_expand_block_move): Likewise.
(print_operand): Likewise.
(get_aligned_mem): Use change_address.
(alpha_set_memflags, alpha_set_memflags_1): Set the alias set.
(alphaev4_insn_pipe, alphaev4_next_group): New functions.
(alphaev4_next_nop, alphaev5_next_nop): New functions.
(alpha_align_insns): Remade from old alphaev5_align_insns
to handle multiple processors.
(alpha_reorg): Call alpha_align_insns for both ev4 and ev5.
* output.h (label_to_alignment): Prototype.
From-SVN: r22505
This commit is contained in:
Richard Henderson
Richard Henderson
parent
2ba573431e
commit
3873d24b23
@ -1,5 +1,20 @@
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Sun Sep 20 19:01:51 1998 Richard Henderson <rth@cygnus.com>
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* alpha.c (alpha_sr_alias_set): New variable.
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(override_options): Set it.
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(alpha_expand_prologue, alpha_expand_epilogue): Use it.
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(mode_mask_operand): Fix signed-unsigned comparision warning.
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(alpha_expand_block_move): Likewise.
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(print_operand): Likewise.
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(get_aligned_mem): Use change_address.
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(alpha_set_memflags, alpha_set_memflags_1): Set the alias set.
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(alphaev4_insn_pipe, alphaev4_next_group): New functions.
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(alphaev4_next_nop, alphaev5_next_nop): New functions.
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(alpha_align_insns): Remade from old alphaev5_align_insns
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to handle multiple processors.
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(alpha_reorg): Call alpha_align_insns for both ev4 and ev5.
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* output.h (label_to_alignment): Prototype.
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* tree.c (new_alias_set): New function.
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* tree.h (new_alias_set): Declare it.
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* c-common.c (c_get_alias_set): Use it.
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@ -100,9 +100,13 @@ int alpha_memory_latency = 3;
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static int alpha_function_needs_gp;
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/* The alias set for prologue/epilogue register save/restore. */
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static int alpha_sr_alias_set;
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/* Declarations of static functions. */
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static void alpha_set_memflags_1
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PROTO((rtx, int, int, int));
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PROTO((rtx, int, int, int, int));
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static rtx alpha_emit_set_const_1
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PROTO((rtx, enum machine_mode, HOST_WIDE_INT, int));
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static void alpha_expand_unaligned_load_words
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@ -302,6 +306,9 @@ override_options ()
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/* Default the definition of "small data" to 8 bytes. */
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if (!g_switch_set)
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g_switch_value = 8;
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/* Acquire a unique set number for our register saves and restores. */
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alpha_sr_alias_set = new_alias_set ();
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}
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/* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
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@ -487,9 +494,9 @@ mode_mask_operand (op, mode)
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return (GET_CODE (op) == CONST_INT
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&& (INTVAL (op) == 0xff
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|| INTVAL (op) == 0xffff
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|| INTVAL (op) == 0xffffffff
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|| INTVAL (op) == (HOST_WIDE_INT)0xffffffff
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#if HOST_BITS_PER_WIDE_INT == 64
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|| INTVAL (op) == 0xffffffffffffffff
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|| INTVAL (op) == -1
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#endif
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));
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}
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@ -870,11 +877,8 @@ get_aligned_mem (ref, paligned_mem, pbitnum)
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if (GET_CODE (base) == PLUS)
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offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
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*paligned_mem = gen_rtx_MEM (SImode,
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plus_constant (base, offset & ~3));
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MEM_IN_STRUCT_P (*paligned_mem) = MEM_IN_STRUCT_P (ref);
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MEM_VOLATILE_P (*paligned_mem) = MEM_VOLATILE_P (ref);
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RTX_UNCHANGING_P (*paligned_mem) = RTX_UNCHANGING_P (ref);
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*paligned_mem = change_address (ref, SImode,
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plus_constant (base, offset & ~3));
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*pbitnum = GEN_INT ((offset & 3) * 8);
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}
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@ -918,9 +922,9 @@ get_unaligned_address (ref, extra_offset)
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found in part of X. */
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static void
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alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
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alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p, alias_set)
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rtx x;
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int in_struct_p, volatile_p, unchanging_p;
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int in_struct_p, volatile_p, unchanging_p, alias_set;
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{
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int i;
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@ -930,25 +934,26 @@ alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
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case PARALLEL:
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for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
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alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
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unchanging_p);
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unchanging_p, alias_set);
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break;
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case INSN:
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alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
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unchanging_p);
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unchanging_p, alias_set);
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break;
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case SET:
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alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
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unchanging_p);
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unchanging_p, alias_set);
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alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
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unchanging_p);
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unchanging_p, alias_set);
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break;
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case MEM:
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MEM_IN_STRUCT_P (x) = in_struct_p;
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MEM_VOLATILE_P (x) = volatile_p;
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RTX_UNCHANGING_P (x) = unchanging_p;
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MEM_ALIAS_SET (x) = alias_set;
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break;
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default:
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@ -967,17 +972,24 @@ alpha_set_memflags (insn, ref)
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rtx insn;
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rtx ref;
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{
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/* Note that it is always safe to get these flags, though they won't
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be what we think if REF is not a MEM. */
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int in_struct_p = MEM_IN_STRUCT_P (ref);
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int volatile_p = MEM_VOLATILE_P (ref);
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int unchanging_p = RTX_UNCHANGING_P (ref);
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int in_struct_p, volatile_p, unchanging_p, alias_set;
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if (GET_CODE (ref) != MEM
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|| (! in_struct_p && ! volatile_p && ! unchanging_p))
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if (GET_CODE (ref) != MEM)
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return;
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alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
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in_struct_p = MEM_IN_STRUCT_P (ref);
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volatile_p = MEM_VOLATILE_P (ref);
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unchanging_p = RTX_UNCHANGING_P (ref);
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alias_set = MEM_ALIAS_SET (ref);
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/* This is only called from alpha.md, after having had something
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generated from one of the insn patterns. So if everything is
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zero, the pattern is already up-to-date. */
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if (! in_struct_p && ! volatile_p && ! unchanging_p && ! alias_set)
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return;
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alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p,
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alias_set);
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}
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/* Try to output insns to set TARGET equal to the constant C if it can be
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@ -1979,7 +1991,7 @@ alpha_expand_block_move (operands)
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}
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src_done:
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if (nregs > sizeof(data_regs)/sizeof(*data_regs))
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if (nregs > (int)(sizeof(data_regs)/sizeof(*data_regs)))
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abort();
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/*
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@ -2730,7 +2742,7 @@ print_operand (file, x, code)
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&& CONST_DOUBLE_LOW (x) == -1)
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fprintf (file, "q");
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#else
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else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffffffffffff)
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else if (GET_CODE (x) == CONST_INT && INTVAL (x) == -1)
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fprintf (file, "q");
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else if (GET_CODE (x) == CONST_DOUBLE
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&& CONST_DOUBLE_HIGH (x) == 0
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@ -3253,7 +3265,7 @@ alpha_expand_prologue ()
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HOST_WIDE_INT frame_size;
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/* Offset from base reg to register save area. */
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HOST_WIDE_INT reg_offset;
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rtx sa_reg;
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rtx sa_reg, mem;
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int i;
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sa_size = alpha_sa_size ();
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@ -3367,16 +3379,17 @@ alpha_expand_prologue ()
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/* Save regs in stack order. Beginning with VMS PV. */
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if (TARGET_OPEN_VMS && vms_is_stack_procedure)
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{
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FRP (emit_move_insn (gen_rtx_MEM (DImode, stack_pointer_rtx),
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gen_rtx_REG (DImode, REG_PV)));
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mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
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}
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/* Save register RA next. */
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if (imask & (1L << REG_RA))
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{
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FRP (emit_move_insn (gen_rtx_MEM (DImode,
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plus_constant (sa_reg, reg_offset)),
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gen_rtx_REG (DImode, REG_RA)));
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mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
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imask &= ~(1L << REG_RA);
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reg_offset += 8;
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}
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@ -3385,18 +3398,18 @@ alpha_expand_prologue ()
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for (i = 0; i < 32; i++)
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if (imask & (1L << i))
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{
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FRP (emit_move_insn (gen_rtx_MEM (DImode,
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plus_constant (sa_reg, reg_offset)),
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gen_rtx_REG (DImode, i)));
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mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
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reg_offset += 8;
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}
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for (i = 0; i < 32; i++)
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if (fmask & (1L << i))
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{
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FRP (emit_move_insn (gen_rtx_MEM (DFmode,
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plus_constant (sa_reg, reg_offset)),
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gen_rtx_REG (DFmode, i+32)));
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mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
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reg_offset += 8;
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}
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@ -3675,7 +3688,7 @@ alpha_expand_epilogue ()
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HOST_WIDE_INT reg_offset;
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int fp_is_frame_pointer, fp_offset;
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rtx sa_reg, sa_reg_exp = NULL;
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rtx sp_adj1, sp_adj2;
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rtx sp_adj1, sp_adj2, mem;
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int i;
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sa_size = alpha_sa_size ();
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@ -3734,10 +3747,9 @@ alpha_expand_epilogue ()
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if (! alpha_eh_epilogue_sp_ofs)
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{
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FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA),
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gen_rtx_MEM (DImode,
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plus_constant(sa_reg,
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reg_offset))));
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mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
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}
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reg_offset += 8;
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imask &= ~(1L << REG_RA);
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@ -3749,10 +3761,9 @@ alpha_expand_epilogue ()
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fp_offset = reg_offset;
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else
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{
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FRP (emit_move_insn (gen_rtx_REG (DImode, i),
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gen_rtx_MEM (DImode,
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plus_constant(sa_reg,
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reg_offset))));
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mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
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}
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reg_offset += 8;
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}
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@ -3760,10 +3771,9 @@ alpha_expand_epilogue ()
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for (i = 0; i < 32; ++i)
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if (fmask & (1L << i))
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{
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FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32),
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gen_rtx_MEM (DFmode,
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plus_constant(sa_reg,
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reg_offset))));
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mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
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reg_offset += 8;
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}
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}
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@ -3820,9 +3830,9 @@ alpha_expand_epilogue ()
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if (fp_is_frame_pointer)
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{
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emit_insn (gen_blockage ());
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FRP (emit_move_insn (hard_frame_pointer_rtx,
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gen_rtx_MEM (DImode,
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plus_constant(sa_reg, fp_offset))));
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mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, fp_offset));
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MEM_ALIAS_SET (mem) = alpha_sr_alias_set;
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FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
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}
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else if (TARGET_OPEN_VMS)
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{
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@ -4281,6 +4291,13 @@ alpha_handle_trap_shadows (insns)
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/* Alpha can only issue instruction groups simultaneously if they are
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suitibly aligned. This is very processor-specific. */
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enum alphaev4_pipe {
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EV4_STOP = 0,
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EV4_IB0 = 1,
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EV4_IB1 = 2,
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EV4_IBX = 4
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};
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enum alphaev5_pipe {
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EV5_STOP = 0,
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EV5_NONE = 1,
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@ -4292,6 +4309,58 @@ enum alphaev5_pipe {
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EV5_FM = 64
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};
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static enum alphaev4_pipe alphaev4_insn_pipe PROTO((rtx));
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static enum alphaev5_pipe alphaev5_insn_pipe PROTO((rtx));
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static rtx alphaev4_next_group PROTO((rtx, int*, int*));
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static rtx alphaev5_next_group PROTO((rtx, int*, int*));
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static rtx alphaev4_next_nop PROTO((int*));
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static rtx alphaev5_next_nop PROTO((int*));
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static void alpha_align_insns
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PROTO((rtx, int, rtx (*)(rtx, int*, int*), rtx (*)(int*), int));
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static enum alphaev4_pipe
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alphaev4_insn_pipe (insn)
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rtx insn;
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{
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if (recog_memoized (insn) < 0)
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return EV4_STOP;
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if (get_attr_length (insn) != 4)
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return EV4_STOP;
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switch (get_attr_type (insn))
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{
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case TYPE_ILD:
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case TYPE_FLD:
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return EV4_IBX;
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case TYPE_LDSYM:
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case TYPE_IADD:
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case TYPE_ILOG:
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case TYPE_ICMOV:
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case TYPE_ICMP:
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case TYPE_IST:
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case TYPE_FST:
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case TYPE_SHIFT:
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case TYPE_IMUL:
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case TYPE_FBR:
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return EV4_IB0;
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case TYPE_MISC:
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case TYPE_IBR:
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case TYPE_JSR:
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case TYPE_FCPYS:
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case TYPE_FCMOV:
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case TYPE_FADD:
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case TYPE_FDIV:
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case TYPE_FMUL:
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return EV4_IB1;
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default:
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abort();
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}
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}
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static enum alphaev5_pipe
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alphaev5_insn_pipe (insn)
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rtx insn;
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@ -4341,10 +4410,109 @@ alphaev5_insn_pipe (insn)
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}
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}
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/* IN_USE is a mask of the slots currently filled within the
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insn group. The mask bits come from alphaev5_pipe above.
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If EV5_E01 is set, then the insn in EV5_E0 can be swapp
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by the hardware into EV5_E1.
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/* IN_USE is a mask of the slots currently filled within the insn group.
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The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
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the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
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LEN is, of course, the length of the group in bytes. */
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static rtx
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alphaev4_next_group (insn, pin_use, plen)
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rtx insn;
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int *pin_use, *plen;
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{
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int len, in_use;
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len = in_use = 0;
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if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
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|| GET_CODE (PATTERN (insn)) == CLOBBER
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|| GET_CODE (PATTERN (insn)) == USE)
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goto next_and_done;
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while (1)
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{
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enum alphaev4_pipe pipe;
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pipe = alphaev4_insn_pipe (insn);
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switch (pipe)
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{
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case EV4_STOP:
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/* Force complex instructions to start new groups. */
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if (in_use)
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goto done;
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/* If this is a completely unrecognized insn, its an asm.
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We don't know how long it is, so record length as -1 to
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signal a needed realignment. */
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if (recog_memoized (insn) < 0)
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len = -1;
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else
|
||||
len = get_attr_length (insn);
|
||||
goto next_and_done;
|
||||
|
||||
case EV4_IBX:
|
||||
if (in_use & EV4_IB0)
|
||||
{
|
||||
if (in_use & EV4_IB1)
|
||||
goto done;
|
||||
in_use |= EV4_IB1;
|
||||
}
|
||||
else
|
||||
in_use |= EV4_IB0 | EV4_IBX;
|
||||
break;
|
||||
|
||||
case EV4_IB0:
|
||||
if (in_use & EV4_IB0)
|
||||
{
|
||||
if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
|
||||
goto done;
|
||||
in_use |= EV4_IB1;
|
||||
}
|
||||
in_use |= EV4_IB0;
|
||||
break;
|
||||
|
||||
case EV4_IB1:
|
||||
if (in_use & EV4_IB1)
|
||||
goto done;
|
||||
in_use |= EV4_IB1;
|
||||
break;
|
||||
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
len += 4;
|
||||
|
||||
/* Haifa doesn't do well scheduling branches. */
|
||||
if (GET_CODE (insn) == JUMP_INSN)
|
||||
goto next_and_done;
|
||||
|
||||
next:
|
||||
insn = next_nonnote_insn (insn);
|
||||
|
||||
if (!insn || GET_RTX_CLASS (GET_CODE (insn)) != 'i')
|
||||
goto done;
|
||||
|
||||
/* Let Haifa tell us where it thinks insn group boundaries are. */
|
||||
if (GET_MODE (insn) == TImode)
|
||||
goto done;
|
||||
|
||||
if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
|
||||
goto next;
|
||||
}
|
||||
|
||||
next_and_done:
|
||||
insn = next_nonnote_insn (insn);
|
||||
|
||||
done:
|
||||
*plen = len;
|
||||
*pin_use = in_use;
|
||||
return insn;
|
||||
}
|
||||
|
||||
/* IN_USE is a mask of the slots currently filled within the insn group.
|
||||
The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
|
||||
the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
|
||||
|
||||
LEN is, of course, the length of the group in bytes. */
|
||||
|
||||
@ -4402,7 +4570,7 @@ alphaev5_next_group (insn, pin_use, plen)
|
||||
case EV5_E0:
|
||||
if (in_use & EV5_E0)
|
||||
{
|
||||
if (!(in_use & EV5_E01) || in_use & EV5_E1)
|
||||
if (!(in_use & EV5_E01) || (in_use & EV5_E1))
|
||||
goto done;
|
||||
in_use |= EV5_E1;
|
||||
}
|
||||
@ -4475,9 +4643,73 @@ alphaev5_next_group (insn, pin_use, plen)
|
||||
return insn;
|
||||
}
|
||||
|
||||
static rtx
|
||||
alphaev4_next_nop (pin_use)
|
||||
int *pin_use;
|
||||
{
|
||||
int in_use = *pin_use;
|
||||
rtx nop;
|
||||
|
||||
if (!(in_use & EV4_IB0))
|
||||
{
|
||||
in_use |= EV4_IB0;
|
||||
nop = gen_nop ();
|
||||
}
|
||||
else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
|
||||
{
|
||||
in_use |= EV4_IB1;
|
||||
nop = gen_nop ();
|
||||
}
|
||||
else if (TARGET_FP && !(in_use & EV4_IB1))
|
||||
{
|
||||
in_use |= EV4_IB1;
|
||||
nop = gen_fnop ();
|
||||
}
|
||||
else
|
||||
nop = gen_unop ();
|
||||
|
||||
*pin_use = in_use;
|
||||
return nop;
|
||||
}
|
||||
|
||||
static rtx
|
||||
alphaev5_next_nop (pin_use)
|
||||
int *pin_use;
|
||||
{
|
||||
int in_use = *pin_use;
|
||||
rtx nop;
|
||||
|
||||
if (!(in_use & EV5_E1))
|
||||
{
|
||||
in_use |= EV5_E1;
|
||||
nop = gen_nop ();
|
||||
}
|
||||
else if (TARGET_FP && !(in_use & EV5_FA))
|
||||
{
|
||||
in_use |= EV5_FA;
|
||||
nop = gen_fnop ();
|
||||
}
|
||||
else if (TARGET_FP && !(in_use & EV5_FM))
|
||||
{
|
||||
in_use |= EV5_FM;
|
||||
nop = gen_fnop ();
|
||||
}
|
||||
else
|
||||
nop = gen_unop ();
|
||||
|
||||
*pin_use = in_use;
|
||||
return nop;
|
||||
}
|
||||
|
||||
/* The instruction group alignment main loop. */
|
||||
|
||||
static void
|
||||
alphaev5_align_insns (insns)
|
||||
alpha_align_insns (insns, max_align, next_group, next_nop, gp_in_use)
|
||||
rtx insns;
|
||||
int max_align;
|
||||
rtx (*next_group) PROTO((rtx, int*, int*));
|
||||
rtx (*next_nop) PROTO((int*));
|
||||
int gp_in_use;
|
||||
{
|
||||
/* ALIGN is the known alignment for the insn group. */
|
||||
int align;
|
||||
@ -4489,14 +4721,17 @@ alphaev5_align_insns (insns)
|
||||
/* Let shorten branches care for assigning alignments to code labels. */
|
||||
shorten_branches (insns);
|
||||
|
||||
/* Account for the initial GP load, which happens before the scheduled
|
||||
prologue we emitted as RTL. */
|
||||
ofs = prev_in_use = 0;
|
||||
if (alpha_does_function_need_gp())
|
||||
{
|
||||
ofs = 8;
|
||||
prev_in_use = EV5_E01 | EV5_E0;
|
||||
prev_in_use = gp_in_use;
|
||||
}
|
||||
align = (FUNCTION_BOUNDARY/BITS_PER_UNIT < 16
|
||||
? FUNCTION_BOUNDARY/BITS_PER_UNIT : 16);
|
||||
|
||||
align = (FUNCTION_BOUNDARY/BITS_PER_UNIT < max_align
|
||||
? FUNCTION_BOUNDARY/BITS_PER_UNIT : max_align);
|
||||
|
||||
i = insns;
|
||||
if (GET_CODE (i) == NOTE)
|
||||
@ -4504,7 +4739,7 @@ alphaev5_align_insns (insns)
|
||||
|
||||
while (i)
|
||||
{
|
||||
next = alphaev5_next_group (i, &in_use, &len);
|
||||
next = (*next_group)(i, &in_use, &len);
|
||||
|
||||
/* When we see a label, resync alignment etc. */
|
||||
if (GET_CODE (i) == CODE_LABEL)
|
||||
@ -4512,7 +4747,7 @@ alphaev5_align_insns (insns)
|
||||
int new_align = 1 << label_to_alignment (i);
|
||||
if (new_align >= align)
|
||||
{
|
||||
align = new_align < 16 ? new_align : 16;
|
||||
align = new_align < max_align ? new_align : max_align;
|
||||
ofs = 0;
|
||||
}
|
||||
else if (ofs & (new_align-1))
|
||||
@ -4562,30 +4797,25 @@ alphaev5_align_insns (insns)
|
||||
int nop_count = (align - ofs) / 4;
|
||||
rtx where;
|
||||
|
||||
/* Insert nops before labels and branches to truely merge the
|
||||
execution of the nops with the previous instruction group. */
|
||||
where = prev_nonnote_insn (i);
|
||||
if (!where || GET_CODE (where) != CODE_LABEL)
|
||||
if (where)
|
||||
{
|
||||
if (GET_CODE (where) == CODE_LABEL)
|
||||
{
|
||||
rtx where2 = prev_nonnote_insn (where);
|
||||
if (where2 && GET_CODE (where2) == JUMP_INSN)
|
||||
where = where2;
|
||||
}
|
||||
else if (GET_CODE (where) != JUMP_INSN)
|
||||
where = i;
|
||||
}
|
||||
else
|
||||
where = i;
|
||||
|
||||
do
|
||||
{
|
||||
if (!(prev_in_use & EV5_E1))
|
||||
{
|
||||
prev_in_use |= EV5_E1;
|
||||
emit_insn_before (gen_nop(), where);
|
||||
}
|
||||
else if (TARGET_FP && !(prev_in_use & EV5_FA))
|
||||
{
|
||||
prev_in_use |= EV5_FA;
|
||||
emit_insn_before (gen_fnop(), where);
|
||||
}
|
||||
else if (TARGET_FP && !(prev_in_use & EV5_FM))
|
||||
{
|
||||
prev_in_use |= EV5_FM;
|
||||
emit_insn_before (gen_fnop(), where);
|
||||
}
|
||||
else
|
||||
emit_insn_before (gen_unop(), where);
|
||||
}
|
||||
emit_insn_before ((*next_nop)(&prev_in_use), where);
|
||||
while (--nop_count);
|
||||
ofs = 0;
|
||||
}
|
||||
@ -4614,8 +4844,12 @@ alpha_reorg (insns)
|
||||
&& alpha_tp != ALPHA_TP_INSN
|
||||
&& flag_schedule_insns_after_reload)
|
||||
{
|
||||
if (alpha_cpu == PROCESSOR_EV5)
|
||||
alphaev5_align_insns (insns);
|
||||
if (alpha_cpu == PROCESSOR_EV4)
|
||||
alpha_align_insns (insns, 8, alphaev4_next_group,
|
||||
alphaev4_next_nop, EV4_IB0);
|
||||
else if (alpha_cpu == PROCESSOR_EV5)
|
||||
alpha_align_insns (insns, 16, alphaev5_next_group,
|
||||
alphaev5_next_nop, EV5_E01 | EV5_E0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -88,6 +88,10 @@ extern void output_asm_insn PROTO((char *, rtx *));
|
||||
Defined in final.c. */
|
||||
extern int insn_current_reference_address PROTO((rtx));
|
||||
|
||||
/* Find the alignment associated with a CODE_LABEL.
|
||||
Defined in final.c. */
|
||||
extern int label_to_alignment PROTO((rtx));
|
||||
|
||||
/* Output a LABEL_REF, or a bare CODE_LABEL, as an assembler symbol. */
|
||||
extern void output_asm_label PROTO((rtx));
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user