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[AARCH64] Add support for floating-point vcond.
gcc/ * config/aarch64/aarch64-simd.md (aarch64_simd_bsl<mode>_internal): Add floating-point modes. (aarch64_simd_bsl): Likewise. (aarch64_vcond_internal<mode>): Likewise. (vcond<mode><mode>): Likewise. (aarch64_cm<cmp><mode>): Fix constraints, add new modes. * config/aarch64/iterators.md (V_cmp_result): Add V2DF. gcc/testsuite/ * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New. * gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c: Likewise. * gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c: Likewise. * gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c: Likewise. * gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c: Likewise. * gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c: Likewise. * gcc/testsuite/gcc.target/aarch64/vect-fcm.x: Likewise. * gcc/testsuite/lib/target-supports.exp (check_effective_target_vect_cond): Enable for AArch64. From-SVN: r195018
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
4dcd1054bf
commit
385eb93d42
@ -1,3 +1,13 @@
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2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd.md
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(aarch64_simd_bsl<mode>_internal): Add floating-point modes.
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(aarch64_simd_bsl): Likewise.
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(aarch64_vcond_internal<mode>): Likewise.
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(vcond<mode><mode>): Likewise.
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(aarch64_cm<cmp><mode>): Fix constraints, add new modes.
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* config/aarch64/iterators.md (V_cmp_result): Add V2DF.
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2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-builtins.c
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@ -1463,7 +1463,7 @@
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(set_attr "simd_mode" "V2SI")]
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)
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;; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register
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;; vbsl_* intrinsics may compile to any of bsl/bif/bit depending on register
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;; allocation. For an intrinsic of form:
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;; vD = bsl_* (vS, vN, vM)
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;; We can use any of:
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@ -1472,11 +1472,12 @@
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;; bif vD, vM, vS (if D = N, so 0-bits in vS choose bits from vM, else vN)
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(define_insn "aarch64_simd_bsl<mode>_internal"
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[(set (match_operand:VDQ 0 "register_operand" "=w,w,w")
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(unspec:VDQ [(match_operand:VDQ 1 "register_operand" " 0,w,w")
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(match_operand:VDQ 2 "register_operand" " w,w,0")
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(match_operand:VDQ 3 "register_operand" " w,0,w")]
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UNSPEC_BSL))]
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[(set (match_operand:VALL 0 "register_operand" "=w,w,w")
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(unspec:VALL
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[(match_operand:<V_cmp_result> 1 "register_operand" " 0,w,w")
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(match_operand:VALL 2 "register_operand" " w,w,0")
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(match_operand:VALL 3 "register_operand" " w,0,w")]
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UNSPEC_BSL))]
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"TARGET_SIMD"
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"@
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bsl\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype>
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@ -1485,15 +1486,15 @@
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)
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(define_expand "aarch64_simd_bsl<mode>"
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[(set (match_operand:VDQ 0 "register_operand")
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(unspec:VDQ [(match_operand:<V_cmp_result> 1 "register_operand")
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(match_operand:VDQ 2 "register_operand")
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(match_operand:VDQ 3 "register_operand")]
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UNSPEC_BSL))]
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[(set (match_operand:VALL 0 "register_operand")
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(unspec:VALL [(match_operand:<V_cmp_result> 1 "register_operand")
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(match_operand:VALL 2 "register_operand")
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(match_operand:VALL 3 "register_operand")]
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UNSPEC_BSL))]
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"TARGET_SIMD"
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{
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/* We can't alias operands together if they have different modes. */
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operands[1] = gen_lowpart (<MODE>mode, operands[1]);
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operands[1] = gen_lowpart (<V_cmp_result>mode, operands[1]);
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})
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(define_expand "aarch64_vcond_internal<mode>"
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@ -1574,14 +1575,64 @@
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DONE;
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})
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(define_expand "vcond<mode><mode>"
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[(set (match_operand:VDQ 0 "register_operand")
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(if_then_else:VDQ
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(define_expand "aarch64_vcond_internal<mode>"
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[(set (match_operand:VDQF 0 "register_operand")
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(if_then_else:VDQF
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(match_operator 3 "comparison_operator"
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[(match_operand:VDQ 4 "register_operand")
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(match_operand:VDQ 5 "nonmemory_operand")])
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(match_operand:VDQ 1 "register_operand")
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(match_operand:VDQ 2 "register_operand")))]
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[(match_operand:VDQF 4 "register_operand")
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(match_operand:VDQF 5 "nonmemory_operand")])
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(match_operand:VDQF 1 "register_operand")
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(match_operand:VDQF 2 "register_operand")))]
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"TARGET_SIMD"
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{
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int inverse = 0;
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rtx mask = gen_reg_rtx (<V_cmp_result>mode);
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if (!REG_P (operands[5])
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&& (operands[5] != CONST0_RTX (<MODE>mode)))
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operands[5] = force_reg (<MODE>mode, operands[5]);
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switch (GET_CODE (operands[3]))
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{
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case LT:
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inverse = 1;
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/* Fall through. */
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case GE:
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emit_insn (gen_aarch64_cmge<mode> (mask, operands[4], operands[5]));
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break;
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case LE:
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inverse = 1;
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/* Fall through. */
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case GT:
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emit_insn (gen_aarch64_cmgt<mode> (mask, operands[4], operands[5]));
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break;
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case NE:
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inverse = 1;
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/* Fall through. */
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case EQ:
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emit_insn (gen_aarch64_cmeq<mode> (mask, operands[4], operands[5]));
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break;
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default:
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gcc_unreachable ();
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}
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if (inverse)
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emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], mask, operands[2],
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operands[1]));
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else
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emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], mask, operands[1],
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operands[2]));
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DONE;
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})
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(define_expand "vcond<mode><mode>"
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[(set (match_operand:VALL 0 "register_operand")
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(if_then_else:VALL
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(match_operator 3 "comparison_operator"
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[(match_operand:VALL 4 "register_operand")
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(match_operand:VALL 5 "nonmemory_operand")])
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(match_operand:VALL 1 "register_operand")
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(match_operand:VALL 2 "register_operand")))]
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"TARGET_SIMD"
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{
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emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1],
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@ -2866,6 +2917,22 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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;; fcm(eq|ge|le|lt|gt)
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(define_insn "aarch64_cm<cmp><mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
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(unspec:<V_cmp_result>
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[(match_operand:VDQF 1 "register_operand" "w,w")
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(match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")]
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VCMP_S))]
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"TARGET_SIMD"
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"@
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fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>
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fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
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[(set_attr "simd_type" "simd_fcmp")
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(set_attr "simd_mode" "<MODE>")]
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)
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;; addp
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(define_insn "aarch64_addp<mode>"
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@ -1,3 +1,15 @@
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2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c: New.
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* gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
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* gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c: Likewise.
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* gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
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* gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
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* gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
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* gcc/testsuite/gcc.target/aarch64/vect-fcm.x: Likewise.
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* gcc/testsuite/lib/target-supports.exp
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(check_effective_target_vect_cond): Enable for AArch64.
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2013-01-08 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/vsqrt.c (test_square_root_v2sf): Use
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
Normal file
14
gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
Normal file
@ -0,0 +1,14 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
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#define FTYPE double
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#define OP ==
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#define INV_OP !=
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#include "vect-fcm.x"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
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/* { dg-final { scan-assembler-times "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 2 } } */
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/* { dg-final { scan-assembler-times "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" 1 } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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/* { dg-final { cleanup-saved-temps } } */
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
Normal file
14
gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
Normal file
@ -0,0 +1,14 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
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#define FTYPE float
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#define OP ==
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#define INV_OP !=
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#include "vect-fcm.x"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
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/* { dg-final { scan-assembler-times "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" 2 } } */
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/* { dg-final { scan-assembler-times "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" 1 } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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/* { dg-final { cleanup-saved-temps } } */
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
Normal file
14
gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
Normal file
@ -0,0 +1,14 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
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#define FTYPE double
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#define OP >=
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#define INV_OP <
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#include "vect-fcm.x"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
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/* { dg-final { scan-assembler-times "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 2 } } */
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/* { dg-final { scan-assembler-times "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" 1 } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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/* { dg-final { cleanup-saved-temps } } */
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
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@ -0,0 +1,14 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
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#define FTYPE float
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#define OP >=
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#define INV_OP <
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#include "vect-fcm.x"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
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/* { dg-final { scan-assembler-times "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" 2 } } */
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/* { dg-final { scan-assembler-times "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" 1 } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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/* { dg-final { cleanup-saved-temps } } */
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
Normal file
14
gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
Normal file
@ -0,0 +1,14 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
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#define FTYPE double
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#define OP >
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#define INV_OP <=
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#include "vect-fcm.x"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
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/* { dg-final { scan-assembler-times "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 2 } } */
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/* { dg-final { scan-assembler-times "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" 1 } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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/* { dg-final { cleanup-saved-temps } } */
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
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14
gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
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@ -0,0 +1,14 @@
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/* { dg-do run } */
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/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
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#define FTYPE float
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#define OP >
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#define INV_OP <=
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#include "vect-fcm.x"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
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/* { dg-final { scan-assembler-times "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" 2 } } */
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/* { dg-final { scan-assembler-times "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" 1 } } */
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/* { dg-final { cleanup-tree-dump "vect" } } */
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/* { dg-final { cleanup-saved-temps } } */
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56
gcc/testsuite/gcc.target/aarch64/vect-fcm.x
Normal file
56
gcc/testsuite/gcc.target/aarch64/vect-fcm.x
Normal file
@ -0,0 +1,56 @@
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#include <stdlib.h>
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#define N 16
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FTYPE input1[N] =
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{2.0, 4.0, 8.0, 16.0,
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2.125, 4.25, 8.5, 17.0,
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-2.0, -4.0, -8.0, -16.0,
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-2.125, -4.25, -8.5, -17.0};
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FTYPE input2[N] =
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{-2.0, 4.0, -8.0, 16.0,
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2.125, -4.25, 8.5, -17.0,
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2.0, -4.0, 8.0, -16.0,
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-2.125, 4.25, -8.5, 17.0};
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void
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foo (FTYPE *in1, FTYPE *in2, FTYPE *output)
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{
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int i = 0;
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/* Vectorizable. */
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for (i = 0; i < N; i++)
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output[i] = (in1[i] OP in2[i]) ? 2.0 : 4.0;
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}
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void
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bar (FTYPE *in1, FTYPE *in2, FTYPE *output)
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{
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int i = 0;
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/* Vectorizable. */
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for (i = 0; i < N; i++)
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output[i] = (in1[i] INV_OP in2[i]) ? 4.0 : 2.0;
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}
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void
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foobar (FTYPE *in1, FTYPE *in2, FTYPE *output)
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{
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int i = 0;
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/* Vectorizable. */
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for (i = 0; i < N; i++)
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output[i] = (in1[i] OP 0.0) ? 4.0 : 2.0;
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}
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int
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main (int argc, char **argv)
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{
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FTYPE out1[N];
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FTYPE out2[N];
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int i = 0;
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foo (input1, input2, out1);
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bar (input1, input2, out2);
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for (i = 0; i < N; i++)
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if (out1[i] != out2[i])
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abort ();
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return 0;
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}
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@ -3699,7 +3699,8 @@ proc check_effective_target_vect_condition { } {
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verbose "check_effective_target_vect_cond: using cached result" 2
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} else {
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set et_vect_cond_saved 0
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if { [istarget powerpc*-*-*]
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if { [istarget aarch64*-*-*]
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|| [istarget powerpc*-*-*]
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|| [istarget ia64-*-*]
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|| [istarget i?86-*-*]
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|| [istarget spu-*-*]
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