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i386.md: Apply trunc_int_for_mode() to GEN_INT operands that make it to RTL.

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* config/i386/i386.md: Apply trunc_int_for_mode() to GEN_INT
operands that make it to RTL.

From-SVN: r41279
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Alexandre Oliva 2001-04-12 02:59:43 +00:00 committed by Alexandre Oliva
parent 125404c5f3
commit 383252a724
2 changed files with 27 additions and 14 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2001-04-11 Alexandre Oliva <aoliva@redhat.com>
* config/i386/i386.md: Apply trunc_int_for_mode() to GEN_INT
operands that make it to RTL.
2001-04-11 Stan Shebs <shebs@apple.com>
Add Darwin (Mac OS X kernel) native support.

36
gcc/config/i386/i386.md
View File

@ -8113,7 +8113,8 @@
mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
operands[3] = gen_rtx_AND (mode, operands[0], GEN_INT (mask));
operands[3] = gen_rtx_AND (mode, operands[0],
GEN_INT (trunc_int_for_mode (mask, mode)));
}")
;; %%% This used to optimize known byte-wide and operations to memory,
@ -9335,7 +9336,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (0x80000000);
"operands[1] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_split
@ -9354,7 +9355,7 @@
size = 10;
operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
operands[0] = adj_offsettable_operand (operands[0], size - 1);
operands[1] = GEN_INT (0x80);
operands[1] = GEN_INT (trunc_int_for_mode (0x80, QImode));
}")
(define_expand "negdf2"
@ -9390,7 +9391,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
(clobber (reg:CC 17))])]
"operands[4] = GEN_INT (0x80000000);
"operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
split_di (operands+0, 1, operands+2, operands+3);")
(define_expand "negxf2"
@ -9651,7 +9652,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (~0x80000000);
"operands[1] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
(define_split
@ -9670,7 +9671,7 @@
size = 10;
operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
operands[0] = adj_offsettable_operand (operands[0], size - 1);
operands[1] = GEN_INT (~0x80);
operands[1] = GEN_INT (trunc_int_for_mode (~0x80, QImode));
}")
(define_expand "absdf2"
@ -9773,7 +9774,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
(clobber (reg:CC 17))])]
"operands[4] = GEN_INT (~0x80000000);
"operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
split_di (operands+0, 1, operands+2, operands+3);")
(define_expand "absxf2"
@ -9817,7 +9818,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (~0x8000);
"operands[1] = GEN_INT (trunc_int_for_mode (~0x8000, SImode));
operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
(define_insn "*abstf2_if"
@ -9843,7 +9844,7 @@
"TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (~0x8000);
"operands[1] = GEN_INT (trunc_int_for_mode (~0x8000, SImode));
operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
(define_insn "*abssf2_1"
@ -10225,7 +10226,8 @@
[(set (match_dup 0)
(mult:DI (match_dup 1)
(match_dup 2)))]
"operands[2] = GEN_INT (1 << INTVAL (operands[2]));")
"operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
DImode));")
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
@ -10436,7 +10438,8 @@
rtx pat;
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = GEN_INT (1 << INTVAL (operands[2]));
operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
Pmode));
pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
if (Pmode != SImode)
pat = gen_rtx_SUBREG (SImode, pat, 0);
@ -10496,7 +10499,8 @@
"
{
operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = GEN_INT (1 << INTVAL (operands[2]));
operands[2] = GEN_INT (trunc_int_for_mode (1 << INTVAL (operands[2]),
Pmode));
}")
;; This pattern can't accept a variable shift count, since shifts by
@ -16142,7 +16146,9 @@
(set (match_dup 0)
(and:SI (match_dup 1) (match_dup 2)))])]
"operands[2]
= GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (GET_MODE (operands[0])));
= GEN_INT (trunc_int_for_mode (INTVAL (operands[2])
& GET_MODE_MASK (GET_MODE (operands[0])),
SImode));
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);")
@ -16160,7 +16166,9 @@
(compare:CCNO (and:SI (match_dup 0) (match_dup 1))
(const_int 0)))]
"operands[1]
= GEN_INT (INTVAL (operands[1]) & GET_MODE_MASK (GET_MODE (operands[0])));
= GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
& GET_MODE_MASK (GET_MODE (operands[0])),
SImode));
operands[0] = gen_lowpart (SImode, operands[0]);")
(define_split