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[AArch64] Don't rely on REG_EQUAL notes to combine SVE BIC

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This patch generalises the SVE BIC pattern so that it doesn't
rely on REG_EQUAL notes.  The danger with relying on the notes
is that an optimisation could for example replace the original
(not ...) note with an (unspec ... UNSPEC_MERGE_PTRUE) in which
the predicate is a constant.  That's a legitimate change and
could even be useful in some situations.

The patch also makes the operand order match the SVE operand order in
both the vector and predicate BIC patterns, which makes things easier
for the ACLE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (bic<mode>3): Rename to...
	(*bic<SVE_I:mode>3): ...this.  Match the form that an SVE inverse
	actually has, rather than relying on REG_EQUAL notes.
	Make the insn operand order match the SVE operand order.
	(*<nlogical><PRED_ALL:mode>3): Make the insn operand order match
	the SVE operand order.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274416
This commit is contained in:
Richard Sandiford 2019-08-14 08:08:08 +00:00 committed by Richard Sandiford
parent 678faefcab
commit 35d6c5913d
2 changed files with 24 additions and 9 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
* config/aarch64/aarch64-sve.md (bic<mode>3): Rename to...
(*bic<SVE_I:mode>3): ...this. Match the form that an SVE inverse
actually has, rather than relying on REG_EQUAL notes.
Make the insn operand order match the SVE operand order.
(*<nlogical><PRED_ALL:mode>3): Make the insn operand order match
the SVE operand order.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.c (aarch64_target_reg): New function.

23
gcc/config/aarch64/aarch64-sve.md
View File

@ -1779,15 +1779,20 @@
;; - BIC
;; -------------------------------------------------------------------------
;; REG_EQUAL notes on "not<mode>3" should ensure that we can generate
;; this pattern even though the NOT instruction itself is predicated.
(define_insn "bic<mode>3"
(define_insn_and_rewrite "*bic<mode>3"
[(set (match_operand:SVE_I 0 "register_operand" "=w")
(and:SVE_I
(not:SVE_I (match_operand:SVE_I 1 "register_operand" "w"))
(match_operand:SVE_I 2 "register_operand" "w")))]
(unspec:SVE_I
[(match_operand 3)
(not:SVE_I (match_operand:SVE_I 2 "register_operand" "w"))]
UNSPEC_MERGE_PTRUE)
(match_operand:SVE_I 1 "register_operand" "w")))]
"TARGET_SVE"
"bic\t%0.d, %2.d, %1.d"
"bic\t%0.d, %1.d, %2.d"
"&& !CONSTANT_P (operands[3])"
{
operands[3] = CONSTM1_RTX (<VPRED>mode);
}
)
;; -------------------------------------------------------------------------
@ -2451,11 +2456,11 @@
[(set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
(and:PRED_ALL
(NLOGICAL:PRED_ALL
(not:PRED_ALL (match_operand:PRED_ALL 2 "register_operand" "Upa"))
(match_operand:PRED_ALL 3 "register_operand" "Upa"))
(not:PRED_ALL (match_operand:PRED_ALL 3 "register_operand" "Upa"))
(match_operand:PRED_ALL 2 "register_operand" "Upa"))
(match_operand:PRED_ALL 1 "register_operand" "Upa")))]
"TARGET_SVE"
"<nlogical>\t%0.b, %1/z, %3.b, %2.b"
"<nlogical>\t%0.b, %1/z, %2.b, %3.b"
)
;; -------------------------------------------------------------------------