diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e7449de84be0..6ef5c8464cd3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+Sun Feb  9 23:58:33 CET 2003  Jan Hubicka  <jh@suse.cz>
+
+	* i386.md (floathi*): Deal with SSE.
+
 Sun Feb  9 23:54:59 CET 2003  Jan Hubicka  <jh@suse.cz>
 
 	* simplify-rtx.c (simplify_unary_operation,
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 97c6d9e6a75b..a751513bd274 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4842,10 +4842,23 @@
 ;; Even though we only accept memory inputs, the backend _really_
 ;; wants to be able to do this between registers.
 
-(define_insn "floathisf2"
+(define_expand "floathisf2"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
+  "TARGET_SSE || TARGET_80387"
+{
+  if (TARGET_SSE && TARGET_SSE_MATH)
+    {
+      emit_insn (gen_floatsisf2 (operands[0],
+				 convert_to_mode (SImode, operands[1], 0)));
+      DONE;
+    }
+})
+
+(define_insn "*floathisf2_1"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && !TARGET_SSE"
+  "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
   "@
    fild%z1\t%1
    #"
@@ -4956,10 +4969,23 @@
   DONE;
 })
 
-(define_insn "floathidf2"
+(define_expand "floathidf2"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
+  "TARGET_SSE2 || TARGET_80387"
+{
+  if (TARGET_SSE && TARGET_SSE_MATH)
+    {
+      emit_insn (gen_floatsidf2 (operands[0],
+				 convert_to_mode (SImode, operands[1], 0)));
+      DONE;
+    }
+})
+
+(define_insn "*floathidf2_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && !TARGET_SSE2"
+  "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
   "@
    fild%z1\t%1
    #"