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re PR target/42495 (redundant memory load)

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PR target/42495
	PR middle-end/42574
	* config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants.
	* config/arm/arm.md (define_split "J", define_split "K"): Make
	IRA/reload friendly.

From-SVN: r162594
This commit is contained in:
Maxim Kuvyrkov 2010-07-27 19:42:15 +00:00 committed by Maxim Kuvyrkov
parent eae7938e45
commit 3393e880c6
3 changed files with 24 additions and 7 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com>
PR target/42495
PR middle-end/42574
* config/arm/arm.c (thumb1_size_rtx_costs): Add cost for "J" constants.
* config/arm/arm.md (define_split "J", define_split "K"): Make
IRA/reload friendly.
2010-07-27 Maxim Kuvyrkov <maxim@codesourcery.com>
* gcse.c (insert_insn_end_basic_block): Update signature, remove

4
gcc/config/arm/arm.c
View File

@ -7003,6 +7003,10 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
{
if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
return 0;
/* See split "TARGET_THUMB1 && satisfies_constraint_J". */
if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
return COSTS_N_INSNS (2);
/* See split "TARGET_THUMB1 && satisfies_constraint_K". */
if (thumb_shiftable_const (INTVAL (x)))
return COSTS_N_INSNS (2);
return COSTS_N_INSNS (3);

19
gcc/config/arm/arm.md
View File

@ -5093,17 +5093,21 @@
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"TARGET_THUMB1 && satisfies_constraint_J (operands[1])"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (neg:SI (match_dup 0)))]
"operands[1] = GEN_INT (- INTVAL (operands[1]));"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (neg:SI (match_dup 2)))]
"
{
operands[1] = GEN_INT (- INTVAL (operands[1]));
operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
}"
)
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"TARGET_THUMB1 && satisfies_constraint_K (operands[1])"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (ashift:SI (match_dup 2) (match_dup 3)))]
"
{
unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu;
@ -5114,12 +5118,13 @@
if ((val & (mask << i)) == val)
break;
/* Shouldn't happen, but we don't want to split if the shift is zero. */
/* Don't split if the shift is zero. */
if (i == 0)
FAIL;
operands[1] = GEN_INT (val >> i);
operands[2] = GEN_INT (i);
operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
operands[3] = GEN_INT (i);
}"
)