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rs6000: Simplify some conditions or code related to TARGET_DIRECT_MOVE
When I was making a patch to rework TARGET_P8_VECTOR, I
noticed that there are some redundant checks and dead code
related to TARGET_DIRECT_MOVE, so I made this patch as one
separated preparatory patch, it consists of:
- Check either TARGET_DIRECT_MOVE or TARGET_P8_VECTOR only
according to the context, rather than checking both of
them since they are actually the same (TARGET_DIRECT_MOVE
is defined as TARGET_P8_VECTOR).
- Simplify TARGET_VSX && TARGET_DIRECT_MOVE as
TARGET_DIRECT_MOVE since direct move ensures VSX enabled.
- Replace some TARGET_POWERPC64 && TARGET_DIRECT_MOVE as
TARGET_DIRECT_MOVE_64BIT to simplify it.
- Remove some dead code guarded with TARGET_DIRECT_MOVE
but the condition never holds here.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Simplify
TARGET_P8_VECTOR && TARGET_DIRECT_MOVE as TARGET_P8_VECTOR.
(rs6000_output_move_128bit): Simplify TARGET_VSX && TARGET_DIRECT_MOVE
as TARGET_DIRECT_MOVE.
* config/rs6000/rs6000.h (TARGET_XSCVDPSPN): Simplify conditions
TARGET_DIRECT_MOVE || TARGET_P8_VECTOR as TARGET_P8_VECTOR.
(TARGET_XSCVSPDPN): Likewise.
(TARGET_DIRECT_MOVE_128): Simplify TARGET_DIRECT_MOVE &&
TARGET_POWERPC64 as TARGET_DIRECT_MOVE_64BIT.
(TARGET_VEXTRACTUB): Likewise.
(TARGET_DIRECT_MOVE_64BIT): Simplify TARGET_P8_VECTOR &&
TARGET_DIRECT_MOVE as TARGET_DIRECT_MOVE.
* config/rs6000/rs6000.md (signbit<mode>2, @signbit<mode>2_dm,
*signbit<mode>2_dm_mem, floatsi<mode>2_lfiwax,
floatsi<SFDF:mode>2_lfiwax_<QHI:mode>_mem_zext,
floatunssi<mode>2_lfiwzx, float<QHI:mode><SFDF:mode>2,
*float<QHI:mode><SFDF:mode>2_internal, floatuns<QHI:mode><SFDF:mode>2,
*floatuns<QHI:mode><SFDF:mode>2_internal, p8_mtvsrd_v16qidi2,
p8_mtvsrd_df, p8_xxpermdi_<mode>, reload_vsx_from_gpr<mode>,
p8_mtvsrd_sf, reload_vsx_from_gprsf, p8_mfvsrd_3_<mode>,
reload_gpr_from_vsx<mode>, reload_gpr_from_vsxsf, unpack<mode>_dm):
Simplify TARGET_DIRECT_MOVE && TARGET_POWERPC64 as
TARGET_DIRECT_MOVE_64BIT.
(unpack<mode>_nodm): Simplify !TARGET_DIRECT_MOVE || !TARGET_POWERPC64
as !TARGET_DIRECT_MOVE_64BIT.
(fix_trunc<mode>si2, fix_trunc<mode>si2_stfiwx,
fix_trunc<mode>si2_internal): Simplify TARGET_P8_VECTOR &&
TARGET_DIRECT_MOVE as TARGET_DIRECT_MOVE.
(fix_trunc<mode>si2_stfiwx, fixuns_trunc<mode>si2_stfiwx): Remove some
dead code as the guard TARGET_DIRECT_MOVE there never holds.
(fixuns_trunc<mode>si2_stfiwx): Change TARGET_P8_VECTOR with
TARGET_DIRECT_MOVE which is a better fit.
* config/rs6000/vsx.md (define_peephole2 for SFmode in GPR): Simplify
TARGET_DIRECT_MOVE && TARGET_POWERPC64 as TARGET_DIRECT_MOVE_64BIT.
This commit is contained in:
Kewen Lin
Kewen Lin
parent
e7e6608387
commit
33386d1421
@ -4055,7 +4055,7 @@ rs6000_option_override_internal (bool global_init_p)
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support. If we only have ISA 2.06 support, and the user did not specify
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the switch, leave it set to -1 so the movmisalign patterns are enabled,
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but we don't enable the full vectorization support */
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if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
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if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR)
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TARGET_ALLOW_MOVMISALIGN = 1;
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else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
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@ -13799,7 +13799,7 @@ rs6000_output_move_128bit (rtx operands[])
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? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
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: "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
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else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
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else if (TARGET_DIRECT_MOVE && src_vsx_p)
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return "#";
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}
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@ -469,13 +469,11 @@ extern int rs6000_vector_align[];
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/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that. */
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#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
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#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
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#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
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#define TARGET_XSCVDPSPN TARGET_P8_VECTOR
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#define TARGET_XSCVSPDPN TARGET_P8_VECTOR
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#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
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#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
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&& TARGET_POWERPC64)
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#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
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&& TARGET_POWERPC64)
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#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT)
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#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT)
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/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
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#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
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@ -555,7 +553,6 @@ extern int rs6000_vector_align[];
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the calculation in 64-bit GPRs and then is transfered to the vector
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registers. */
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#define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
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&& TARGET_P8_VECTOR \
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&& TARGET_POWERPC64)
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/* Inlining allows targets to define the meanings of bits in target_info
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@ -5296,7 +5296,7 @@
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(match_dup 6))]
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"TARGET_HARD_FLOAT
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&& (!FLOAT128_IEEE_P (<MODE>mode)
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|| (TARGET_POWERPC64 && TARGET_DIRECT_MOVE))"
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|| TARGET_DIRECT_MOVE_64BIT)"
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{
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if (FLOAT128_IEEE_P (<MODE>mode))
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{
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@ -5339,7 +5339,7 @@
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa,r")]
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UNSPEC_SIGNBIT))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"@
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mfvsrd %0,%x1
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#"
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@ -5358,7 +5358,7 @@
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[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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(unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "m")]
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UNSPEC_SIGNBIT))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& 1"
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[(set (match_dup 0)
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@ -5872,7 +5872,7 @@
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rtx src = operands[1];
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rtx tmp;
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if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
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if (!MEM_P (src) && TARGET_DIRECT_MOVE_64BIT)
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tmp = convert_to_mode (DImode, src, false);
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else
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{
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@ -5928,7 +5928,7 @@
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(match_operand:QHI 1 "indexed_or_indirect_operand" "Z,Z"))))
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(clobber (match_scratch:DI 2 "=d,wa"))]
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"TARGET_HARD_FLOAT && <SI_CONVERT_FP> && TARGET_P9_VECTOR
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&& TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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&& TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& 1"
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[(pc)]
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@ -5968,7 +5968,7 @@
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rtx src = operands[1];
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rtx tmp;
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if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
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if (!MEM_P (src) && TARGET_DIRECT_MOVE_64BIT)
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tmp = convert_to_mode (DImode, src, true);
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else
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{
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@ -6187,7 +6187,7 @@
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(clobber (match_scratch:DI 2))
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(clobber (match_scratch:DI 3))
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(clobber (match_scratch:<QHI:MODE> 4))])]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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{
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if (MEM_P (operands[1]))
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operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
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@ -6200,7 +6200,7 @@
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(clobber (match_scratch:DI 2 "=v,wa,v"))
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(clobber (match_scratch:DI 3 "=X,r,X"))
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(clobber (match_scratch:<QHI:MODE> 4 "=X,X,v"))]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -6240,7 +6240,7 @@
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(match_operand:QHI 1 "input_operand")))
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(clobber (match_scratch:DI 2))
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(clobber (match_scratch:DI 3))])]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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{
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if (MEM_P (operands[1]))
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operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
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@ -6252,7 +6252,7 @@
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(match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
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(clobber (match_scratch:DI 2 "=v,wa,wa"))
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(clobber (match_scratch:DI 3 "=X,r,X"))]
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
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"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -6285,7 +6285,7 @@
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(fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
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"TARGET_HARD_FLOAT"
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{
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if (!(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE))
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if (!TARGET_DIRECT_MOVE)
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{
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rtx src = force_reg (<MODE>mode, operands[1]);
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@ -6310,7 +6310,7 @@
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(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
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(clobber (match_scratch:DI 2 "=d"))]
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"TARGET_HARD_FLOAT && TARGET_STFIWX && can_create_pseudo_p ()
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&& !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
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&& !TARGET_DIRECT_MOVE"
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"#"
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"&& 1"
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[(pc)]
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@ -6329,12 +6329,6 @@
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emit_insn (gen_stfiwx (dest, tmp));
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DONE;
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}
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else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE && !MEM_P (dest))
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{
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dest = gen_lowpart (DImode, dest);
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emit_move_insn (dest, tmp);
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DONE;
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}
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else
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{
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rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
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@ -6352,7 +6346,7 @@
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
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(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
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"TARGET_HARD_FLOAT
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&& !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
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&& !TARGET_DIRECT_MOVE"
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"#"
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"&& 1"
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[(pc)]
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@ -6458,7 +6452,7 @@
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(clobber (match_scratch:DI 2 "=d"))]
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"TARGET_HARD_FLOAT && TARGET_FCTIWUZ
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&& TARGET_STFIWX && can_create_pseudo_p ()
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&& !TARGET_P8_VECTOR"
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&& !TARGET_DIRECT_MOVE"
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"#"
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"&& 1"
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[(pc)]
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@ -6477,12 +6471,6 @@
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emit_insn (gen_stfiwx (dest, tmp));
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DONE;
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}
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else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
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{
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dest = gen_lowpart (DImode, dest);
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emit_move_insn (dest, tmp);
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DONE;
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}
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else
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{
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rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
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@ -9572,7 +9560,7 @@
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[(set (match_operand:V16QI 0 "register_operand" "=wa")
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(unspec:V16QI [(match_operand:DI 1 "register_operand" "r")]
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UNSPEC_P8V_MTVSRD))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"mtvsrd %x0,%1"
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[(set_attr "type" "mtvsr")])
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@ -9606,7 +9594,7 @@
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[(set (match_operand:DF 0 "register_operand" "=wa")
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(unspec:DF [(match_operand:DI 1 "register_operand" "r")]
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UNSPEC_P8V_MTVSRD))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"mtvsrd %x0,%1"
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[(set_attr "type" "mtvsr")])
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@ -9616,7 +9604,7 @@
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(match_operand:DF 1 "register_operand" "wa")
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(match_operand:DF 2 "register_operand" "wa")]
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UNSPEC_P8V_XXPERMDI))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"xxpermdi %x0,%x1,%x2,0"
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[(set_attr "type" "vecperm")])
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@ -9626,7 +9614,7 @@
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[(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
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UNSPEC_P8V_RELOAD_FROM_GPR))
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(clobber (match_operand:IF 2 "register_operand" "=wa"))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -9671,7 +9659,7 @@
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[(set (match_operand:SF 0 "register_operand" "=wa")
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(unspec:SF [(match_operand:DI 1 "register_operand" "r")]
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UNSPEC_P8V_MTVSRD))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"mtvsrd %x0,%1"
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[(set_attr "type" "mtvsr")])
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@ -9680,7 +9668,7 @@
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(unspec:SF [(match_operand:SF 1 "register_operand" "r")]
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UNSPEC_P8V_RELOAD_FROM_GPR))
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(clobber (match_operand:DI 2 "register_operand" "=r"))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -9706,7 +9694,7 @@
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[(set (match_operand:DF 0 "register_operand" "=r")
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(unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
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UNSPEC_P8V_RELOAD_FROM_VSX))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"mfvsrd %0,%x1"
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[(set_attr "type" "mfvsr")])
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@ -9716,7 +9704,7 @@
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[(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
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UNSPEC_P8V_RELOAD_FROM_VSX))
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(clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -9744,7 +9732,7 @@
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(unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
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UNSPEC_P8V_RELOAD_FROM_VSX))
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(clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
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"TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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@ -14873,7 +14861,7 @@
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[(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
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(match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
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UNSPEC_UNPACK_128BIT))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (<MODE>mode)"
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"TARGET_DIRECT_MOVE_64BIT && FLOAT128_2REG_P (<MODE>mode)"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 3))]
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@ -14896,7 +14884,7 @@
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[(match_operand:FMOVE128 1 "register_operand" "d,d,r")
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(match_operand:QI 2 "const_0_to_1_operand" "i,i,i")]
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UNSPEC_UNPACK_128BIT))]
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"(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)"
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"!TARGET_DIRECT_MOVE_64BIT && FLOAT128_2REG_P (<MODE>mode)"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 3))]
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@ -6338,7 +6338,7 @@
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(set (match_operand:SF SFBOOL_MTVSR_D "vsx_register_operand")
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(unspec:SF [(match_dup SFBOOL_SHL_D)] UNSPEC_P8V_MTVSRD))]
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"TARGET_POWERPC64 && TARGET_DIRECT_MOVE
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"TARGET_DIRECT_MOVE_64BIT
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/* The REG_P (xxx) tests prevents SUBREG's, which allows us to use REGNO
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to compare registers, when the mode is different. */
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&& REG_P (operands[SFBOOL_MFVSR_D]) && REG_P (operands[SFBOOL_BOOL_D])
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