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pa.c (hppa_legitimize_address): Don't lose for (plus (plus (mult (A) (shadd_const)) (B)) (C)) if...
* pa.c (hppa_legitimize_address): Don't lose for
(plus (plus (mult (A) (shadd_const)) (B)) (C)) if
B + C isn't a valid address for indexing.
(basereg_operand): Only accept base registers after
cse has completed. Don't accept the frame pointer if
it's likely to be eliminated.
* pa.md (unscaled indexing patterns): Add variants with
basereg and index register reversed.
(HImode and QImode loads): Add zero extended variants.
From-SVN: r11625
This commit is contained in:
Jeff Law
parent
fdb5537fe0
commit
31d4f31fd7
@ -767,19 +767,19 @@ hppa_legitimize_address (x, oldx, mode)
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{
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rtx regx1, regx2;
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/* Add the two unscaled terms B and C; only force them into registers
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if it's absolutely necessary. */
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/* Add the two unscaled terms B and C; if either B or C isn't
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a register or small constant int, then fail. */
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regx1 = XEXP (XEXP (x, 0), 1);
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if (! (GET_CODE (regx1) == REG
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|| (GET_CODE (regx1) == CONST_INT
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&& INT_14_BITS (regx1))))
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regx1 = force_reg (Pmode, force_operand (XEXP (XEXP (x, 0), 1), 0));
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return orig;
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regx2 = XEXP (x, 1);
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if (! (GET_CODE (regx2) == REG
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|| (GET_CODE (regx2) == CONST_INT
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&& INT_14_BITS (regx2))))
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regx2 = force_reg (Pmode, force_operand (XEXP (x, 1), 0));
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return orig;
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/* Add them, make sure the result is in canonical form. */
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if (GET_CODE (regx1) == REG)
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@ -4941,6 +4941,12 @@ basereg_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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/* cse will create some unscaled indexed addresses, however; it
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generally isn't a win on the PA, so avoid creating unscaled
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indexed addresses until after cse is finished. */
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if (!cse_not_expected)
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return 0;
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/* Once reload has started everything is considered valid. Reload should
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only create indexed addresses using the stack/frame pointer, and any
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others were checked for validity when created by the combine pass.
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@ -4952,8 +4958,14 @@ basereg_operand (op, mode)
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if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
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return (GET_CODE (op) == REG || GET_CODE (op) == CONST_INT);
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/* Stack and frame pointers are always OK for indexing. */
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if (op == stack_pointer_rtx || op == frame_pointer_rtx)
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/* Stack is always OK for indexing. */
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if (op == stack_pointer_rtx)
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return 1;
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/* While it's always safe to index off the frame pointer, it's not
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always profitable, particularly when the frame pointer is being
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eliminated. */
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if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
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return 1;
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/* The only other valid OPs are pseudo registers with
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@ -1527,6 +1527,25 @@
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[2] == hard_frame_pointer_rtx
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|| operands[2] == stack_pointer_rtx)
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return \"ldwx %1(0,%2),%0\";
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else
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return \"ldwx %2(0,%1),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
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@ -1851,7 +1870,20 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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; Same thing with zero extension.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:HI
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(plus:SI
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(mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"ldhx,s %2(0,%1),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; These variants of the above insns can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Note how operand 3 uses a predicate of "const_int_operand", but
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@ -1877,6 +1909,44 @@
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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; Now the zero extended variant.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=&r")
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(zero_extend:SI (mem:HI (plus:SI (plus:SI
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(mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rI")))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh1addl %2,%1,%0\;ldh %3(0,%0),%0\";
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else
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return \"sh1addl %2,%1,%0\;ldhx %3(0,%0),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[2] == hard_frame_pointer_rtx
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|| operands[2] == stack_pointer_rtx)
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return \"ldhx %1(0,%2),%0\";
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else
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return \"ldhx %2(0,%1),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
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@ -1896,6 +1966,49 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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; Now zero extended variants.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:HI
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(plus:SI
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(match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[2] == hard_frame_pointer_rtx
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|| operands[2] == stack_pointer_rtx)
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return \"ldhx %1(0,%2),%0\";
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else
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return \"ldhx %2(0,%1),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:HI
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(plus:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "basereg_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[1] == hard_frame_pointer_rtx
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|| operands[1] == stack_pointer_rtx)
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return \"ldhx %2(0,%1),%0\";
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else
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return \"ldhx %1(0,%2),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(mem:HI (plus:SI (match_operand:SI 1 "register_operand" "=r")
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@ -1907,6 +2020,20 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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; And a zero extended variant.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:HI
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(plus:SI
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(match_operand:SI 1 "register_operand" "=r")
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(match_operand:SI 2 "int5_operand" "L")))))
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(set (match_dup 1)
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(plus:SI (match_dup 1) (match_dup 2)))]
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""
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"ldhs,mb %2(0,%1),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "=r")
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(match_operand:SI 1 "int5_operand" "L")))
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@ -1962,6 +2089,25 @@
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[(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
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(set_attr "length" "4,4,4,4,4,4,4,4")])
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(define_insn ""
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[(set (match_operand:QI 0 "register_operand" "=r")
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(mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[2] == hard_frame_pointer_rtx
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|| operands[2] == stack_pointer_rtx)
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return \"ldbx %1(0,%2),%0\";
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else
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return \"ldbx %2(0,%1),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:QI 0 "register_operand" "=r")
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(mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
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@ -1981,6 +2127,91 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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; Indexed byte load with zero extension to SImode or HImode.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:QI
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(plus:SI
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(match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[2] == hard_frame_pointer_rtx
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|| operands[2] == stack_pointer_rtx)
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return \"ldbx %1(0,%2),%0\";
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else
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return \"ldbx %2(0,%1),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:QI
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(plus:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "basereg_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[1] == hard_frame_pointer_rtx
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|| operands[1] == stack_pointer_rtx)
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return \"ldbx %2(0,%1),%0\";
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else
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return \"ldbx %1(0,%2),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (mem:QI
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(plus:SI
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(match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[2] == hard_frame_pointer_rtx
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|| operands[2] == stack_pointer_rtx)
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return \"ldbx %1(0,%2),%0\";
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else
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return \"ldbx %2(0,%1),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (mem:QI
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(plus:SI
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(match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "basereg_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"*
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{
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
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pseudos that don't get hard registers. Deal with it. */
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if (operands[1] == hard_frame_pointer_rtx
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|| operands[1] == stack_pointer_rtx)
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return \"ldbx %2(0,%1),%0\";
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else
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return \"ldbx %1(0,%2),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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|
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(define_insn ""
|
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[(set (match_operand:QI 0 "register_operand" "=r")
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(mem:QI (plus:SI (match_operand:SI 1 "register_operand" "=r")
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@ -1991,6 +2222,29 @@
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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|
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; Now the same thing with zero extensions.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
|
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(zero_extend:SI (mem:QI (plus:SI
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(match_operand:SI 1 "register_operand" "=r")
|
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(match_operand:SI 2 "int5_operand" "L")))))
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(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
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""
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"ldbs,mb %2(0,%1),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
|
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|
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(define_insn ""
|
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (mem:QI (plus:SI
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(match_operand:SI 1 "register_operand" "=r")
|
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(match_operand:SI 2 "int5_operand" "L")))))
|
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(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
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""
|
||||
"ldbs,mb %2(0,%1),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
|
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|
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(define_insn ""
|
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[(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "=r")
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(match_operand:SI 1 "int5_operand" "L")))
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@ -2225,6 +2479,25 @@
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[(set_attr "type" "fpload")
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(set_attr "length" "8")])
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|
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=fx")
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(mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
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||||
"*
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||||
{
|
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/* Reload can create backwards (relative to cse) unscaled index
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address modes when eliminating registers and possibly for
|
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pseudos that don't get hard registers. Deal with it. */
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||||
if (operands[2] == hard_frame_pointer_rtx
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||||
|| operands[2] == stack_pointer_rtx)
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return \"flddx %1(0,%2),%0\";
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else
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return \"flddx %2(0,%1),%0\";
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}"
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[(set_attr "type" "fpload")
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(set_attr "length" "4")])
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|
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=fx")
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(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
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@ -2283,6 +2556,25 @@
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[(set_attr "type" "fpstore")
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(set_attr "length" "8")])
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|
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(define_insn ""
|
||||
[(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
(match_operand:DF 0 "register_operand" "fx"))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
|
||||
"*
|
||||
{
|
||||
/* Reload can create backwards (relative to cse) unscaled index
|
||||
address modes when eliminating registers and possibly for
|
||||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"fstdx %0,%1(0,%2)\";
|
||||
else
|
||||
return \"fstdx %0,%2(0,%1)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "basereg_operand" "r")))
|
||||
@ -2568,6 +2860,25 @@
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=fx")
|
||||
(mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r"))))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
|
||||
"*
|
||||
{
|
||||
/* Reload can create backwards (relative to cse) unscaled index
|
||||
address modes when eliminating registers and possibly for
|
||||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"fldwx %1(0,%2),%0\";
|
||||
else
|
||||
return \"fldwx %2(0,%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=fx")
|
||||
(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
|
||||
@ -2626,6 +2937,25 @@
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
(match_operand:SF 0 "register_operand" "fx"))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
|
||||
"*
|
||||
{
|
||||
/* Reload can create backwards (relative to cse) unscaled index
|
||||
address modes when eliminating registers and possibly for
|
||||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"fstwx %0,%1(0,%2)\";
|
||||
else
|
||||
return \"fstwx %0,%2(0,%1)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand:SI 2 "basereg_operand" "r")))
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user