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sse.md (define_mode_suffix vecmemsuffix): New.
gcc/
2019-06-05 Hongtao Liu <hongtao.liu@intel.com>
* config/i386/sse.md (define_mode_suffix vecmemsuffix): New.
(define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"): Enable
memory operand for it.
(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"): Ditto.
gcc/testsuite
2019-06-05 Hongtao Liu <hongtao.liu@intel.com>
* gcc.target/i386/avx512dq-vfpclasspd-1.c: Adjust scan assember
for {x,y,z} suffix.
* gcc.target/i386/avx512dq-vfpclassps-1.c: Ditto.
From-SVN: r271984
This commit is contained in:
Hongtao Liu
Hongtao Liu
parent
269f05ff58
commit
3146ec83db
@ -1,3 +1,10 @@
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2019-06-05 Hongtao Liu <hongtao.liu@intel.com>
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* config/i386/sse.md (define_mode_suffix vecmemsuffix): New.
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(define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"): Enable
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memory operand for it.
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(define_insn "avx512dq_vmfpclass<mode><mask_scalar_merge_name>"): Ditto.
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2019-06-05 Martin Sebor <msebor@redhat.com>
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* config/i386/i386-features.c (ix86_get_function_versions_dispatcher):
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@ -595,6 +595,10 @@
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(define_mode_attr ssequarterinsnmode
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[(V16SF "V4SF") (V8DF "V2DF") (V16SI "TI") (V8DI "TI")])
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(define_mode_attr vecmemsuffix
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[(V16SF "{z}") (V8SF "{y}") (V4SF "{x}")
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(V8DF "{z}") (V4DF "{y}") (V2DF "{x}")])
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(define_mode_attr ssedoublemodelower
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[(V16QI "v16hi") (V32QI "v32hi") (V64QI "v64hi")
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(V8HI "v8si") (V16HI "v16si") (V32HI "v32si")
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@ -21317,11 +21321,11 @@
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(define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
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(unspec:<avx512fmaskmode>
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[(match_operand:VF_AVX512VL 1 "register_operand" "v")
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[(match_operand:VF_AVX512VL 1 "vector_operand" "vm")
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(match_operand:QI 2 "const_0_to_255_operand" "n")]
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UNSPEC_FPCLASS))]
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"TARGET_AVX512DQ"
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"vfpclass<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
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"vfpclass<ssemodesuffix><vecmemsuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
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[(set_attr "type" "sse")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "evex")
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@ -21331,7 +21335,7 @@
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[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
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(and:<avx512fmaskmode>
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(unspec:<avx512fmaskmode>
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[(match_operand:VF_128 1 "register_operand" "v")
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[(match_operand:VF_128 1 "vector_operand" "vm")
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(match_operand:QI 2 "const_0_to_255_operand" "n")]
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UNSPEC_FPCLASS)
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(const_int 1)))]
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@ -1,3 +1,9 @@
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2019-06-05 Hongtao Liu <hongtao.liu@intel.com>
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* gcc.target/i386/avx512dq-vfpclasspd-1.c: Adjust scan assember
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for {x,y,z} suffix.
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* gcc.target/i386/avx512dq-vfpclassps-1.c: Ditto.
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2019-06-05 Martin Sebor <msebor@redhat.com>
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* gcc.dg/format/gcc_diag-11.c: Skip until -Wformat-diag has
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@ -1,11 +1,11 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512dq -mavx512vl -O2" } */
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/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspdz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspdy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspdx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspdz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspdy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspdx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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@ -1,11 +1,11 @@
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/* { dg-do compile } */
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/* { dg-options "-mavx512dq -mavx512vl -O2" } */
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/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclassps\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspsz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspsx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspsz\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspsy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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/* { dg-final { scan-assembler-times "vfpclasspsx\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
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#include <immintrin.h>
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