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mips.c (MIPS_FP_CONDITIONS): New macro.
* config/mips/mips.c (MIPS_FP_CONDITIONS): New macro.
(mips_fp_condition): New enum.
(mips_fp_conditions): New array.
(print_fcc_operand): Delete.
(print_operand): Remove %V, %v and %Q. Redefine %Z so that it prints
the operand and comma if and only if ISA_HAS_8CC. Add %Y.
(builtin_description): Add "cond" field.
(DIRECT_BUILTIN): Initialize it.
(CMP_{SCALAR,PS,4S}_BUILTINS, MOVTF_BUILTINS): Split INSN parameter
into INSN and CODE. Initialize the "cond" field.
(CMP_BUILTINS): Update accordingly.
(mips_bdesc): Use MIPS_FP_CONDITIONS to invoke CMP_BUILTINS.
(mips_expand_builtin_movtf, mips_expand_builtin_compare): Take the
mips_fp_condition as argument. Make it the final operand of the
comparison instruction.
(mips_expand_builtin): Update accordingly.
* config/mips/mips.md (UNSPEC_C_*, UNSPEC_CABS_*): Delete.
(UNSPEC_C, UNSPEC_CABS): New constants. Shuffle others to fill
the gaps.
* config/mips/mips-ps-3d.md (mips_cond_move_tf_ps, bc1any[24][ft]):
Don't use the 'Q' operand prefix; just print the operand normally.
(mips_cabs_*, mips_c_*): Delete, replacing with...
(mips_c_cond_{ps,4s}, mips_cabs_cond_{s,d,ps,4s}): ...these new
patterns. Split the 4s versions into 2 ps patterns after reload.
From-SVN: r86791
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
fa01624514
commit
308cd61171
gcc
@ -1,3 +1,30 @@
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2004-08-30 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (MIPS_FP_CONDITIONS): New macro.
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(mips_fp_condition): New enum.
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(mips_fp_conditions): New array.
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(print_fcc_operand): Delete.
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(print_operand): Remove %V, %v and %Q. Redefine %Z so that it prints
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the operand and comma if and only if ISA_HAS_8CC. Add %Y.
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(builtin_description): Add "cond" field.
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(DIRECT_BUILTIN): Initialize it.
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(CMP_{SCALAR,PS,4S}_BUILTINS, MOVTF_BUILTINS): Split INSN parameter
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into INSN and CODE. Initialize the "cond" field.
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(CMP_BUILTINS): Update accordingly.
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(mips_bdesc): Use MIPS_FP_CONDITIONS to invoke CMP_BUILTINS.
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(mips_expand_builtin_movtf, mips_expand_builtin_compare): Take the
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mips_fp_condition as argument. Make it the final operand of the
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comparison instruction.
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(mips_expand_builtin): Update accordingly.
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* config/mips/mips.md (UNSPEC_C_*, UNSPEC_CABS_*): Delete.
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(UNSPEC_C, UNSPEC_CABS): New constants. Shuffle others to fill
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the gaps.
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* config/mips/mips-ps-3d.md (mips_cond_move_tf_ps, bc1any[24][ft]):
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Don't use the 'Q' operand prefix; just print the operand normally.
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(mips_cabs_*, mips_c_*): Delete, replacing with...
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(mips_c_cond_{ps,4s}, mips_cabs_cond_{s,d,ps,4s}): ...these new
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patterns. Split the 4s versions into 2 ps patterns after reload.
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2004-08-30 Richard Henderson <rth@redhat.com>
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* fold-const.c (tree_expr_nonzero_p): Use get_base_address before
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File diff suppressed because it is too large
Load Diff
@ -188,6 +188,37 @@ enum mips_builtin_type
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MIPS_BUILTIN_CMP_SINGLE
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};
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/* Invokes MACRO (COND) for each c.cond.fmt condition. */
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#define MIPS_FP_CONDITIONS(MACRO) \
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MACRO (f), \
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MACRO (un), \
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MACRO (eq), \
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MACRO (ueq), \
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MACRO (olt), \
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MACRO (ult), \
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MACRO (ole), \
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MACRO (ule), \
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MACRO (sf), \
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MACRO (ngle), \
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MACRO (seq), \
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MACRO (ngl), \
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MACRO (lt), \
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MACRO (nge), \
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MACRO (le), \
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MACRO (ngt)
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/* Enumerates the codes above as MIPS_FP_COND_<X>. */
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#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
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enum mips_fp_condition {
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MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
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};
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/* Index X provides the string representation of MIPS_FP_COND_<X>. */
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#define STRINGIFY(X) #X
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static const char *const mips_fp_conditions[] = {
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MIPS_FP_CONDITIONS (STRINGIFY)
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};
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/* A function to save or store a register. The first argument is the
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register and the second is the stack slot. */
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typedef void (*mips_save_restore_fn) (rtx, rtx);
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@ -325,9 +356,11 @@ static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
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static void mips_init_builtins (void);
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static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree);
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static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
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enum insn_code, rtx, tree);
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enum insn_code, enum mips_fp_condition,
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rtx, tree);
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static rtx mips_expand_builtin_compare (enum mips_builtin_type,
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enum insn_code, rtx, tree);
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enum insn_code, enum mips_fp_condition,
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rtx, tree);
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/* Structure to be filled in by compute_frame_size with register
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save masks, and offsets for the current function. */
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@ -4586,31 +4619,6 @@ mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
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return offset;
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}
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/* A helper function for print_operand. This prints out a floating point
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condition code register. OP is the operand we are printing. CODE is the
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rtx code of OP. ALIGN is the required register alignment for OP. OFFSET
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is the index into operand for multiple register operands. If IGNORE is
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true, then we only print the register name if it isn't fcc0, and we
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follow it with a comma. */
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static void
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print_fcc_operand (FILE *file, rtx op, enum rtx_code code,
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int align, int offset, int ignore)
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{
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int regnum;
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if (code != REG)
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abort ();
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regnum = REGNO (op);
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if (!ST_REG_P (regnum)
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|| (regnum - ST_REG_FIRST) % align != 0)
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abort ();
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if (!ignore || regnum != ST_REG_FIRST)
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fprintf (file, "%s%s", reg_names[regnum+offset], (ignore ? "," : ""));
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}
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/* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
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'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
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@ -4628,13 +4636,9 @@ print_fcc_operand (FILE *file, rtx op, enum rtx_code code,
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'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
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'z' for (eq:?I ...), 'n' for (ne:?I ...).
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't' like 'T', but with the EQ/NE cases reversed
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'Z' print register and a comma, but print nothing for $fcc0
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'Y' for a CONST_INT X, print mips_fp_conditions[X]
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'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
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'R' print the reloc associated with LO_SUM
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'V' Check if the fcc register number divided by 4 is zero. Then print
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the fcc register plus 2.
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'v' Check if the fcc register number divided by 4 is zero. Then print
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the fcc register.
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'Q' print the fcc register.
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The punctuation characters are:
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@ -4866,17 +4870,24 @@ print_operand (FILE *file, rtx op, int letter)
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else if (letter == 'R')
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print_operand_reloc (file, op, mips_lo_relocs);
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else if (letter == 'Y')
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{
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if (GET_CODE (op) == CONST_INT
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&& ((unsigned HOST_WIDE_INT) INTVAL (op)
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< ARRAY_SIZE (mips_fp_conditions)))
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fputs (mips_fp_conditions[INTVAL (op)], file);
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else
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output_operand_lossage ("invalid %%Y value");
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}
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else if (letter == 'Z')
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print_fcc_operand (file, op, code, 1, 0, 1);
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else if (letter == 'V')
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print_fcc_operand (file, op, code, 4, 2, 0);
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else if (letter == 'v')
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print_fcc_operand (file, op, code, 4, 0, 0);
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else if (letter == 'Q')
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print_fcc_operand (file, op, code, 1, 0, 0);
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{
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if (ISA_HAS_8CC)
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{
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print_operand (file, op, 0);
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fputc (',', file);
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}
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}
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else if (code == REG || code == SUBREG)
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{
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@ -9274,6 +9285,9 @@ struct builtin_description
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for more information. */
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enum insn_code icode;
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/* The floating-point comparison code to use with ICODE, if any. */
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enum mips_fp_condition cond;
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/* The name of the builtin function. */
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const char *name;
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@ -9290,60 +9304,69 @@ struct builtin_description
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/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
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FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
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#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN, "__builtin_mips_" #INSN, \
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{ CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
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MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
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/* Define builtins for scalar comparison instructions CODE_FOR_mips_<INSN>_s
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and CODE_FOR_mips_<INSN>_d, both of which require TARGET_FLAGS. */
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#define CMP_SCALAR_BUILTINS(INSN, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN ## _s, "__builtin_mips_" #INSN "_s", \
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/* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
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TARGET_FLAGS. */
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#define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_" #INSN "_" #COND "_s", \
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MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
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{ CODE_FOR_mips_ ## INSN ## _d, "__builtin_mips_" #INSN "_d", \
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{ CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_" #INSN "_" #COND "_d", \
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MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
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/* Define builtins for PS comparison instruction CODE_FOR_mips_<INSN>_ps.
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/* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
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The lower and upper forms require TARGET_FLAGS while the any and all
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forms require MASK_MIPS3D. */
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#define CMP_PS_BUILTINS(INSN, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_any_" #INSN "_ps", \
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#define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_any_" #INSN "_" #COND "_ps", \
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MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
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{ CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_all_" #INSN "_ps", \
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{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_all_" #INSN "_" #COND "_ps", \
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MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
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{ CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_lower_" #INSN "_ps", \
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{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_lower_" #INSN "_" #COND "_ps", \
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MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
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{ CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_upper_" #INSN "_ps", \
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{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_upper_" #INSN "_" #COND "_ps", \
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MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
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/* Define builtins for instruction CODE_FOR_mips_<INSN>_4s, which compares
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two pairs of V2SF vectors. The functions require MASK_MIPS3D. */
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#define CMP_4S_BUILTINS(INSN) \
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{ CODE_FOR_mips_ ## INSN ## _4s, "__builtin_mips_any_" #INSN "_4s", \
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/* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
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require MASK_MIPS3D. */
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#define CMP_4S_BUILTINS(INSN, COND) \
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{ CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_any_" #INSN "_" #COND "_4s", \
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MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
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MASK_MIPS3D }, \
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{ CODE_FOR_mips_ ## INSN ## _4s, "__builtin_mips_all_" #INSN "_4s", \
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{ CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_all_" #INSN "_" #COND "_4s", \
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MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
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MASK_MIPS3D }
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/* Define movt and movf builtins that use CODE_FOR_mips_<INSN>_ps as
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the comparison instruction. The comparison instruction requires
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TARGET_FLAGS. */
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#define MOVTF_BUILTINS(INSN, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_movt_" #INSN "_ps", \
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/* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
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instruction requires TARGET_FLAGS. */
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#define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
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{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_movt_" #INSN "_" #COND "_ps", \
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MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
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TARGET_FLAGS }, \
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{ CODE_FOR_mips_ ## INSN ## _ps, "__builtin_mips_movf_" #INSN "_ps", \
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{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
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"__builtin_mips_movf_" #INSN "_" #COND "_ps", \
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MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
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TARGET_FLAGS }
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/* Define all the builtins related to c.cond.fmt condition COND. */
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#define CMP_BUILTINS(COND) \
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MOVTF_BUILTINS (c_ ## COND, MASK_PAIRED_SINGLE), \
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MOVTF_BUILTINS (cabs_ ## COND, MASK_MIPS3D), \
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CMP_SCALAR_BUILTINS (cabs_ ## COND, MASK_MIPS3D), \
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CMP_PS_BUILTINS (c_ ## COND, MASK_PAIRED_SINGLE), \
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CMP_PS_BUILTINS (cabs_ ## COND, MASK_MIPS3D), \
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CMP_4S_BUILTINS (c_ ## COND), \
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CMP_4S_BUILTINS (cabs_ ## COND)
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MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
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MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
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CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
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CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
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CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
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CMP_4S_BUILTINS (c, COND), \
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CMP_4S_BUILTINS (cabs, COND)
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/* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
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#define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
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@ -9379,22 +9402,7 @@ static const struct builtin_description mips_bdesc[] =
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DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
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DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
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CMP_BUILTINS (f),
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CMP_BUILTINS (un),
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CMP_BUILTINS (eq),
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CMP_BUILTINS (ueq),
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CMP_BUILTINS (olt),
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CMP_BUILTINS (ult),
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CMP_BUILTINS (ole),
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CMP_BUILTINS (ule),
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CMP_BUILTINS (sf),
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CMP_BUILTINS (ngle),
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CMP_BUILTINS (seq),
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CMP_BUILTINS (ngl),
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CMP_BUILTINS (lt),
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CMP_BUILTINS (nge),
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CMP_BUILTINS (le),
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CMP_BUILTINS (ngt)
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MIPS_FP_CONDITIONS (CMP_BUILTINS)
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};
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@ -9460,14 +9468,16 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case MIPS_BUILTIN_MOVT:
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case MIPS_BUILTIN_MOVF:
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return mips_expand_builtin_movtf (type, icode, target, arglist);
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return mips_expand_builtin_movtf (type, icode, mips_bdesc[fcode].cond,
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target, arglist);
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case MIPS_BUILTIN_CMP_ANY:
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case MIPS_BUILTIN_CMP_ALL:
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case MIPS_BUILTIN_CMP_UPPER:
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case MIPS_BUILTIN_CMP_LOWER:
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case MIPS_BUILTIN_CMP_SINGLE:
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return mips_expand_builtin_compare (type, icode, target, arglist);
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return mips_expand_builtin_compare (type, icode, mips_bdesc[fcode].cond,
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target, arglist);
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default:
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return 0;
|
||||
@ -9587,13 +9597,14 @@ mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist)
|
||||
}
|
||||
|
||||
/* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
|
||||
function (TYPE says which). ARGLIST is the list of arguments to
|
||||
the function and ICODE says which instruction should be used to
|
||||
compare the first two arguments. TARGET, if nonnull, suggests a
|
||||
good place to put the result. */
|
||||
function (TYPE says which). ARGLIST is the list of arguments to the
|
||||
function, ICODE is the instruction that should be used to compare
|
||||
the first two arguments, and COND is the conditon it should test.
|
||||
TARGET, if nonnull, suggests a good place to put the result. */
|
||||
|
||||
static rtx
|
||||
mips_expand_builtin_movtf (enum mips_builtin_type type, enum insn_code icode,
|
||||
mips_expand_builtin_movtf (enum mips_builtin_type type,
|
||||
enum insn_code icode, enum mips_fp_condition cond,
|
||||
rtx target, tree arglist)
|
||||
{
|
||||
rtx cmp_result, op0, op1;
|
||||
@ -9601,7 +9612,7 @@ mips_expand_builtin_movtf (enum mips_builtin_type type, enum insn_code icode,
|
||||
cmp_result = mips_prepare_builtin_target (icode, 0, 0);
|
||||
op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
|
||||
op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
|
||||
emit_insn (GEN_FCN (icode) (cmp_result, op0, op1));
|
||||
emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
|
||||
|
||||
icode = CODE_FOR_mips_cond_move_tf_ps;
|
||||
target = mips_prepare_builtin_target (icode, 0, target);
|
||||
@ -9619,13 +9630,15 @@ mips_expand_builtin_movtf (enum mips_builtin_type type, enum insn_code icode,
|
||||
return target;
|
||||
}
|
||||
|
||||
/* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code of
|
||||
the comparison instruction and ARGLIST is the list of function arguments.
|
||||
TARGET, if nonnull, suggests a good place to put the boolean result. */
|
||||
/* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
|
||||
of the comparison instruction and COND is the condition it should test.
|
||||
ARGLIST is the list of function arguments and TARGET, if nonnull,
|
||||
suggests a good place to put the boolean result. */
|
||||
|
||||
static rtx
|
||||
mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
|
||||
enum insn_code icode, rtx target, tree arglist)
|
||||
enum insn_code icode, enum mips_fp_condition cond,
|
||||
rtx target, tree arglist)
|
||||
{
|
||||
rtx label1, label2, if_then_else;
|
||||
rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
|
||||
@ -9637,17 +9650,18 @@ mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
|
||||
|
||||
/* Prepare the operands to the comparison. */
|
||||
cmp_result = mips_prepare_builtin_target (icode, 0, 0);
|
||||
for (i = 1; i < insn_data[icode].n_operands; i++)
|
||||
for (i = 1; i < insn_data[icode].n_operands - 1; i++)
|
||||
ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
|
||||
|
||||
switch (insn_data[icode].n_operands)
|
||||
{
|
||||
case 3:
|
||||
pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2]);
|
||||
case 4:
|
||||
pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
|
||||
break;
|
||||
|
||||
case 5:
|
||||
pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], ops[3], ops[4]);
|
||||
case 6:
|
||||
pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
|
||||
ops[3], ops[4], GEN_INT (cond));
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
@ -53,54 +53,23 @@
|
||||
;; For MIPS Paired-Singled Floating Point Instructions.
|
||||
|
||||
(UNSPEC_MOVE_TF_PS 200)
|
||||
(UNSPEC_C_F 201)
|
||||
(UNSPEC_C_UN 202)
|
||||
(UNSPEC_C_EQ 203)
|
||||
(UNSPEC_C_UEQ 204)
|
||||
(UNSPEC_C_OLT 205)
|
||||
(UNSPEC_C_ULT 206)
|
||||
(UNSPEC_C_OLE 207)
|
||||
(UNSPEC_C_ULE 208)
|
||||
(UNSPEC_C_SF 209)
|
||||
(UNSPEC_C_NGLE 210)
|
||||
(UNSPEC_C_SEQ 211)
|
||||
(UNSPEC_C_NGL 212)
|
||||
(UNSPEC_C_LT 213)
|
||||
(UNSPEC_C_NGE 214)
|
||||
(UNSPEC_C_LE 215)
|
||||
(UNSPEC_C_NGT 216)
|
||||
(UNSPEC_C 201)
|
||||
|
||||
;; MIPS64/MIPS32R2 alnv.ps
|
||||
(UNSPEC_ALNV_PS 217)
|
||||
(UNSPEC_ALNV_PS 202)
|
||||
|
||||
;; MIPS-3D instructions
|
||||
(UNSPEC_CABS 203)
|
||||
|
||||
(UNSPEC_CABS_F 218)
|
||||
(UNSPEC_CABS_UN 219)
|
||||
(UNSPEC_CABS_EQ 220)
|
||||
(UNSPEC_CABS_UEQ 221)
|
||||
(UNSPEC_CABS_OLT 222)
|
||||
(UNSPEC_CABS_ULT 223)
|
||||
(UNSPEC_CABS_OLE 224)
|
||||
(UNSPEC_CABS_ULE 225)
|
||||
(UNSPEC_CABS_SF 226)
|
||||
(UNSPEC_CABS_NGLE 227)
|
||||
(UNSPEC_CABS_SEQ 228)
|
||||
(UNSPEC_CABS_NGL 229)
|
||||
(UNSPEC_CABS_LT 230)
|
||||
(UNSPEC_CABS_NGE 231)
|
||||
(UNSPEC_CABS_LE 232)
|
||||
(UNSPEC_CABS_NGT 233)
|
||||
(UNSPEC_ADDR_PS 204)
|
||||
(UNSPEC_CVT_PW_PS 205)
|
||||
(UNSPEC_CVT_PS_PW 206)
|
||||
(UNSPEC_MULR_PS 207)
|
||||
|
||||
(UNSPEC_ADDR_PS 234)
|
||||
(UNSPEC_CVT_PW_PS 235)
|
||||
(UNSPEC_CVT_PS_PW 236)
|
||||
(UNSPEC_MULR_PS 237)
|
||||
|
||||
(UNSPEC_RSQRT1 238)
|
||||
(UNSPEC_RSQRT2 239)
|
||||
(UNSPEC_RECIP1 240)
|
||||
(UNSPEC_RECIP2 241)
|
||||
(UNSPEC_RSQRT1 208)
|
||||
(UNSPEC_RSQRT2 209)
|
||||
(UNSPEC_RECIP1 210)
|
||||
(UNSPEC_RECIP2 211)
|
||||
]
|
||||
)
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user