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Remove Cell Broadband Engine SPU targets

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From-SVN: r275343
This commit is contained in:
Ulrich Weigand 2019-09-03 15:08:28 +00:00 committed by Ulrich Weigand
parent 9343921853
commit 2f2aeda98f
273 changed files with 299 additions and 34017 deletions
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4
ChangeLog
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@ -1,3 +1,7 @@
2019-09-03 Ulrich Weigand <uweigand@de.ibm.com>
* MAINTAINERS: Remove spu port maintainers.
2019-08-28 Martin Liska <mliska@suse.cz>
* .gitignore: Add .clangd and compile_commands.json

3
MAINTAINERS
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@ -109,9 +109,6 @@ sh port Alexandre Oliva <aoliva@gcc.gnu.org>
sh port Oleg Endo <olegendo@gcc.gnu.org>
sparc port David S. Miller <davem@redhat.com>
sparc port Eric Botcazou <ebotcazou@libertysurf.fr>
spu port Trevor Smigiel <trevor_smigiel@playstation.sony.com>
spu port David Edelsohn <dje.gcc@gmail.com>
spu port Ulrich Weigand <uweigand@de.ibm.com>
tilegx port Walter Lee <walt@tilera.com>
tilepro port Walter Lee <walt@tilera.com>
v850 port Nick Clifton <nickc@redhat.com>

5
contrib/ChangeLog
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@ -1,3 +1,8 @@
2019-09-03 Ulrich Weigand <uweigand@de.ibm.com>
* compare-all-tests (all_targets): Remove references to spu.
* config-list.mk (LIST): Likewise.
2019-09-02 Alexander Monakov <amonakov@ispras.ru>
* vim-gcc-dev/syntax/gcc-match.vim: Do not override 'tabstop' here.

2
contrib/compare-all-tests
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@ -34,7 +34,7 @@ s390_opts='-m31 -m31/-mzarch -m64'
sh_opts='-m3 -m3e -m4 -m4a -m4al -m4/-mieee -m1 -m1/-mno-cbranchdi -m2a -m2a/-mieee -m2e -m2e/-mieee'
sparc_opts='-mcpu=v8/-m32 -mcpu=v9/-m32 -m64'
all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sparc spu v850 vax xstormy16 xtensa' # e500
all_targets='alpha arm avr bfin cris fr30 frv h8300 ia64 iq2000 m32c m32r m68k mcore mips mmix mn10300 pa pdp11 ppc sh sparc v850 vax xstormy16 xtensa' # e500
test_one_file ()
{

2
contrib/config-list.mk
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@ -90,7 +90,7 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \
sparc-leon3-linux-gnuOPT-enable-target=all sparc-netbsdelf \
sparc64-sun-solaris2.11OPT-with-gnu-ldOPT-with-gnu-asOPT-enable-threads=posix \
sparc-wrs-vxworks sparc64-elf sparc64-rtems sparc64-linux sparc64-freebsd6 \
sparc64-netbsd sparc64-openbsd spu-elf \
sparc64-netbsd sparc64-openbsd \
tilegx-linux-gnu tilegxbe-linux-gnu tilepro-linux-gnu \
v850e-elf v850-elf v850-rtems vax-linux-gnu \
vax-netbsdelf vax-openbsd visium-elf x86_64-apple-darwin \

5
contrib/header-tools/ChangeLog
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@ -1,3 +1,8 @@
2019-09-03 Ulrich Weigand <uweigand@de.ibm.com>
* README: Remove references to spu.
* reduce-headers: Likewise.
2017-07-02 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>

2
contrib/header-tools/README
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@ -203,7 +203,7 @@ reduce-headers
these targets. They are also known to the tool. When building targets it
will check those targets before the rest.
This coverage can be achieved by building config-list.mk with :
LIST="aarch64-linux-gnu arm-netbsdelf c6x-elf epiphany-elf hppa2.0-hpux10.1 i686-mingw32crt i686-pc-msdosdjgpp mipsel-elf powerpc-eabisimaltivec rs6000-ibm-aix5.1.0 sh-superh-elf sparc64-elf spu-elf"
LIST="aarch64-linux-gnu arm-netbsdelf c6x-elf epiphany-elf hppa2.0-hpux10.1 i686-mingw32crt i686-pc-msdosdjgpp mipsel-elf powerpc-eabisimaltivec rs6000-ibm-aix5.1.0 sh-superh-elf sparc64-elf"
-b specifies the native bootstrapped build root directory
-t specifies a target build root directory that config-list.mk was run from

3
contrib/header-tools/reduce-headers
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@ -32,8 +32,7 @@ target_priority = [
"powerpc-eabisimaltivec",
"rs6000-ibm-aix5.1.0",
"sh-superh-elf",
"sparc64-elf",
"spu-elf"
"sparc64-elf"
]

13
gcc/ChangeLog
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@ -1,3 +1,16 @@
2019-09-03 Ulrich Weigand <uweigand@de.ibm.com>
* config.gcc: Obsolete spu target. Remove references to spu.
* configure.ac: Remove references to spu.
* configure: Regenerate.
* config/spu/: Remove directory.
* common/config/spu/: Remove directory.
* doc/extend.texi: Remove references to spu.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* doc/sourcebuild.texi: Likewise.
2019-09-03 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR middle-end/91603

56
gcc/common/config/spu/spu-common.c
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@ -1,56 +0,0 @@
/* Common hooks for SPU.
Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
#include "params.h"
static void
spu_option_init_struct (struct gcc_options *opts)
{
/* With so many registers this is better on by default. */
opts->x_flag_rename_registers = 1;
}
/* Implement TARGET_OPTION_DEFAULT_PARAMS. */
static void
spu_option_default_params (void)
{
/* Override some of the default param values. With so many registers
larger values are better for these params. */
set_default_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 128);
}
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
#undef TARGET_OPTION_INIT_STRUCT
#define TARGET_OPTION_INIT_STRUCT spu_option_init_struct
#undef TARGET_OPTION_DEFAULT_PARAMS
#define TARGET_OPTION_DEFAULT_PARAMS spu_option_default_params
#undef TARGET_EXCEPT_UNWIND_INFO
#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;

33
gcc/config.gcc
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@ -247,8 +247,7 @@ md_file=
# Obsolete configurations.
case ${target} in
spu*-*-* \
| tile*-*-* \
tile*-*-* \
)
if test "x$enable_obsolete" != xyes; then
echo "*** Configuration ${target} is obsolete." >&2
@ -280,6 +279,7 @@ case ${target} in
| powerpc*-*-linux*paired* \
| powerpc*-*-*spe* \
| sparc-hal-solaris2* \
| spu*-*-* \
| thumb-*-* \
| *-*-freebsd[12] | *-*-freebsd[1234].* \
| *-*-freebsd*aout* \
@ -535,9 +535,6 @@ sparc*-*-*)
d_target_objs="sparc-d.o"
extra_headers="visintrin.h"
;;
spu*-*-*)
cpu_type=spu
;;
s390*-*-*)
cpu_type=s390
d_target_objs="s390-d.o"
@ -3171,15 +3168,6 @@ sparc64-*-openbsd*)
with_cpu=ultrasparc
tmake_file="${tmake_file} sparc/t-sparc"
;;
spu-*-elf*)
tm_file="dbxelf.h elfos.h spu/spu-elf.h spu/spu.h newlib-stdint.h"
tmake_file="spu/t-spu-elf"
native_system_header_dir=/include
extra_headers="spu_intrinsics.h spu_internals.h vmx2spu.h spu_mfcio.h vec_types.h spu_cache.h"
extra_modes=spu/spu-modes.def
c_target_objs="${c_target_objs} spu-c.o"
cxx_target_objs="${cxx_target_objs} spu-c.o"
;;
tic6x-*-elf)
tm_file="elfos.h ${tm_file} c6x/elf-common.h c6x/elf.h"
tm_file="${tm_file} dbxelf.h tm-dwarf2.h newlib-stdint.h"
@ -4890,23 +4878,6 @@ case "${target}" in
esac
;;
spu-*-*)
supported_defaults="arch tune"
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
"" | cell | celledp)
# OK
;;
*)
echo "Unknown cpu used in --with-$which=$val." 1>&2
exit 1
;;
esac
done
;;
tic6x-*-*)
supported_defaults="arch"

179
gcc/config/spu/constraints.md
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@ -1,179 +0,0 @@
;; Constraint definitions for SPU
;; Copyright (C) 2006-2019 Free Software Foundation, Inc.
;;
;; This file is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 3 of the License, or (at your option)
;; any later version.
;; This file is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz
;; GCC: ffffiiiiiiii x x x x xxxx xx
;; SPU: xxxx xxx xxxx xxxx x xxx xx x xxx xx
;; FREE: ffff i a a a a a aa aaa
;; x - used
;; a - available
;; i - available for integer immediates
;; f - available for floating point immediates
;; For most immediate constraints we have 3 variations to deal with the
;; fact const_int has no mode. One variation treats const_int as 32 bit,
;; another treats it as 64 bit, and the third sign extends it to 128 bit.
(define_constraint "A"
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32-bit value."
(ior (and (match_code "const_int,const_double,const_vector")
(match_test "immediate_load_p (op, SImode)"))
(match_code "symbol_ref,label_ref,high,const")))
(define_constraint "B"
"An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32-bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "arith_immediate_p (op, SImode, -0x200, 0x1ff)")))
(define_constraint "C"
"An immediate for and/xor/or instructions. const_int is treated as a 32-bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "logical_immediate_p (op, SImode)")))
(define_constraint "D"
"An immediate for iohl instruction. const_int is treated as a 32-bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "iohl_immediate_p (op, SImode)")))
(define_constraint "U"
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit."
(and (match_code "const_int,const_double,const_vector")
(match_test "immediate_load_p (op, TImode)")))
(define_constraint "W"
"An immediate for shift and rotate instructions. const_int is treated as a 32-bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "arith_immediate_p (op, SImode, -0x80000000ll, 0x7fffffffll)")))
(define_constraint "Y"
"An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit."
(and (match_code "const_int,const_double,const_vector")
(match_test "logical_immediate_p (op, TImode)")))
(define_constraint "Z"
"An immediate for iohl instruction. const_int is sign extended to 128 bit."
(and (match_code "const_int,const_double,const_vector")
(match_test "iohl_immediate_p (op, TImode)")))
(define_constraint "a"
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64-bit value."
(and (match_code "const_int")
(match_test "immediate_load_p (op, DImode)")))
(define_constraint "c"
"An immediate for and/xor/or instructions. const_int is treated as a 64-bit value."
(and (match_code "const_int")
(match_test "logical_immediate_p (op, DImode)")))
(define_constraint "d"
"An immediate for iohl instruction. const_int is treated as a 64-bit value."
(and (match_code "const_int")
(match_test "iohl_immediate_p (op, DImode)")))
(define_constraint "f"
"An immediate which can be loaded with fsmbi."
(and (match_code "const_int,const_double,const_vector")
(match_test "fsmbi_const_p (op)")))
(define_constraint "j"
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 32-bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "cpat_const_p (op, SImode)")))
(define_constraint "k"
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 64-bit value."
(and (match_code "const_int,const_double,const_vector")
(match_test "cpat_const_p (op, DImode)")))
(define_constraint "l"
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions."
(and (match_code "const_double,const_vector")
(match_test "cpat_const_p (op, TImode)")))
;; Integer constraints
(define_constraint "I"
"A constant in the range [-64, 63] for shift/rotate instructions."
(and (match_code "const_int")
(match_test "ival >= -0x40 && ival <= 0x3f")))
(define_constraint "J"
"An unsigned 7-bit constant for conversion/nop/channel instructions."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 0x7f")))
(define_constraint "K"
"A signed 10-bit constant for most arithmetic instructions."
(and (match_code "const_int")
(match_test "ival >= -0x200 && ival <= 0x1ff")))
(define_constraint "M"
"A signed 16-bit immediate for @code{stop}."
(and (match_code "const_int")
(match_test "ival >= -0x8000ll && ival <= 0x7fffll")))
(define_constraint "N"
"An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}."
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 0xffff")))
(define_constraint "O"
"An unsigned 7-bit constant whose 3 least significant bits are 0."
(and (match_code "const_int")
(match_test "(ival & 7) == 0")))
(define_constraint "P"
"An unsigned 3-bit constant for 16-byte rotates and shifts"
(and (match_code "const_int")
(match_test "ival >= 0 && ival <= 7")))
;; Memory constraints
(define_memory_constraint "R"
"Call operand, reg, for indirect calls"
(and (match_code "mem")
(match_test "GET_CODE(XEXP(op, 0)) == REG")))
(define_memory_constraint "S"
"Call operand, symbol, for relative calls."
(and (match_code "mem")
(match_test "!TARGET_LARGE_MEM
&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF))")))
(define_memory_constraint "T"
"Call operand, const_int, for absolute calls."
(and (match_code "mem")
(match_test "GET_CODE (XEXP (op, 0)) == CONST_INT
&& INTVAL (XEXP (op, 0)) >= 0
&& INTVAL (XEXP (op, 0)) <= 0x3ffff")))
;; Floating-point constant constraints.
(define_constraint "v"
"Floating point power of 2 with exponent in [0..127]"
(and (match_code "const_double,const_vector")
(match_test "exp2_immediate_p (op, VOIDmode, 0, 127)")))
(define_constraint "w"
"Floating point power of 2 with exponent in [-126..0]"
(and (match_code "const_double,const_vector")
(match_test "exp2_immediate_p (op, VOIDmode, -126, 0)")))

122
gcc/config/spu/predicates.md
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@ -1,122 +0,0 @@
;; Predicate definitions for CELL SPU
;; Copyright (C) 2006-2019 Free Software Foundation, Inc.
;;
;; This file is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 3 of the License, or (at your option)
;; any later version.
;; This file is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Return 1 if operand is constant zero of its mode
(define_predicate "const_zero_operand"
(and (match_code "const_int,const,const_double,const_vector")
(match_test "op == CONST0_RTX (mode)")))
(define_predicate "const_one_operand"
(and (match_code "const_int,const,const_double,const_vector")
(match_test "op == CONST1_RTX (mode)")))
(define_predicate "spu_reg_operand"
(and (match_operand 0 "register_operand")
(ior (not (match_code "subreg"))
(match_test "valid_subreg (op)"))))
(define_predicate "spu_nonimm_operand"
(and (match_operand 0 "nonimmediate_operand")
(ior (not (match_code "subreg"))
(match_test "valid_subreg (op)"))))
(define_predicate "spu_nonmem_operand"
(and (match_operand 0 "nonmemory_operand")
(ior (not (match_code "subreg"))
(match_test "valid_subreg (op)"))))
(define_predicate "spu_mov_operand"
(ior (match_operand 0 "memory_operand")
(match_operand 0 "spu_nonmem_operand")))
(define_predicate "spu_dest_operand"
(ior (match_operand 0 "memory_operand")
(match_operand 0 "spu_reg_operand")))
(define_predicate "call_operand"
(and (match_code "mem")
(match_test "(!TARGET_LARGE_MEM && satisfies_constraint_S (op))
|| (satisfies_constraint_R (op)
&& REGNO (XEXP (op, 0)) != FRAME_POINTER_REGNUM
&& REGNO (XEXP (op, 0)) != ARG_POINTER_REGNUM
&& (REGNO (XEXP (op, 0)) < FIRST_PSEUDO_REGISTER
|| REGNO (XEXP (op, 0)) > LAST_VIRTUAL_REGISTER))")))
(define_predicate "vec_imm_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "spu_legitimate_constant_p (mode, op)")))
(define_predicate "spu_arith_operand"
(match_code "reg,subreg,const_int,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
return arith_immediate_p (op, mode, -0x200, 0x1ff);
return 0;
})
(define_predicate "spu_logical_operand"
(match_code "reg,subreg,const_int,const_double,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode);
return 0;
})
(define_predicate "spu_ior_operand"
(match_code "reg,subreg,const_int,const_double,const_vector")
{
if (spu_reg_operand (op, mode))
return 1;
if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode)
|| iohl_immediate_p (op, mode);
return 0;
})
(define_predicate "imm_K_operand"
(and (match_code "const_int")
(match_test "arith_immediate_p (op, mode, -0x200, 0x1ff)")))
;; Return 1 if OP is a comparison operation that is valid for a branch insn.
;; We only check the opcode against the mode of the register value here.
(define_predicate "branch_comparison_operator"
(and (match_code "eq,ne")
(ior (match_test "GET_MODE (XEXP (op, 0)) == HImode")
(match_test "GET_MODE (XEXP (op, 0)) == SImode"))))
(define_predicate "spu_inv_exp2_operand"
(and (match_code "const_double,const_vector")
(and (match_operand 0 "immediate_operand")
(match_test "exp2_immediate_p (op, mode, -126, 0)"))))
(define_predicate "spu_exp2_operand"
(and (match_code "const_double,const_vector")
(and (match_operand 0 "immediate_operand")
(match_test "exp2_immediate_p (op, mode, 0, 127)"))))
(define_predicate "shiftrt_operator"
(match_code "lshiftrt,ashiftrt"))
(define_predicate "extend_operator"
(match_code "sign_extend,zero_extend"))

781
gcc/config/spu/spu-builtins.def
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@ -1,781 +0,0 @@
/* Definitions of builtin functions for the Synergistic Processing Unit (SPU). */
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The first argument to these macros is the return type of the builtin,
* the rest are arguments of the builtin. */
#define _A1(a) {a, SPU_BTI_END_OF_PARAMS}
#define _A2(a,b) {a, b, SPU_BTI_END_OF_PARAMS}
#define _A3(a,b,c) {a, b, c, SPU_BTI_END_OF_PARAMS}
#define _A4(a,b,c,d) {a, b, c, d, SPU_BTI_END_OF_PARAMS}
/* definitions to support si intrinsic functions: (These and other builtin
* definitions must precede definitions of the overloaded generic intrinsics */
DEF_BUILTIN (SI_LQD, CODE_FOR_spu_lqd, "si_lqd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10_4))
DEF_BUILTIN (SI_LQX, CODE_FOR_spu_lqx, "si_lqx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_LQA, CODE_FOR_spu_lqa, "si_lqa", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U16_2))
DEF_BUILTIN (SI_LQR, CODE_FOR_spu_lqr, "si_lqr", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_S16_2))
DEF_BUILTIN (SI_STQD, CODE_FOR_spu_stqd, "si_stqd", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10_4))
DEF_BUILTIN (SI_STQX, CODE_FOR_spu_stqx, "si_stqx", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_STQA, CODE_FOR_spu_stqa, "si_stqa", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_U16_2))
DEF_BUILTIN (SI_STQR, CODE_FOR_spu_stqr, "si_stqr", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S16_2))
DEF_BUILTIN (SI_CBD, CODE_FOR_spu_cbx, "si_cbd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
DEF_BUILTIN (SI_CBX, CODE_FOR_spu_cbx, "si_cbx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CHD, CODE_FOR_spu_chx, "si_chd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
DEF_BUILTIN (SI_CHX, CODE_FOR_spu_chx, "si_chx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CWD, CODE_FOR_spu_cwx, "si_cwd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
DEF_BUILTIN (SI_CWX, CODE_FOR_spu_cwx, "si_cwx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CDD, CODE_FOR_spu_cdx, "si_cdd", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S7))
DEF_BUILTIN (SI_CDX, CODE_FOR_spu_cdx, "si_cdx", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ILH, CODE_FOR_movv8hi, "si_ilh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_16))
DEF_BUILTIN (SI_ILHU, CODE_FOR_spu_ilhu, "si_ilhu", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_16))
DEF_BUILTIN (SI_IL, CODE_FOR_movv4si, "si_il", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_S16))
DEF_BUILTIN (SI_ILA, CODE_FOR_movv4si, "si_ila", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U18))
DEF_BUILTIN (SI_IOHL, CODE_FOR_iorv4si3, "si_iohl", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U16))
DEF_BUILTIN (SI_FSMBI, CODE_FOR_spu_fsmb, "si_fsmbi", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_16))
DEF_BUILTIN (SI_AH, CODE_FOR_addv8hi3, "si_ah", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_AHI, CODE_FOR_addv8hi3, "si_ahi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_A, CODE_FOR_addv4si3, "si_a", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_AI, CODE_FOR_addv4si3, "si_ai", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_ADDX, CODE_FOR_addx_v4si, "si_addx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CG, CODE_FOR_cg_v4si, "si_cg", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CGX, CODE_FOR_cgx_v4si, "si_cgx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SFH, CODE_FOR_spu_sfh, "si_sfh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SFHI, CODE_FOR_spu_sfh, "si_sfhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_SF, CODE_FOR_spu_sf, "si_sf", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SFI, CODE_FOR_spu_sf, "si_sfi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_SFX, CODE_FOR_spu_sfx, "si_sfx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_BG, CODE_FOR_spu_bg, "si_bg", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_BGX, CODE_FOR_spu_bgx, "si_bgx", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPY, CODE_FOR_vec_widen_smult_odd_v8hi, "si_mpy", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYU, CODE_FOR_vec_widen_umult_odd_v8hi, "si_mpyu", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYI, CODE_FOR_vec_widen_smult_odd_v8hi, "si_mpyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_MPYUI, CODE_FOR_vec_widen_umult_odd_v8hi, "si_mpyui", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_MPYA, CODE_FOR_spu_mpya, "si_mpya", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYH, CODE_FOR_spu_mpyh, "si_mpyh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYS, CODE_FOR_spu_mpys, "si_mpys", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYHH, CODE_FOR_vec_widen_smult_even_v8hi, "si_mpyhh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYHHU, CODE_FOR_vec_widen_umult_even_v8hi, "si_mpyhhu", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYHHA, CODE_FOR_spu_mpyhha, "si_mpyhha", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_MPYHHAU, CODE_FOR_spu_mpyhhau, "si_mpyhhau", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CLZ, CODE_FOR_clzv4si2, "si_clz", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CNTB, CODE_FOR_cntb_v16qi, "si_cntb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FSMB, CODE_FOR_spu_fsmb, "si_fsmb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FSMH, CODE_FOR_spu_fsmh, "si_fsmh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FSM, CODE_FOR_spu_fsm, "si_fsm", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_GBB, CODE_FOR_spu_gbb, "si_gbb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_GBH, CODE_FOR_spu_gbh, "si_gbh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_GB, CODE_FOR_spu_gb, "si_gb", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_AVGB, CODE_FOR_spu_avgb, "si_avgb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ABSDB, CODE_FOR_spu_absdb, "si_absdb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SUMB, CODE_FOR_spu_sumb, "si_sumb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_XSBH, CODE_FOR_spu_xsbh, "si_xsbh", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_XSHW, CODE_FOR_spu_xshw, "si_xshw", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_XSWD, CODE_FOR_spu_xswd, "si_xswd", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_AND, CODE_FOR_andv16qi3, "si_and", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ANDC, CODE_FOR_andc_v16qi, "si_andc", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ANDBI, CODE_FOR_andv16qi3, "si_andbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_ANDHI, CODE_FOR_andv8hi3, "si_andhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_ANDI, CODE_FOR_andv4si3, "si_andi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_OR, CODE_FOR_iorv16qi3, "si_or", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ORC, CODE_FOR_orc_v16qi, "si_orc", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ORBI, CODE_FOR_iorv16qi3, "si_orbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_ORHI, CODE_FOR_iorv8hi3, "si_orhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_ORI, CODE_FOR_iorv4si3, "si_ori", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_ORX, CODE_FOR_spu_orx, "si_orx", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_XOR, CODE_FOR_xorv16qi3, "si_xor", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_XORBI, CODE_FOR_xorv16qi3, "si_xorbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_XORHI, CODE_FOR_xorv8hi3, "si_xorhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_XORI, CODE_FOR_xorv4si3, "si_xori", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_NAND, CODE_FOR_nand_v16qi, "si_nand", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_NOR, CODE_FOR_nor_v16qi, "si_nor", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_EQV, CODE_FOR_eqv_v16qi, "si_eqv", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SELB, CODE_FOR_selb, "si_selb", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHUFB, CODE_FOR_shufb, "si_shufb", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLH, CODE_FOR_vashlv8hi3, "si_shlh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLHI, CODE_FOR_vashlv8hi3, "si_shlhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHL, CODE_FOR_vashlv4si3, "si_shl", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLI, CODE_FOR_vashlv4si3, "si_shli", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHLQBI, CODE_FOR_shlqbi_ti, "si_shlqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLQBII, CODE_FOR_shlqbi_ti, "si_shlqbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHLQBY, CODE_FOR_shlqby_ti, "si_shlqby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_SHLQBYI, CODE_FOR_shlqby_ti, "si_shlqbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_SHLQBYBI, CODE_FOR_shlqbybi_ti, "si_shlqbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTH, CODE_FOR_vrotlv8hi3, "si_roth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTHI, CODE_FOR_vrotlv8hi3, "si_rothi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROT, CODE_FOR_vrotlv4si3, "si_rot", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTI, CODE_FOR_vrotlv4si3, "si_roti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQBY, CODE_FOR_rotqby_ti, "si_rotqby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTQBYI, CODE_FOR_rotqby_ti, "si_rotqbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQBYBI, CODE_FOR_rotqbybi_ti, "si_rotqbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTQBI, CODE_FOR_rotqbi_ti, "si_rotqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTQBII, CODE_FOR_rotqbi_ti, "si_rotqbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTHM, CODE_FOR_rotm_v8hi, "si_rothm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTHMI, CODE_FOR_rotm_v8hi, "si_rothmi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTM, CODE_FOR_rotm_v4si, "si_rotm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTMI, CODE_FOR_rotm_v4si, "si_rotmi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQMBY, CODE_FOR_rotqmby_ti, "si_rotqmby", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTQMBYI, CODE_FOR_rotqmby_ti, "si_rotqmbyi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQMBI, CODE_FOR_rotqmbi_ti, "si_rotqmbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTQMBII, CODE_FOR_rotqmbi_ti, "si_rotqmbii", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTQMBYBI, CODE_FOR_rotqmbybi_ti, "si_rotqmbybi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTMAH, CODE_FOR_rotma_v8hi, "si_rotmah", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTMAHI, CODE_FOR_rotma_v8hi, "si_rotmahi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_ROTMA, CODE_FOR_rotma_v4si, "si_rotma", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_ROTMAI, CODE_FOR_rotma_v4si, "si_rotmai", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_7))
DEF_BUILTIN (SI_HEQ, CODE_FOR_spu_heq, "si_heq", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_HEQI, CODE_FOR_spu_heq, "si_heqi", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_HGT, CODE_FOR_spu_hgt, "si_hgt", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_HGTI, CODE_FOR_spu_hgt, "si_hgti", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_HLGT, CODE_FOR_spu_hlgt, "si_hlgt", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_HLGTI, CODE_FOR_spu_hlgt, "si_hlgti", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CEQB, CODE_FOR_ceq_v16qi, "si_ceqb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CEQBI, CODE_FOR_ceq_v16qi, "si_ceqbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CEQH, CODE_FOR_ceq_v8hi, "si_ceqh", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CEQHI, CODE_FOR_ceq_v8hi, "si_ceqhi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CEQ, CODE_FOR_ceq_v4si, "si_ceq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CEQI, CODE_FOR_ceq_v4si, "si_ceqi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CGTB, CODE_FOR_cgt_v16qi, "si_cgtb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CGTBI, CODE_FOR_cgt_v16qi, "si_cgtbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CGTH, CODE_FOR_cgt_v8hi, "si_cgth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CGTHI, CODE_FOR_cgt_v8hi, "si_cgthi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CGT, CODE_FOR_cgt_v4si, "si_cgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CGTI, CODE_FOR_cgt_v4si, "si_cgti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CLGTB, CODE_FOR_clgt_v16qi, "si_clgtb", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CLGTBI, CODE_FOR_clgt_v16qi, "si_clgtbi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CLGTH, CODE_FOR_clgt_v8hi, "si_clgth", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CLGTHI, CODE_FOR_clgt_v8hi, "si_clgthi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_CLGT, CODE_FOR_clgt_v4si, "si_clgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CLGTI, CODE_FOR_clgt_v4si, "si_clgti", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_S10))
DEF_BUILTIN (SI_BISLED, CODE_FOR_spu_bisled, "si_bisled", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_PTR))
DEF_BUILTIN (SI_BISLEDD, CODE_FOR_spu_bisledd, "si_bisledd", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_PTR))
DEF_BUILTIN (SI_BISLEDE, CODE_FOR_spu_bislede, "si_bislede", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_PTR))
DEF_BUILTIN (SI_FA, CODE_FOR_addv4sf3, "si_fa", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFA, CODE_FOR_addv2df3, "si_dfa", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FS, CODE_FOR_subv4sf3, "si_fs", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFS, CODE_FOR_subv2df3, "si_dfs", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FM, CODE_FOR_mulv4sf3, "si_fm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFM, CODE_FOR_mulv2df3, "si_dfm", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FMA, CODE_FOR_fmav4sf4, "si_fma", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFMA, CODE_FOR_fmav2df4, "si_dfma", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFNMA, CODE_FOR_nfmav2df4, "si_dfnma", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FNMS, CODE_FOR_fnmav4sf4, "si_fnms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFNMS, CODE_FOR_nfmsv2df4, "si_dfnms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FMS, CODE_FOR_fmsv4sf4, "si_fms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFMS, CODE_FOR_fmsv2df4, "si_dfms", B_INSN, _A4(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FREST, CODE_FOR_frest_v4sf, "si_frest", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FRSQEST, CODE_FOR_frsqest_v4sf, "si_frsqest", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FI, CODE_FOR_fi_v4sf, "si_fi", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_CSFLT, CODE_FOR_spu_csflt, "si_csflt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_CFLTS, CODE_FOR_spu_cflts, "si_cflts", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_CUFLT, CODE_FOR_spu_cuflt, "si_cuflt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_CFLTU, CODE_FOR_spu_cfltu, "si_cfltu", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_FRDS, CODE_FOR_spu_frds, "si_frds", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FESD, CODE_FOR_spu_fesd, "si_fesd", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FCEQ, CODE_FOR_ceq_v4sf, "si_fceq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFCEQ, CODE_FOR_ceq_v2df, "si_dfceq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FCMEQ, CODE_FOR_cmeq_v4sf, "si_fcmeq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFCMEQ, CODE_FOR_cmeq_v2df, "si_dfcmeq", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FCGT, CODE_FOR_cgt_v4sf, "si_fcgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFCGT, CODE_FOR_cgt_v2df, "si_dfcgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FCMGT, CODE_FOR_cmgt_v4sf, "si_fcmgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFCMGT, CODE_FOR_cmgt_v2df, "si_dfcmgt", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_DFTSV, CODE_FOR_dftsv, "si_dftsv", B_INSN, _A3(SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_STOP, CODE_FOR_spu_stop, "si_stop", B_INSN, _A2(SPU_BTI_VOID, SPU_BTI_U14))
DEF_BUILTIN (SI_STOPD, CODE_FOR_spu_stopd, "si_stopd", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_LNOP, CODE_FOR_lnop, "si_lnop", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SI_NOP, CODE_FOR_nop, "si_nop", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SI_SYNC, CODE_FOR_sync, "si_sync", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SI_SYNCC, CODE_FOR_syncc, "si_syncc", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SI_DSYNC, CODE_FOR_dsync, "si_dsync", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SI_MFSPR, CODE_FOR_spu_mfspr, "si_mfspr", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_MTSPR, CODE_FOR_spu_mtspr, "si_mtspr", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_U7, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FSCRRD, CODE_FOR_spu_fscrrd, "si_fscrrd", B_INSN, _A1(SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FSCRWR, CODE_FOR_spu_fscrwr, "si_fscrwr", B_INSN, _A2(SPU_BTI_VOID, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_RDCH, CODE_FOR_spu_rdch, "si_rdch", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_RCHCNT, CODE_FOR_spu_rchcnt, "si_rchcnt", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_U7))
DEF_BUILTIN (SI_WRCH, CODE_FOR_spu_wrch, "si_wrch", B_INSN, _A3(SPU_BTI_VOID, SPU_BTI_U7, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_CHAR, CODE_FOR_spu_convert, "si_to_char", B_INSN, _A2(SPU_BTI_INTQI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_UCHAR, CODE_FOR_spu_convert, "si_to_uchar", B_INSN, _A2(SPU_BTI_UINTQI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_SHORT, CODE_FOR_spu_convert, "si_to_short", B_INSN, _A2(SPU_BTI_INTHI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_USHORT, CODE_FOR_spu_convert, "si_to_ushort", B_INSN, _A2(SPU_BTI_UINTHI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_INT, CODE_FOR_spu_convert, "si_to_int", B_INSN, _A2(SPU_BTI_INTSI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_UINT, CODE_FOR_spu_convert, "si_to_uint", B_INSN, _A2(SPU_BTI_UINTSI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_LONG, CODE_FOR_spu_convert, "si_to_long", B_INSN, _A2(SPU_BTI_INTDI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_ULONG, CODE_FOR_spu_convert, "si_to_ulong", B_INSN, _A2(SPU_BTI_UINTDI, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_FLOAT, CODE_FOR_spu_convert, "si_to_float", B_INSN, _A2(SPU_BTI_FLOAT, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_DOUBLE, CODE_FOR_spu_convert, "si_to_double", B_INSN, _A2(SPU_BTI_DOUBLE, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_TO_PTR, CODE_FOR_spu_convert, "si_to_ptr", B_INSN, _A2(SPU_BTI_PTR, SPU_BTI_QUADWORD))
DEF_BUILTIN (SI_FROM_CHAR, CODE_FOR_spu_convert, "si_from_char", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTQI))
DEF_BUILTIN (SI_FROM_UCHAR, CODE_FOR_spu_convert, "si_from_uchar", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTQI))
DEF_BUILTIN (SI_FROM_SHORT, CODE_FOR_spu_convert, "si_from_short", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTHI))
DEF_BUILTIN (SI_FROM_USHORT, CODE_FOR_spu_convert, "si_from_ushort", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTHI))
DEF_BUILTIN (SI_FROM_INT, CODE_FOR_spu_convert, "si_from_int", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTSI))
DEF_BUILTIN (SI_FROM_UINT, CODE_FOR_spu_convert, "si_from_uint", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTSI))
DEF_BUILTIN (SI_FROM_LONG, CODE_FOR_spu_convert, "si_from_long", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_INTDI))
DEF_BUILTIN (SI_FROM_ULONG, CODE_FOR_spu_convert, "si_from_ulong", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_UINTDI))
DEF_BUILTIN (SI_FROM_FLOAT, CODE_FOR_spu_convert, "si_from_float", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_FLOAT))
DEF_BUILTIN (SI_FROM_DOUBLE, CODE_FOR_spu_convert, "si_from_double", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_DOUBLE))
DEF_BUILTIN (SI_FROM_PTR, CODE_FOR_spu_convert, "si_from_ptr", B_INSN, _A2(SPU_BTI_QUADWORD, SPU_BTI_PTR))
/* definitions to support generic builtin functions: */
DEF_BUILTIN (SPU_CONVTS, CODE_FOR_spu_cflts, "spu_convts", B_INSN, _A3(SPU_BTI_V4SI, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_CONVTU, CODE_FOR_spu_cfltu, "spu_convtu", B_INSN, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_ROUNDTF, CODE_FOR_spu_frds, "spu_roundtf", B_INSN, _A2(SPU_BTI_V4SF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_MULH, CODE_FOR_spu_mpyh, "spu_mulh", B_INSN, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_MULSR, CODE_FOR_spu_mpys, "spu_mulsr", B_INSN, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_FREST, CODE_FOR_frest_v4sf, "spu_frest", B_INSN, _A2(SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_FRSQEST, CODE_FOR_frsqest_v4sf, "spu_frsqest", B_INSN, _A2(SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_NMADD, CODE_FOR_nfmav2df4, "spu_nmadd", B_INSN, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_ABSD, CODE_FOR_spu_absdb, "spu_absd", B_INSN, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_AVG, CODE_FOR_spu_avgb, "spu_avg", B_INSN, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SUMB, CODE_FOR_spu_sumb, "spu_sumb", B_INSN, _A3(SPU_BTI_UV8HI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_BISLED, CODE_FOR_spu_bisled, "spu_bisled", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_PTR))
DEF_BUILTIN (SPU_BISLED_D, CODE_FOR_spu_bisledd, "spu_bisled_d", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_PTR))
DEF_BUILTIN (SPU_BISLED_E, CODE_FOR_spu_bislede, "spu_bisled_e", B_BISLED, _A3(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_PTR))
DEF_BUILTIN (SPU_IDISABLE, CODE_FOR_spu_idisable, "spu_idisable", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_IENABLE, CODE_FOR_spu_ienable, "spu_ienable", B_INSN, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MASK_FOR_LOAD, CODE_FOR_spu_lvsr, "spu_lvsr", B_INSN, _A2(SPU_BTI_V16QI, SPU_BTI_PTR))
DEF_BUILTIN (SPU_TESTSV, CODE_FOR_dftsv, "spu_testsv", B_INSN, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_U7))
/* definitions to support overloaded generic builtin functions: */
DEF_BUILTIN (SPU_CONVTF, CODE_FOR_nothing, "spu_convtf", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CONVTF_0, CODE_FOR_spu_cuflt, "spu_convtf_0", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_CONVTF_1, CODE_FOR_spu_csflt, "spu_convtf_1", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_EXTEND, CODE_FOR_nothing, "spu_extend", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_EXTEND_0, CODE_FOR_spu_xsbh, "spu_extend_0", B_INTERNAL, _A2(SPU_BTI_V8HI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_EXTEND_1, CODE_FOR_spu_xshw, "spu_extend_1", B_INTERNAL, _A2(SPU_BTI_V4SI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_EXTEND_2, CODE_FOR_spu_xswd, "spu_extend_2", B_INTERNAL, _A2(SPU_BTI_V2DI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_EXTEND_3, CODE_FOR_spu_fesd, "spu_extend_3", B_INTERNAL, _A2(SPU_BTI_V2DF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_ADD, CODE_FOR_nothing, "spu_add", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_ADD_0, CODE_FOR_addv4si3, "spu_add_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_ADD_1, CODE_FOR_addv4si3, "spu_add_1", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_ADD_2, CODE_FOR_addv8hi3, "spu_add_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_ADD_3, CODE_FOR_addv8hi3, "spu_add_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_ADD_4, CODE_FOR_addv4sf3, "spu_add_4", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_ADD_5, CODE_FOR_addv2df3, "spu_add_5", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_ADD_6, CODE_FOR_addv8hi3, "spu_add_6", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_ADD_7, CODE_FOR_addv8hi3, "spu_add_7", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_ADD_8, CODE_FOR_addv4si3, "spu_add_8", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_ADD_9, CODE_FOR_addv4si3, "spu_add_9", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_ADDX, CODE_FOR_nothing, "spu_addx", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_ADDX_0, CODE_FOR_addx_v4si, "spu_addx_0", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_ADDX_1, CODE_FOR_addx_v4si, "spu_addx_1", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_GENC, CODE_FOR_nothing, "spu_genc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_GENC_0, CODE_FOR_cg_v4si, "spu_genc_0", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_GENC_1, CODE_FOR_cg_v4si, "spu_genc_1", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_GENCX, CODE_FOR_nothing, "spu_gencx", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_GENCX_0, CODE_FOR_cgx_v4si, "spu_gencx_0", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_GENCX_1, CODE_FOR_cgx_v4si, "spu_gencx_1", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_MADD, CODE_FOR_nothing, "spu_madd", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MADD_0, CODE_FOR_spu_mpya, "spu_madd_0", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_MADD_1, CODE_FOR_fmav4sf4, "spu_madd_1", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_MADD_2, CODE_FOR_fmav2df4, "spu_madd_2", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_MSUB, CODE_FOR_nothing, "spu_msub", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MSUB_0, CODE_FOR_fmsv4sf4, "spu_msub_0", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_MSUB_1, CODE_FOR_fmsv2df4, "spu_msub_1", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_MHHADD, CODE_FOR_nothing, "spu_mhhadd", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MHHADD_0, CODE_FOR_spu_mpyhhau, "spu_mhhadd_0", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_MHHADD_1, CODE_FOR_spu_mpyhha, "spu_mhhadd_1", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_MULE, CODE_FOR_nothing, "spu_mule", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MULE_0, CODE_FOR_vec_widen_umult_even_v8hi, "spu_mule_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_MULE_1, CODE_FOR_vec_widen_smult_even_v8hi, "spu_mule_1", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_MUL, CODE_FOR_nothing, "spu_mul", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MUL_0, CODE_FOR_mulv4sf3, "spu_mul_0", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_MUL_1, CODE_FOR_mulv2df3, "spu_mul_1", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_MULO, CODE_FOR_nothing, "spu_mulo", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MULO_0, CODE_FOR_vec_widen_smult_odd_v8hi, "spu_mulo_0", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_MULO_1, CODE_FOR_vec_widen_umult_odd_v8hi, "spu_mulo_1", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_MULO_2, CODE_FOR_vec_widen_smult_odd_v8hi, "spu_mulo_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_MULO_3, CODE_FOR_vec_widen_umult_odd_v8hi, "spu_mulo_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_NMSUB, CODE_FOR_nothing, "spu_nmsub", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_NMSUB_0, CODE_FOR_fnmav4sf4, "spu_nmsub_0", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_NMSUB_1, CODE_FOR_nfmsv2df4, "spu_nmsub_1", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_SUB, CODE_FOR_nothing, "spu_sub", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SUB_0, CODE_FOR_subv8hi3, "spu_sub_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SUB_1, CODE_FOR_subv8hi3, "spu_sub_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_SUB_2, CODE_FOR_subv4si3, "spu_sub_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SUB_3, CODE_FOR_subv4si3, "spu_sub_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_SUB_4, CODE_FOR_subv4sf3, "spu_sub_4", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_SUB_5, CODE_FOR_subv2df3, "spu_sub_5", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_SUB_6, CODE_FOR_subv8hi3, "spu_sub_6", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UINTHI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SUB_7, CODE_FOR_subv8hi3, "spu_sub_7", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_INTHI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_SUB_8, CODE_FOR_subv4si3, "spu_sub_8", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UINTSI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SUB_9, CODE_FOR_subv4si3, "spu_sub_9", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_INTSI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_SUBX, CODE_FOR_nothing, "spu_subx", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SUBX_0, CODE_FOR_sfx_v4si, "spu_subx_0", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SUBX_1, CODE_FOR_sfx_v4si, "spu_subx_1", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_GENB, CODE_FOR_nothing, "spu_genb", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_GENB_0, CODE_FOR_bg_v4si, "spu_genb_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_GENB_1, CODE_FOR_bg_v4si, "spu_genb_1", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_GENBX, CODE_FOR_nothing, "spu_genbx", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_GENBX_0, CODE_FOR_bgx_v4si, "spu_genbx_0", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_GENBX_1, CODE_FOR_bgx_v4si, "spu_genbx_1", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_CMPEQ, CODE_FOR_nothing, "spu_cmpeq", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CMPEQ_0, CODE_FOR_ceq_v16qi, "spu_cmpeq_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_CMPEQ_1, CODE_FOR_ceq_v16qi, "spu_cmpeq_1", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_CMPEQ_2, CODE_FOR_ceq_v8hi, "spu_cmpeq_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_CMPEQ_3, CODE_FOR_ceq_v8hi, "spu_cmpeq_3", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_CMPEQ_4, CODE_FOR_ceq_v4si, "spu_cmpeq_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_CMPEQ_5, CODE_FOR_ceq_v4si, "spu_cmpeq_5", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_CMPEQ_6, CODE_FOR_ceq_v4sf, "spu_cmpeq_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_CMPEQ_7, CODE_FOR_ceq_v16qi, "spu_cmpeq_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_CMPEQ_8, CODE_FOR_ceq_v16qi, "spu_cmpeq_8", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_CMPEQ_9, CODE_FOR_ceq_v8hi, "spu_cmpeq_9", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_CMPEQ_10, CODE_FOR_ceq_v8hi, "spu_cmpeq_10", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_CMPEQ_11, CODE_FOR_ceq_v4si, "spu_cmpeq_11", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_CMPEQ_12, CODE_FOR_ceq_v4si, "spu_cmpeq_12", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_CMPEQ_13, CODE_FOR_ceq_v2df, "spu_cmpeq_13", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_CMPABSEQ, CODE_FOR_nothing, "spu_cmpabseq", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CMPABSEQ_0, CODE_FOR_cmeq_v4sf, "spu_cmpabseq_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_CMPABSEQ_1, CODE_FOR_cmeq_v2df, "spu_cmpabseq_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_CMPGT, CODE_FOR_nothing, "spu_cmpgt", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CMPGT_0, CODE_FOR_clgt_v16qi, "spu_cmpgt_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_CMPGT_1, CODE_FOR_cgt_v16qi, "spu_cmpgt_1", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_CMPGT_2, CODE_FOR_clgt_v8hi, "spu_cmpgt_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_CMPGT_3, CODE_FOR_cgt_v8hi, "spu_cmpgt_3", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_CMPGT_4, CODE_FOR_clgt_v4si, "spu_cmpgt_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_CMPGT_5, CODE_FOR_cgt_v4si, "spu_cmpgt_5", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_CMPGT_6, CODE_FOR_cgt_v4sf, "spu_cmpgt_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_CMPGT_7, CODE_FOR_clgt_v16qi, "spu_cmpgt_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_CMPGT_8, CODE_FOR_cgt_v16qi, "spu_cmpgt_8", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_CMPGT_9, CODE_FOR_clgt_v8hi, "spu_cmpgt_9", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_CMPGT_10, CODE_FOR_cgt_v8hi, "spu_cmpgt_10", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_CMPGT_11, CODE_FOR_cgt_v4si, "spu_cmpgt_11", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_CMPGT_12, CODE_FOR_clgt_v4si, "spu_cmpgt_12", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_CMPGT_13, CODE_FOR_cgt_v2df, "spu_cmpgt_13", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_CMPABSGT, CODE_FOR_nothing, "spu_cmpabsgt", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CMPABSGT_0, CODE_FOR_cmgt_v4sf, "spu_cmpabsgt_0", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_CMPABSGT_1, CODE_FOR_cmgt_v2df, "spu_cmpabsgt_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_HCMPEQ, CODE_FOR_nothing, "spu_hcmpeq", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_HCMPEQ_0, CODE_FOR_spu_heq, "spu_hcmpeq_0", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_INTSI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_HCMPEQ_1, CODE_FOR_spu_heq, "spu_hcmpeq_1", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_UINTSI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_HCMPGT, CODE_FOR_nothing, "spu_hcmpgt", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_HCMPGT_0, CODE_FOR_spu_hgt, "spu_hcmpgt_0", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_INTSI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_HCMPGT_1, CODE_FOR_spu_hlgt, "spu_hcmpgt_1", B_INTERNAL, _A3(SPU_BTI_VOID, SPU_BTI_UINTSI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_CNTB, CODE_FOR_nothing, "spu_cntb", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CNTB_0, CODE_FOR_cntb_v16qi, "spu_cntb_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_CNTB_1, CODE_FOR_cntb_v16qi, "spu_cntb_1", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_CNTLZ, CODE_FOR_nothing, "spu_cntlz", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_CNTLZ_0, CODE_FOR_clzv4si2, "spu_cntlz_0", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_CNTLZ_1, CODE_FOR_clzv4si2, "spu_cntlz_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_CNTLZ_2, CODE_FOR_clzv4si2, "spu_cntlz_2", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_GATHER, CODE_FOR_nothing, "spu_gather", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_GATHER_0, CODE_FOR_spu_gb, "spu_gather_0", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_GATHER_1, CODE_FOR_spu_gb, "spu_gather_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_GATHER_2, CODE_FOR_spu_gbh, "spu_gather_2", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_GATHER_3, CODE_FOR_spu_gbh, "spu_gather_3", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_GATHER_4, CODE_FOR_spu_gbb, "spu_gather_4", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_GATHER_5, CODE_FOR_spu_gbb, "spu_gather_5", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_GATHER_6, CODE_FOR_spu_gb, "spu_gather_6", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_MASKB, CODE_FOR_nothing, "spu_maskb", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MASKB_0, CODE_FOR_spu_fsmb, "spu_maskb_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_MASKB_1, CODE_FOR_spu_fsmb, "spu_maskb_1", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_MASKB_2, CODE_FOR_spu_fsmb, "spu_maskb_2", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_MASKB_3, CODE_FOR_spu_fsmb, "spu_maskb_3", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_MASKH, CODE_FOR_nothing, "spu_maskh", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MASKH_0, CODE_FOR_spu_fsmh, "spu_maskh_0", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_MASKH_1, CODE_FOR_spu_fsmh, "spu_maskh_1", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_MASKH_2, CODE_FOR_spu_fsmh, "spu_maskh_2", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_MASKH_3, CODE_FOR_spu_fsmh, "spu_maskh_3", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_MASKH_4, CODE_FOR_spu_fsmh, "spu_maskh_4", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_MASKH_5, CODE_FOR_spu_fsmh, "spu_maskh_5", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_MASKW, CODE_FOR_nothing, "spu_maskw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_MASKW_0, CODE_FOR_spu_fsm, "spu_maskw_0", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_MASKW_1, CODE_FOR_spu_fsm, "spu_maskw_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_MASKW_2, CODE_FOR_spu_fsm, "spu_maskw_2", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_MASKW_3, CODE_FOR_spu_fsm, "spu_maskw_3", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_MASKW_4, CODE_FOR_spu_fsm, "spu_maskw_4", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_MASKW_5, CODE_FOR_spu_fsm, "spu_maskw_5", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_SEL, CODE_FOR_nothing, "spu_sel", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SEL_0, CODE_FOR_selb, "spu_sel_0", B_INTERNAL, _A4(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_SEL_1, CODE_FOR_selb, "spu_sel_1", B_INTERNAL, _A4(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_SEL_2, CODE_FOR_selb, "spu_sel_2", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SEL_3, CODE_FOR_selb, "spu_sel_3", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SEL_4, CODE_FOR_selb, "spu_sel_4", B_INTERNAL, _A4(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SEL_5, CODE_FOR_selb, "spu_sel_5", B_INTERNAL, _A4(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SEL_6, CODE_FOR_selb, "spu_sel_6", B_INTERNAL, _A4(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SEL_7, CODE_FOR_selb, "spu_sel_7", B_INTERNAL, _A4(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SEL_8, CODE_FOR_selb, "spu_sel_8", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SEL_9, CODE_FOR_selb, "spu_sel_9", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_SHUFFLE, CODE_FOR_nothing, "spu_shuffle", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SHUFFLE_0, CODE_FOR_shufb, "spu_shuffle_0", B_INTERNAL, _A4(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_1, CODE_FOR_shufb, "spu_shuffle_1", B_INTERNAL, _A4(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_2, CODE_FOR_shufb, "spu_shuffle_2", B_INTERNAL, _A4(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_3, CODE_FOR_shufb, "spu_shuffle_3", B_INTERNAL, _A4(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_4, CODE_FOR_shufb, "spu_shuffle_4", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_5, CODE_FOR_shufb, "spu_shuffle_5", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_6, CODE_FOR_shufb, "spu_shuffle_6", B_INTERNAL, _A4(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_7, CODE_FOR_shufb, "spu_shuffle_7", B_INTERNAL, _A4(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_8, CODE_FOR_shufb, "spu_shuffle_8", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_SHUFFLE_9, CODE_FOR_shufb, "spu_shuffle_9", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_AND, CODE_FOR_nothing, "spu_and", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_AND_0, CODE_FOR_andv16qi3, "spu_and_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_AND_1, CODE_FOR_andv16qi3, "spu_and_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_AND_2, CODE_FOR_andv8hi3, "spu_and_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_AND_3, CODE_FOR_andv8hi3, "spu_and_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_AND_4, CODE_FOR_andv4si3, "spu_and_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_AND_5, CODE_FOR_andv4si3, "spu_and_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_AND_6, CODE_FOR_andv2di3, "spu_and_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_AND_7, CODE_FOR_andv2di3, "spu_and_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_AND_8, CODE_FOR_andv4si3, "spu_and_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_AND_9, CODE_FOR_andv2di3, "spu_and_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_AND_10, CODE_FOR_andv16qi3, "spu_and_10", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_AND_11, CODE_FOR_andv16qi3, "spu_and_11", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_AND_12, CODE_FOR_andv8hi3, "spu_and_12", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_AND_13, CODE_FOR_andv8hi3, "spu_and_13", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_AND_14, CODE_FOR_andv4si3, "spu_and_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_AND_15, CODE_FOR_andv4si3, "spu_and_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_ANDC, CODE_FOR_nothing, "spu_andc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_ANDC_0, CODE_FOR_andc_v2di, "spu_andc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_ANDC_1, CODE_FOR_andc_v2di, "spu_andc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_ANDC_2, CODE_FOR_andc_v4si, "spu_andc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_ANDC_3, CODE_FOR_andc_v4si, "spu_andc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_ANDC_4, CODE_FOR_andc_v8hi, "spu_andc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_ANDC_5, CODE_FOR_andc_v8hi, "spu_andc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_ANDC_6, CODE_FOR_andc_v16qi, "spu_andc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_ANDC_7, CODE_FOR_andc_v16qi, "spu_andc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_ANDC_8, CODE_FOR_andc_v4si, "spu_andc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_ANDC_9, CODE_FOR_andc_v2di, "spu_andc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_EQV, CODE_FOR_nothing, "spu_eqv", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_EQV_0, CODE_FOR_eqv_v2di, "spu_eqv_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_EQV_1, CODE_FOR_eqv_v2di, "spu_eqv_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_EQV_2, CODE_FOR_eqv_v4si, "spu_eqv_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_EQV_3, CODE_FOR_eqv_v4si, "spu_eqv_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_EQV_4, CODE_FOR_eqv_v8hi, "spu_eqv_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_EQV_5, CODE_FOR_eqv_v8hi, "spu_eqv_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_EQV_6, CODE_FOR_eqv_v16qi, "spu_eqv_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_EQV_7, CODE_FOR_eqv_v16qi, "spu_eqv_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_EQV_8, CODE_FOR_eqv_v4si, "spu_eqv_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_EQV_9, CODE_FOR_eqv_v2di, "spu_eqv_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_NAND, CODE_FOR_nothing, "spu_nand", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_NAND_0, CODE_FOR_nand_v2di, "spu_nand_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_NAND_1, CODE_FOR_nand_v2di, "spu_nand_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_NAND_2, CODE_FOR_nand_v4si, "spu_nand_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_NAND_3, CODE_FOR_nand_v4si, "spu_nand_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_NAND_4, CODE_FOR_nand_v8hi, "spu_nand_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_NAND_5, CODE_FOR_nand_v8hi, "spu_nand_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_NAND_6, CODE_FOR_nand_v16qi, "spu_nand_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_NAND_7, CODE_FOR_nand_v16qi, "spu_nand_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_NAND_8, CODE_FOR_nand_v4si, "spu_nand_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_NAND_9, CODE_FOR_nand_v2di, "spu_nand_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_NOR, CODE_FOR_nothing, "spu_nor", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_NOR_0, CODE_FOR_nor_v2di, "spu_nor_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_NOR_1, CODE_FOR_nor_v2di, "spu_nor_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_NOR_2, CODE_FOR_nor_v4si, "spu_nor_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_NOR_3, CODE_FOR_nor_v4si, "spu_nor_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_NOR_4, CODE_FOR_nor_v8hi, "spu_nor_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_NOR_5, CODE_FOR_nor_v8hi, "spu_nor_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_NOR_6, CODE_FOR_nor_v16qi, "spu_nor_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_NOR_7, CODE_FOR_nor_v16qi, "spu_nor_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_NOR_8, CODE_FOR_nor_v4si, "spu_nor_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_NOR_9, CODE_FOR_nor_v2di, "spu_nor_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_OR, CODE_FOR_nothing, "spu_or", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_OR_0, CODE_FOR_iorv16qi3, "spu_or_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_OR_1, CODE_FOR_iorv16qi3, "spu_or_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_OR_2, CODE_FOR_iorv8hi3, "spu_or_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_OR_3, CODE_FOR_iorv8hi3, "spu_or_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_OR_4, CODE_FOR_iorv4si3, "spu_or_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_OR_5, CODE_FOR_iorv4si3, "spu_or_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_OR_6, CODE_FOR_iorv2di3, "spu_or_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_OR_7, CODE_FOR_iorv2di3, "spu_or_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_OR_8, CODE_FOR_iorv4si3, "spu_or_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_OR_9, CODE_FOR_iorv2di3, "spu_or_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_OR_10, CODE_FOR_iorv16qi3, "spu_or_10", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_OR_11, CODE_FOR_iorv16qi3, "spu_or_11", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_OR_12, CODE_FOR_iorv8hi3, "spu_or_12", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_OR_13, CODE_FOR_iorv8hi3, "spu_or_13", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_OR_14, CODE_FOR_iorv4si3, "spu_or_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_OR_15, CODE_FOR_iorv4si3, "spu_or_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_ORC, CODE_FOR_nothing, "spu_orc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_ORC_0, CODE_FOR_orc_v2di, "spu_orc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_ORC_1, CODE_FOR_orc_v2di, "spu_orc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_ORC_2, CODE_FOR_orc_v4si, "spu_orc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_ORC_3, CODE_FOR_orc_v4si, "spu_orc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_ORC_4, CODE_FOR_orc_v8hi, "spu_orc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_ORC_5, CODE_FOR_orc_v8hi, "spu_orc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_ORC_6, CODE_FOR_orc_v16qi, "spu_orc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_ORC_7, CODE_FOR_orc_v16qi, "spu_orc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_ORC_8, CODE_FOR_orc_v4si, "spu_orc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_ORC_9, CODE_FOR_orc_v2di, "spu_orc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_ORX, CODE_FOR_nothing, "spu_orx", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_ORX_0, CODE_FOR_spu_orx, "spu_orx_0", B_INTERNAL, _A2(SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_ORX_1, CODE_FOR_spu_orx, "spu_orx_1", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_XOR, CODE_FOR_nothing, "spu_xor", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_XOR_0, CODE_FOR_xorv16qi3, "spu_xor_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UV16QI))
DEF_BUILTIN (SPU_XOR_1, CODE_FOR_xorv16qi3, "spu_xor_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_V16QI))
DEF_BUILTIN (SPU_XOR_2, CODE_FOR_xorv8hi3, "spu_xor_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_XOR_3, CODE_FOR_xorv8hi3, "spu_xor_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_XOR_4, CODE_FOR_xorv4si3, "spu_xor_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_XOR_5, CODE_FOR_xorv4si3, "spu_xor_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_XOR_6, CODE_FOR_xorv2di3, "spu_xor_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UV2DI))
DEF_BUILTIN (SPU_XOR_7, CODE_FOR_xorv2di3, "spu_xor_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_V2DI))
DEF_BUILTIN (SPU_XOR_8, CODE_FOR_xorv4si3, "spu_xor_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_V4SF))
DEF_BUILTIN (SPU_XOR_9, CODE_FOR_xorv2di3, "spu_xor_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_V2DF))
DEF_BUILTIN (SPU_XOR_10, CODE_FOR_xorv16qi3, "spu_xor_10", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_XOR_11, CODE_FOR_xorv16qi3, "spu_xor_11", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_XOR_12, CODE_FOR_xorv8hi3, "spu_xor_12", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_XOR_13, CODE_FOR_xorv8hi3, "spu_xor_13", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_XOR_14, CODE_FOR_xorv4si3, "spu_xor_14", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_XOR_15, CODE_FOR_xorv4si3, "spu_xor_15", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RL, CODE_FOR_nothing, "spu_rl", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RL_0, CODE_FOR_vrotlv8hi3, "spu_rl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_RL_1, CODE_FOR_vrotlv8hi3, "spu_rl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_RL_2, CODE_FOR_vrotlv4si3, "spu_rl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_RL_3, CODE_FOR_vrotlv4si3, "spu_rl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_RL_4, CODE_FOR_vrotlv8hi3, "spu_rl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_RL_5, CODE_FOR_vrotlv8hi3, "spu_rl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_RL_6, CODE_FOR_vrotlv4si3, "spu_rl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RL_7, CODE_FOR_vrotlv4si3, "spu_rl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW, CODE_FOR_nothing, "spu_rlqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLQW_0, CODE_FOR_rotqbi_ti, "spu_rlqw_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_1, CODE_FOR_rotqbi_ti, "spu_rlqw_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_2, CODE_FOR_rotqbi_ti, "spu_rlqw_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_3, CODE_FOR_rotqbi_ti, "spu_rlqw_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_4, CODE_FOR_rotqbi_ti, "spu_rlqw_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_5, CODE_FOR_rotqbi_ti, "spu_rlqw_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_6, CODE_FOR_rotqbi_ti, "spu_rlqw_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_7, CODE_FOR_rotqbi_ti, "spu_rlqw_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_8, CODE_FOR_rotqbi_ti, "spu_rlqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQW_9, CODE_FOR_rotqbi_ti, "spu_rlqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE, CODE_FOR_nothing, "spu_rlqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLQWBYTE_0, CODE_FOR_rotqby_ti, "spu_rlqwbyte_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_1, CODE_FOR_rotqby_ti, "spu_rlqwbyte_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_2, CODE_FOR_rotqby_ti, "spu_rlqwbyte_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_3, CODE_FOR_rotqby_ti, "spu_rlqwbyte_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_4, CODE_FOR_rotqby_ti, "spu_rlqwbyte_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_5, CODE_FOR_rotqby_ti, "spu_rlqwbyte_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_6, CODE_FOR_rotqby_ti, "spu_rlqwbyte_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_7, CODE_FOR_rotqby_ti, "spu_rlqwbyte_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_8, CODE_FOR_rotqby_ti, "spu_rlqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTE_9, CODE_FOR_rotqby_ti, "spu_rlqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC, CODE_FOR_nothing, "spu_rlqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLQWBYTEBC_0, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_1, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_2, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_3, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_4, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_5, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_6, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_7, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_8, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLQWBYTEBC_9, CODE_FOR_rotqbybi_ti, "spu_rlqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASK, CODE_FOR_nothing, "spu_rlmask", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLMASK_0, CODE_FOR_rotm_v8hi, "spu_rlmask_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_RLMASK_1, CODE_FOR_rotm_v8hi, "spu_rlmask_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_RLMASK_2, CODE_FOR_rotm_v4si, "spu_rlmask_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_RLMASK_3, CODE_FOR_rotm_v4si, "spu_rlmask_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_RLMASK_4, CODE_FOR_rotm_v8hi, "spu_rlmask_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASK_5, CODE_FOR_rotm_v8hi, "spu_rlmask_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASK_6, CODE_FOR_rotm_v4si, "spu_rlmask_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASK_7, CODE_FOR_rotm_v4si, "spu_rlmask_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKA, CODE_FOR_nothing, "spu_rlmaska", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLMASKA_0, CODE_FOR_rotma_v8hi, "spu_rlmaska_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_RLMASKA_1, CODE_FOR_rotma_v8hi, "spu_rlmaska_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_V8HI))
DEF_BUILTIN (SPU_RLMASKA_2, CODE_FOR_rotma_v4si, "spu_rlmaska_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_RLMASKA_3, CODE_FOR_rotma_v4si, "spu_rlmaska_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_V4SI))
DEF_BUILTIN (SPU_RLMASKA_4, CODE_FOR_rotma_v8hi, "spu_rlmaska_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKA_5, CODE_FOR_rotma_v8hi, "spu_rlmaska_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKA_6, CODE_FOR_rotma_v4si, "spu_rlmaska_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKA_7, CODE_FOR_rotma_v4si, "spu_rlmaska_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW, CODE_FOR_nothing, "spu_rlmaskqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLMASKQW_0, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_1, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_2, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_3, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_4, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_5, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_6, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_7, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_8, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQW_9, CODE_FOR_rotqmbi_ti, "spu_rlmaskqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE, CODE_FOR_nothing, "spu_rlmaskqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLMASKQWBYTE_0, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_1, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_2, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_3, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_4, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_5, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_6, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_7, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_8, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTE_9, CODE_FOR_rotqmby_ti, "spu_rlmaskqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC, CODE_FOR_nothing, "spu_rlmaskqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_0, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_1, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_2, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_3, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_4, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_5, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_6, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_7, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_8, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_RLMASKQWBYTEBC_9, CODE_FOR_rotqmbybi_ti, "spu_rlmaskqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_SL, CODE_FOR_nothing, "spu_sl", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SL_0, CODE_FOR_vashlv8hi3, "spu_sl_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SL_1, CODE_FOR_vashlv8hi3, "spu_sl_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SL_2, CODE_FOR_vashlv4si3, "spu_sl_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SL_3, CODE_FOR_vashlv4si3, "spu_sl_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SL_4, CODE_FOR_vashlv8hi3, "spu_sl_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SL_5, CODE_FOR_vashlv8hi3, "spu_sl_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SL_6, CODE_FOR_vashlv4si3, "spu_sl_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SL_7, CODE_FOR_vashlv4si3, "spu_sl_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW, CODE_FOR_nothing, "spu_slqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SLQW_0, CODE_FOR_shlqbi_ti, "spu_slqw_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_1, CODE_FOR_shlqbi_ti, "spu_slqw_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_2, CODE_FOR_shlqbi_ti, "spu_slqw_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_3, CODE_FOR_shlqbi_ti, "spu_slqw_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_4, CODE_FOR_shlqbi_ti, "spu_slqw_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_5, CODE_FOR_shlqbi_ti, "spu_slqw_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_6, CODE_FOR_shlqbi_ti, "spu_slqw_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_7, CODE_FOR_shlqbi_ti, "spu_slqw_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_8, CODE_FOR_shlqbi_ti, "spu_slqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQW_9, CODE_FOR_shlqbi_ti, "spu_slqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE, CODE_FOR_nothing, "spu_slqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SLQWBYTE_0, CODE_FOR_shlqby_ti, "spu_slqwbyte_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_1, CODE_FOR_shlqby_ti, "spu_slqwbyte_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_2, CODE_FOR_shlqby_ti, "spu_slqwbyte_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_3, CODE_FOR_shlqby_ti, "spu_slqwbyte_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_4, CODE_FOR_shlqby_ti, "spu_slqwbyte_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_5, CODE_FOR_shlqby_ti, "spu_slqwbyte_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_6, CODE_FOR_shlqby_ti, "spu_slqwbyte_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_7, CODE_FOR_shlqby_ti, "spu_slqwbyte_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_8, CODE_FOR_shlqby_ti, "spu_slqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTE_9, CODE_FOR_shlqby_ti, "spu_slqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC, CODE_FOR_nothing, "spu_slqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SLQWBYTEBC_0, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_1, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_2, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_3, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_4, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_5, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_6, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_7, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_8, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SLQWBYTEBC_9, CODE_FOR_shlqbybi_ti, "spu_slqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR, CODE_FOR_nothing, "spu_sr", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SR_0, CODE_FOR_vlshrv8hi3, "spu_sr_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SR_1, CODE_FOR_vlshrv8hi3, "spu_sr_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SR_2, CODE_FOR_vlshrv4si3, "spu_sr_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SR_3, CODE_FOR_vlshrv4si3, "spu_sr_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SR_4, CODE_FOR_vlshrv8hi3, "spu_sr_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR_5, CODE_FOR_vlshrv8hi3, "spu_sr_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR_6, CODE_FOR_vlshrv4si3, "spu_sr_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SR_7, CODE_FOR_vlshrv4si3, "spu_sr_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA, CODE_FOR_nothing, "spu_sra", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRA_0, CODE_FOR_vashrv8hi3, "spu_sra_0", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SRA_1, CODE_FOR_vashrv8hi3, "spu_sra_1", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UV8HI))
DEF_BUILTIN (SPU_SRA_2, CODE_FOR_vashrv4si3, "spu_sra_2", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SRA_3, CODE_FOR_vashrv4si3, "spu_sra_3", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UV4SI))
DEF_BUILTIN (SPU_SRA_4, CODE_FOR_vashrv8hi3, "spu_sra_4", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA_5, CODE_FOR_vashrv8hi3, "spu_sra_5", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA_6, CODE_FOR_vashrv4si3, "spu_sra_6", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRA_7, CODE_FOR_vashrv4si3, "spu_sra_7", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW, CODE_FOR_nothing, "spu_srqw", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRQW_0, CODE_FOR_shrqbi_ti, "spu_srqw_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_1, CODE_FOR_shrqbi_ti, "spu_srqw_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_2, CODE_FOR_shrqbi_ti, "spu_srqw_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_3, CODE_FOR_shrqbi_ti, "spu_srqw_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_4, CODE_FOR_shrqbi_ti, "spu_srqw_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_5, CODE_FOR_shrqbi_ti, "spu_srqw_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_6, CODE_FOR_shrqbi_ti, "spu_srqw_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_7, CODE_FOR_shrqbi_ti, "spu_srqw_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_8, CODE_FOR_shrqbi_ti, "spu_srqw_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQW_9, CODE_FOR_shrqbi_ti, "spu_srqw_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE, CODE_FOR_nothing, "spu_srqwbyte", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRQWBYTE_0, CODE_FOR_shrqby_ti, "spu_srqwbyte_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_1, CODE_FOR_shrqby_ti, "spu_srqwbyte_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_2, CODE_FOR_shrqby_ti, "spu_srqwbyte_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_3, CODE_FOR_shrqby_ti, "spu_srqwbyte_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_4, CODE_FOR_shrqby_ti, "spu_srqwbyte_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_5, CODE_FOR_shrqby_ti, "spu_srqwbyte_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_6, CODE_FOR_shrqby_ti, "spu_srqwbyte_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_7, CODE_FOR_shrqby_ti, "spu_srqwbyte_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_8, CODE_FOR_shrqby_ti, "spu_srqwbyte_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTE_9, CODE_FOR_shrqby_ti, "spu_srqwbyte_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC, CODE_FOR_nothing, "spu_srqwbytebc", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SRQWBYTEBC_0, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_0", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_V2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_1, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_1", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UV2DI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_2, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_2", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_V4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_3, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_3", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_4, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_4", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_V8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_5, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_5", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UV8HI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_6, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_6", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_V16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_7, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_7", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UV16QI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_8, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_V4SF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SRQWBYTEBC_9, CODE_FOR_shrqbybi_ti, "spu_srqwbytebc_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_V2DF, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SPLATS, CODE_FOR_nothing, "spu_splats", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_SPLATS_0, CODE_FOR_spu_splats, "spu_splats_0", B_INTERNAL, _A2(SPU_BTI_UV16QI, SPU_BTI_UINTQI))
DEF_BUILTIN (SPU_SPLATS_1, CODE_FOR_spu_splats, "spu_splats_1", B_INTERNAL, _A2(SPU_BTI_V16QI, SPU_BTI_INTQI))
DEF_BUILTIN (SPU_SPLATS_2, CODE_FOR_spu_splats, "spu_splats_2", B_INTERNAL, _A2(SPU_BTI_UV8HI, SPU_BTI_UINTHI))
DEF_BUILTIN (SPU_SPLATS_3, CODE_FOR_spu_splats, "spu_splats_3", B_INTERNAL, _A2(SPU_BTI_V8HI, SPU_BTI_INTHI))
DEF_BUILTIN (SPU_SPLATS_4, CODE_FOR_spu_splats, "spu_splats_4", B_INTERNAL, _A2(SPU_BTI_UV4SI, SPU_BTI_UINTSI))
DEF_BUILTIN (SPU_SPLATS_5, CODE_FOR_spu_splats, "spu_splats_5", B_INTERNAL, _A2(SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_SPLATS_6, CODE_FOR_spu_splats, "spu_splats_6", B_INTERNAL, _A2(SPU_BTI_UV2DI, SPU_BTI_UINTDI))
DEF_BUILTIN (SPU_SPLATS_7, CODE_FOR_spu_splats, "spu_splats_7", B_INTERNAL, _A2(SPU_BTI_V2DI, SPU_BTI_INTDI))
DEF_BUILTIN (SPU_SPLATS_8, CODE_FOR_spu_splats, "spu_splats_8", B_INTERNAL, _A2(SPU_BTI_V4SF, SPU_BTI_FLOAT))
DEF_BUILTIN (SPU_SPLATS_9, CODE_FOR_spu_splats, "spu_splats_9", B_INTERNAL, _A2(SPU_BTI_V2DF, SPU_BTI_DOUBLE))
DEF_BUILTIN (SPU_EXTRACT, CODE_FOR_nothing, "spu_extract", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_EXTRACT_0, CODE_FOR_spu_extract, "spu_extract_0", B_INTERNAL, _A3(SPU_BTI_UINTQI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_1, CODE_FOR_spu_extract, "spu_extract_1", B_INTERNAL, _A3(SPU_BTI_INTQI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_2, CODE_FOR_spu_extract, "spu_extract_2", B_INTERNAL, _A3(SPU_BTI_UINTHI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_3, CODE_FOR_spu_extract, "spu_extract_3", B_INTERNAL, _A3(SPU_BTI_INTHI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_4, CODE_FOR_spu_extract, "spu_extract_4", B_INTERNAL, _A3(SPU_BTI_UINTSI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_5, CODE_FOR_spu_extract, "spu_extract_5", B_INTERNAL, _A3(SPU_BTI_INTSI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_6, CODE_FOR_spu_extract, "spu_extract_6", B_INTERNAL, _A3(SPU_BTI_UINTDI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_7, CODE_FOR_spu_extract, "spu_extract_7", B_INTERNAL, _A3(SPU_BTI_INTDI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_8, CODE_FOR_spu_extract, "spu_extract_8", B_INTERNAL, _A3(SPU_BTI_FLOAT, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_EXTRACT_9, CODE_FOR_spu_extract, "spu_extract_9", B_INTERNAL, _A3(SPU_BTI_DOUBLE, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT, CODE_FOR_nothing, "spu_insert", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_INSERT_0, CODE_FOR_spu_insert, "spu_insert_0", B_INTERNAL, _A4(SPU_BTI_UV16QI, SPU_BTI_UINTQI, SPU_BTI_UV16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_1, CODE_FOR_spu_insert, "spu_insert_1", B_INTERNAL, _A4(SPU_BTI_V16QI, SPU_BTI_INTQI, SPU_BTI_V16QI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_2, CODE_FOR_spu_insert, "spu_insert_2", B_INTERNAL, _A4(SPU_BTI_UV8HI, SPU_BTI_UINTHI, SPU_BTI_UV8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_3, CODE_FOR_spu_insert, "spu_insert_3", B_INTERNAL, _A4(SPU_BTI_V8HI, SPU_BTI_INTHI, SPU_BTI_V8HI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_4, CODE_FOR_spu_insert, "spu_insert_4", B_INTERNAL, _A4(SPU_BTI_UV4SI, SPU_BTI_UINTSI, SPU_BTI_UV4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_5, CODE_FOR_spu_insert, "spu_insert_5", B_INTERNAL, _A4(SPU_BTI_V4SI, SPU_BTI_INTSI, SPU_BTI_V4SI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_6, CODE_FOR_spu_insert, "spu_insert_6", B_INTERNAL, _A4(SPU_BTI_UV2DI, SPU_BTI_UINTDI, SPU_BTI_UV2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_7, CODE_FOR_spu_insert, "spu_insert_7", B_INTERNAL, _A4(SPU_BTI_V2DI, SPU_BTI_INTDI, SPU_BTI_V2DI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_8, CODE_FOR_spu_insert, "spu_insert_8", B_INTERNAL, _A4(SPU_BTI_V4SF, SPU_BTI_FLOAT, SPU_BTI_V4SF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_INSERT_9, CODE_FOR_spu_insert, "spu_insert_9", B_INTERNAL, _A4(SPU_BTI_V2DF, SPU_BTI_DOUBLE, SPU_BTI_V2DF, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE, CODE_FOR_nothing, "spu_promote", B_OVERLOAD, _A1(SPU_BTI_VOID))
DEF_BUILTIN (SPU_PROMOTE_0, CODE_FOR_spu_promote, "spu_promote_0", B_INTERNAL, _A3(SPU_BTI_UV16QI, SPU_BTI_UINTQI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_1, CODE_FOR_spu_promote, "spu_promote_1", B_INTERNAL, _A3(SPU_BTI_V16QI, SPU_BTI_INTQI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_2, CODE_FOR_spu_promote, "spu_promote_2", B_INTERNAL, _A3(SPU_BTI_UV8HI, SPU_BTI_UINTHI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_3, CODE_FOR_spu_promote, "spu_promote_3", B_INTERNAL, _A3(SPU_BTI_V8HI, SPU_BTI_INTHI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_4, CODE_FOR_spu_promote, "spu_promote_4", B_INTERNAL, _A3(SPU_BTI_UV4SI, SPU_BTI_UINTSI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_5, CODE_FOR_spu_promote, "spu_promote_5", B_INTERNAL, _A3(SPU_BTI_V4SI, SPU_BTI_INTSI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_6, CODE_FOR_spu_promote, "spu_promote_6", B_INTERNAL, _A3(SPU_BTI_UV2DI, SPU_BTI_UINTDI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_7, CODE_FOR_spu_promote, "spu_promote_7", B_INTERNAL, _A3(SPU_BTI_V2DI, SPU_BTI_INTDI, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_8, CODE_FOR_spu_promote, "spu_promote_8", B_INTERNAL, _A3(SPU_BTI_V4SF, SPU_BTI_FLOAT, SPU_BTI_INTSI))
DEF_BUILTIN (SPU_PROMOTE_9, CODE_FOR_spu_promote, "spu_promote_9", B_INTERNAL, _A3(SPU_BTI_V2DF, SPU_BTI_DOUBLE, SPU_BTI_INTSI))
/* We need something that is not B_INTERNAL as a sentinel. */
/* These are for the convenience of implementing fma() in the standard
libraries. */
DEF_BUILTIN (SCALAR_FMA, CODE_FOR_fmasf4, "fmas", B_INSN, _A4(SPU_BTI_FLOAT, SPU_BTI_FLOAT, SPU_BTI_FLOAT, SPU_BTI_FLOAT))
DEF_BUILTIN (SCALAR_DFMA, CODE_FOR_fmadf4, "dfmas", B_INSN, _A4(SPU_BTI_DOUBLE, SPU_BTI_DOUBLE, SPU_BTI_DOUBLE, SPU_BTI_DOUBLE))
DEF_BUILTIN (SPU_ALIGN_HINT, CODE_FOR_spu_align_hint,"spu_align_hint", B_INSN, _A4(SPU_BTI_VOID, SPU_BTI_PTR, SPU_BTI_7, SPU_BTI_7))
#undef _A1
#undef _A2
#undef _A3
#undef _A4

864
gcc/config/spu/spu-builtins.md
View File

@ -1,864 +0,0 @@
;; Copyright (C) 2006-2019 Free Software Foundation, Inc.
;; This file is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 3 of the License, or (at your option)
;; any later version.
;; This file is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
;; for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; This includes expands for all the intrinsics.
;; spu_expand_builtin looks at the mode of match_operand.
;; load/store
(define_expand "spu_lqd"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_nonmem_operand" ""))
(const_int -16))))]
""
{
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) & 15) != 0)
operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
if (GET_CODE (operands[2]) != CONST_INT)
{
rtx op2 = operands[2];
operands[2] = force_reg (Pmode, operands[2]);
if (!ALIGNED_SYMBOL_REF_P (op2))
emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
}
})
(define_expand "spu_lqx"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_reg_operand" ""))
(const_int -16))))]
""
"")
(define_expand "spu_lqa"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
(const_int -16))))]
""
{
if (GET_CODE (operands[1]) == CONST_INT
&& (INTVAL (operands[1]) & 15) != 0)
operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
})
(define_expand "spu_lqr"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
(const_int -16))))]
""
"")
(define_expand "spu_stqd"
[(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_nonmem_operand" ""))
(const_int -16)))
(match_operand:TI 0 "spu_reg_operand" "r,r"))]
""
{
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) & 15) != 0)
operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
if (GET_CODE (operands[2]) != CONST_INT)
{
rtx op2 = operands[2];
operands[2] = force_reg (Pmode, operands[2]);
if (!ALIGNED_SYMBOL_REF_P (op2))
emit_insn (gen_andsi3 (operands[2], operands[2], GEN_INT (-16)));
}
})
(define_expand "spu_stqx"
[(set (mem:TI (and:SI (plus:SI (match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_reg_operand" ""))
(const_int -16)))
(match_operand:TI 0 "spu_reg_operand" "r"))]
""
"")
(define_expand "spu_stqa"
[(set (mem:TI (and:SI (match_operand:SI 1 "immediate_operand" "")
(const_int -16)))
(match_operand:TI 0 "spu_reg_operand" "r"))]
""
{
if (GET_CODE (operands[1]) == CONST_INT
&& (INTVAL (operands[1]) & 15) != 0)
operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
})
(define_expand "spu_stqr"
[(set (mem:TI (and:SI (match_operand:SI 1 "address_operand" "")
(const_int -16)))
(match_operand:TI 0 "spu_reg_operand" ""))]
""
"")
;; generate control word
(define_expand "spu_cbx"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_nonmem_operand" "")
(const_int 1)] UNSPEC_CPAT))]
""
"")
(define_expand "spu_chx"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_nonmem_operand" "")
(const_int 2)] UNSPEC_CPAT))]
""
"")
(define_expand "spu_cwx"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_nonmem_operand" "")
(const_int 4)] UNSPEC_CPAT))]
""
"")
(define_expand "spu_cdx"
[(set (match_operand:TI 0 "spu_reg_operand" "")
(unspec:TI [(match_operand:SI 1 "spu_reg_operand" "")
(match_operand:SI 2 "spu_nonmem_operand" "")
(const_int 8)] UNSPEC_CPAT))]
""
"")
;; Constant formation
(define_expand "spu_ilhu"
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
(const_vector:V4SI [(match_operand:SI 1 "immediate_operand" "")]))]
""
"{ emit_insn(gen_movv4si(operands[0], spu_const(V4SImode, (INTVAL(operands[1]) << 16))));
DONE;
}")
;; integer subtract
(define_expand "spu_sfh"
[(set (match_operand:V8HI 0 "spu_reg_operand" "")
(minus:V8HI (match_operand:V8HI 2 "spu_nonmem_operand" "")
(match_operand:V8HI 1 "spu_reg_operand" "")))]
""
"")
(define_expand "spu_sf"
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
(minus:V4SI (match_operand:V4SI 2 "spu_nonmem_operand" "")
(match_operand:V4SI 1 "spu_reg_operand" "")))]
""
"")
(define_expand "spu_sfx"
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
(unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
(match_operand:V4SI 1 "spu_reg_operand" "")
(match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_SFX))]
""
"")
(define_expand "spu_bg"
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
(unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
(match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_BG))]
""
"")
(define_expand "spu_bgx"
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
(unspec:V4SI [(match_operand:V4SI 2 "spu_reg_operand" "")
(match_operand:V4SI 1 "spu_reg_operand" "")
(match_operand:V4SI 3 "spu_reg_operand" "")] UNSPEC_BGX))]
""
"")
(define_insn "spu_mpya"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
(match_operand:V4SI 3 "spu_reg_operand" "r")))]
""
"mpya\t%0,%1,%2,%3"
[(set_attr "type" "fp7")])
(define_insn "spu_mpyh"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(ashift:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
(const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
""
"mpyh\t%0,%1,%2"
[(set_attr "type" "fp7")])
(define_insn "spu_mpys"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(ashiftrt:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))
(const_vector:V4SI [(const_int 16)(const_int 16)(const_int 16)(const_int 16)])))]
""
"mpys\t%0,%1,%2"
[(set_attr "type" "fp7")])
(define_insn "spu_mpyhhau"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(plus:V4SI
(mult:V4SI
(zero_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
(zero_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
(match_operand:V4SI 3 "spu_reg_operand" "0")))]
""
"mpyhhau\t%0,%1,%2"
[(set_attr "type" "fp7")])
(define_insn "spu_mpyhha"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(plus:V4SI
(mult:V4SI
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))
(match_operand:V4SI 3 "spu_reg_operand" "0")))]
""
"mpyhha\t%0,%1,%2"
[(set_attr "type" "fp7")])
;; form select mask
(define_insn "spu_fsmb"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r,r")
(unspec:V16QI [(match_operand:SI 1 "spu_nonmem_operand" "r,MN")] UNSPEC_FSMB))]
""
"@
fsmb\t%0,%1
fsmbi\t%0,%1"
[(set_attr "type" "shuf")])
(define_insn "spu_fsmh"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(unspec:V8HI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSMH))]
""
"fsmh\t%0,%1"
[(set_attr "type" "shuf")])
(define_insn "spu_fsm"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec:V4SI [(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_FSM))]
""
"fsm\t%0,%1"
[(set_attr "type" "shuf")])
;; gather bits
(define_insn "spu_gbb"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec:V4SI [(match_operand:V16QI 1 "spu_reg_operand" "r")] UNSPEC_GBB))]
""
"gbb\t%0,%1"
[(set_attr "type" "shuf")])
(define_insn "spu_gbh"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec:V4SI [(match_operand:V8HI 1 "spu_reg_operand" "r")] UNSPEC_GBH))]
""
"gbh\t%0,%1"
[(set_attr "type" "shuf")])
(define_insn "spu_gb"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_GB))]
""
"gb\t%0,%1"
[(set_attr "type" "shuf")])
;; misc byte operations
(define_insn "spu_avgb"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
(match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_AVGB))]
""
"avgb\t%0,%1,%2"
[(set_attr "type" "fxb")])
(define_insn "spu_absdb"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(unspec:V16QI [(match_operand:V16QI 1 "spu_reg_operand" "r")
(match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_ABSDB))]
""
"absdb\t%0,%1,%2"
[(set_attr "type" "fxb")])
(define_insn "spu_sumb"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(unspec:V8HI [(match_operand:V16QI 1 "spu_reg_operand" "r")
(match_operand:V16QI 2 "spu_reg_operand" "r")] UNSPEC_SUMB))]
""
"sumb\t%0,%1,%2"
[(set_attr "type" "fxb")])
;; sign extend
(define_insn "spu_xsbh"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(sign_extend:V8HI
(vec_select:V8QI
(match_operand:V16QI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
(const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
""
"xsbh\t%0,%1")
(define_insn "spu_xshw"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(sign_extend:V4SI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
""
"xshw\t%0,%1")
(define_insn "spu_xswd"
[(set (match_operand:V2DI 0 "spu_reg_operand" "=r")
(sign_extend:V2DI
(vec_select:V2SI
(match_operand:V4SI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)]))))]
""
"xswd\t%0,%1")
;; or across
(define_insn "spu_orx"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec:V4SI [(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_ORX))]
""
"orx\t%0,%1")
;; compare & halt
(define_insn "spu_heq"
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
(match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HEQ)]
""
"@
heq\t%0,%1
heqi\t%0,%1")
(define_insn "spu_hgt"
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
(match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HGT)]
""
"@
hgt\t%0,%1
hgti\t%0,%1")
(define_insn "spu_hlgt"
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r,r")
(match_operand:SI 1 "spu_nonmem_operand" "r,K")] UNSPEC_HLGT)]
""
"@
hlgt\t%0,%1
hlgti\t%0,%1")
;; branches
;; The description below hides the fact that bisled conditionally
;; executes the call depending on the value in channel 0. This was
;; done so that the description would conform to the format of a call
;; insn. Otherwise (if this were not part of call insn), the link
;; register, $lr, would not be saved/restored in the prologue/epilogue.
(define_insn "spu_bisled"
[(parallel
[(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
(const_int 0))
(clobber (reg:SI 0))
(clobber (reg:SI 130))
(use (match_operand:SI 1 "address_operand" ""))
(use (const_int 0))])]
""
"bisled\t$lr,%0"
[(set_attr "type" "br")])
(define_insn "spu_bisledd"
[(parallel
[(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
(const_int 0))
(clobber (reg:SI 0))
(clobber (reg:SI 130))
(use (match_operand:SI 1 "address_operand" ""))
(use (const_int 1))])]
""
"bisledd\t$lr,%0"
[(set_attr "type" "br")])
(define_insn "spu_bislede"
[(parallel
[(call (mem:QI (match_operand:SI 0 "spu_reg_operand" "r"))
(const_int 0))
(clobber (reg:SI 0))
(clobber (reg:SI 130))
(use (match_operand:SI 1 "address_operand" ""))
(use (const_int 2))])]
""
"bislede\t$lr,%0"
[(set_attr "type" "br")])
;; float convert
(define_expand "spu_csflt"
[(set (match_operand:V4SF 0 "spu_reg_operand")
(unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand")
(match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
""
{
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convtf expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
if (GET_CODE (operands[2]) != CONST_INT)
{
rtx exp2;
rtx cnv = gen_reg_rtx (V4SFmode);
rtx scale = gen_reg_rtx (SImode);
rtx op2 = force_reg (SImode, operands[2]);
rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1));
emit_insn (gen_subsi3 (scale, const1_rtx, op2));
exp2 = spu_gen_exp2 (V4SFmode, scale);
emit_insn (gen_floatv4siv4sf2_mul (cnv, operands[1], m1));
emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2));
}
else
{
rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
emit_insn (gen_floatv4siv4sf2_div (operands[0], operands[1], exp2));
}
DONE;
})
(define_expand "spu_cflts"
[(set (match_operand:V4SI 0 "spu_reg_operand")
(unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand")
(match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
""
{
rtx exp2;
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convts expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
if (GET_CODE (operands[2]) != CONST_INT)
{
rtx mul = gen_reg_rtx (V4SFmode);
emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
emit_insn (gen_fix_truncv4sfv4si2 (operands[0], mul));
}
else
emit_insn (gen_fix_truncv4sfv4si2_mul (operands[0], operands[1], exp2));
DONE;
})
(define_expand "spu_cuflt"
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
(unspec:V4SF [(match_operand:V4SI 1 "spu_reg_operand")
(match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
""
{
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convtf expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
if (GET_CODE (operands[2]) != CONST_INT)
{
rtx exp2;
rtx cnv = gen_reg_rtx (V4SFmode);
rtx scale = gen_reg_rtx (SImode);
rtx op2 = force_reg (SImode, operands[2]);
rtx m1 = spu_gen_exp2 (V4SFmode, GEN_INT (-1));
emit_insn (gen_subsi3 (scale, const1_rtx, op2));
exp2 = spu_gen_exp2 (V4SFmode, scale);
emit_insn (gen_floatunsv4siv4sf2_mul (cnv, operands[1], m1));
emit_insn (gen_mulv4sf3 (operands[0], cnv, exp2));
}
else
{
rtx exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
emit_insn (gen_floatunsv4siv4sf2_div (operands[0], operands[1], exp2));
}
DONE;
})
(define_expand "spu_cfltu"
[(set (match_operand:V4SI 0 "spu_reg_operand")
(unspec:V4SI [(match_operand:V4SF 1 "spu_reg_operand")
(match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
""
{
rtx exp2;
if (GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convtu expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
if (GET_CODE (operands[2]) != CONST_INT)
{
rtx mul = gen_reg_rtx (V4SFmode);
emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
emit_insn (gen_fixuns_truncv4sfv4si2 (operands[0], mul));
}
else
emit_insn (gen_fixuns_truncv4sfv4si2_mul (operands[0], operands[1], exp2));
DONE;
})
(define_expand "spu_frds"
[(set (match_operand:V4SF 0 "spu_reg_operand" "")
(vec_select:V4SF
(vec_concat:V4SF
(float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" ""))
(match_dup:V2SF 2))
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
""
"operands[2] = spu_const(V2SFmode, 0);")
(define_insn "_frds"
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
(vec_select:V4SF
(vec_concat:V4SF
(float_truncate:V2SF (match_operand:V2DF 1 "spu_reg_operand" "r"))
(match_operand:V2SF 2 "vec_imm_operand" "i"))
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
""
"frds\t%0,%1"
[(set_attr "type" "fpd")])
(define_insn "spu_fesd"
[(set (match_operand:V2DF 0 "spu_reg_operand" "=r")
(float_extend:V2DF
(vec_select:V2SF
(match_operand:V4SF 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)]))))]
""
"fesd\t%0,%1"
[(set_attr "type" "fpd")])
;; control
(define_insn "spu_stop"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "M")] UNSPEC_STOP)]
""
"stop\t%0"
[(set_attr "type" "br")])
(define_insn "spu_stopd"
[(unspec_volatile [(match_operand:SI 0 "spu_reg_operand" "r")
(match_operand:SI 1 "spu_reg_operand" "r")
(match_operand:SI 2 "spu_reg_operand" "r")] UNSPEC_STOPD)]
""
"stopd\t%0,%1,%2"
[(set_attr "type" "br")])
;; interrupt disable/enable
(define_expand "spu_idisable"
[(parallel
[(unspec_volatile [(const_int 0)] UNSPEC_SET_INTR)
(clobber (match_dup:SI 0))
(clobber (mem:BLK (scratch)))])]
""
"operands[0] = gen_reg_rtx (SImode);")
(define_expand "spu_ienable"
[(parallel
[(unspec_volatile [(const_int 1)] UNSPEC_SET_INTR)
(clobber (match_dup:SI 0))
(clobber (mem:BLK (scratch)))])]
""
"operands[0] = gen_reg_rtx (SImode);")
(define_insn "set_intr"
[(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR)
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
(clobber (mem:BLK (scratch)))]
"! flag_pic"
"ila\t%0,.+8\;bi%I1\t%0"
[(set_attr "length" "8")
(set_attr "type" "multi0")])
(define_insn "set_intr_pic"
[(unspec_volatile [(match_operand 1 "const_int_operand" "i")] UNSPEC_SET_INTR)
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
(clobber (mem:BLK (scratch)))]
"flag_pic"
"brsl\t%0,.+4\;ai\t%0,%0,8\;bi%I1\t%0"
[(set_attr "length" "12")
(set_attr "type" "multi1")])
(define_insn "set_intr_cc"
[(cond_exec (match_operator 1 "branch_comparison_operator"
[(match_operand 2 "spu_reg_operand" "r")
(const_int 0)])
(parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR)
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
(clobber (mem:BLK (scratch)))]))]
"! flag_pic"
"ila\t%0,.+8\;bi%b2%b1z%I3\t%2,%0"
[(set_attr "length" "8")
(set_attr "type" "multi0")])
(define_insn "set_intr_cc_pic"
[(cond_exec (match_operator 1 "branch_comparison_operator"
[(match_operand 2 "spu_reg_operand" "r")
(const_int 0)])
(parallel [(unspec_volatile [(match_operand:SI 3 "const_int_operand" "i")] UNSPEC_SET_INTR)
(clobber (match_operand:SI 0 "spu_reg_operand" "=&r"))
(clobber (mem:BLK (scratch)))]))]
"flag_pic"
"brsl\t%0,.+4\;ai\t%0,%0,8\;bi%b2%b1z%I3\t%2,%0"
[(set_attr "length" "12")
(set_attr "type" "multi1")])
(define_insn "set_intr_return"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")] UNSPEC_SET_INTR)
(return)]
""
"bi%I0\t$lr"
[(set_attr "type" "br")])
(define_peephole2
[(parallel
[(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPEC_SET_INTR)
(clobber (match_operand:SI 1 "spu_reg_operand"))
(clobber (mem:BLK (scratch)))])
(use (reg:SI 0))
(return)]
""
[(use (reg:SI 0))
(parallel
[(unspec_volatile [(match_dup:SI 0)] UNSPEC_SET_INTR)
(return)])]
"")
;; special purpose registers
(define_insn "spu_fscrrd"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec_volatile:V4SI [(const_int 6)] UNSPEC_FSCRRD))]
""
"fscrrd\t%0"
[(set_attr "type" "spr")])
(define_insn "spu_fscrwr"
[(unspec_volatile [(match_operand:V4SI 0 "spu_reg_operand" "r")] UNSPEC_FSCRWR)]
""
"fscrwr\t$0,%0"
[(set_attr "type" "spr")])
(define_insn "spu_mfspr"
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_MFSPR))]
""
"mfspr\t%0,$sp%1"
[(set_attr "type" "spr")])
(define_insn "spu_mtspr"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
(match_operand:SI 1 "spu_reg_operand" "r")] UNSPEC_MTSPR)]
""
"mtspr\t$sp%0,%1"
[(set_attr "type" "spr")])
;; channels
(define_expand "spu_rdch"
[(set (match_operand:V4SI 0 "spu_reg_operand" "")
(unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RDCH))]
""
"{
if (spu_safe_dma (INTVAL (operands[1])))
{
emit_insn (gen_spu_rdch_clobber (operands[0], operands[1]));
DONE;
}
}")
(define_expand "spu_rchcnt"
[(set (match_operand:SI 0 "spu_reg_operand" "")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_RCHCNT))]
""
"{
if (spu_safe_dma (INTVAL (operands[1])))
{
emit_insn (gen_spu_rchcnt_clobber (operands[0], operands[1]));
DONE;
}
}")
(define_expand "spu_wrch"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "")
(match_operand:V4SI 1 "spu_reg_operand" "")] UNSPEC_WRCH)]
""
"{
if (spu_safe_dma (INTVAL (operands[0])))
{
emit_insn (gen_spu_wrch_clobber (operands[0], operands[1]));
DONE;
}
}")
(define_insn "spu_rdch_noclobber"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))]
""
"rdch\t%0,$ch%1"
[(set_attr "type" "spr")])
(define_insn "spu_rchcnt_noclobber"
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))]
""
"rchcnt\t%0,$ch%1"
[(set_attr "type" "spr")])
(define_insn "spu_wrch_noclobber"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)]
""
"wrch\t$ch%0,%1"
[(set_attr "type" "spr")])
(define_insn "spu_rdch_clobber"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(unspec_volatile:V4SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RDCH))
(clobber (mem:BLK (scratch)))]
""
"rdch\t%0,$ch%1"
[(set_attr "type" "spr")])
(define_insn "spu_rchcnt_clobber"
[(set (match_operand:SI 0 "spu_reg_operand" "=r")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "J")] UNSPEC_RCHCNT))
(clobber (mem:BLK (scratch)))]
""
"rchcnt\t%0,$ch%1"
[(set_attr "type" "spr")])
(define_insn "spu_wrch_clobber"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "J")
(match_operand:V4SI 1 "spu_reg_operand" "r")] UNSPEC_WRCH)
(clobber (mem:BLK (scratch)))]
""
"wrch\t$ch%0,%1"
[(set_attr "type" "spr")])
(define_expand "spu_splats"
[(set (match_operand 0 "spu_reg_operand" "")
(vec_duplicate (match_operand 1 "spu_nonmem_operand" "")))]
""
{
spu_builtin_splats(operands);
DONE;
})
(define_expand "spu_extract"
[(set (match_operand 0 "spu_reg_operand" "")
(unspec [(match_operand 1 "spu_reg_operand" "")
(match_operand 2 "spu_nonmem_operand" "")] 0))]
""
{
spu_builtin_extract (operands);
DONE;
})
(define_expand "spu_insert"
[(set (match_operand 0 "spu_reg_operand" "")
(unspec [(match_operand 1 "spu_reg_operand" "")
(match_operand 2 "spu_reg_operand" "")
(match_operand:SI 3 "spu_nonmem_operand" "")] 0))]
""
{
spu_builtin_insert(operands);
DONE;
})
(define_expand "spu_promote"
[(set (match_operand 0 "spu_reg_operand" "")
(unspec [(match_operand 1 "spu_reg_operand" "")
(match_operand:SI 2 "immediate_operand" "")] 0))]
""
{
spu_builtin_promote(operands);
DONE;
})
;; Currently doing nothing with this but expanding its args.
(define_expand "spu_align_hint"
[(unspec [(match_operand:SI 0 "address_operand" "")
(match_operand:SI 1 "immediate_operand" "")
(match_operand:SI 2 "immediate_operand" "")] 0)]
""
{
DONE;
})

233
gcc/config/spu/spu-c.c
View File

@ -1,233 +0,0 @@
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "target.h"
#include "c-family/c-common.h"
#include "stringpool.h"
#include "langhooks.h"
/* Keep the vector keywords handy for fast comparisons. */
static GTY(()) tree __vector_keyword;
static GTY(()) tree vector_keyword;
static cpp_hashnode *
spu_categorize_keyword (const cpp_token *tok)
{
if (tok->type == CPP_NAME)
{
cpp_hashnode *ident = tok->val.node.node;
if (ident == C_CPP_HASHNODE (vector_keyword)
|| ident == C_CPP_HASHNODE (__vector_keyword))
return C_CPP_HASHNODE (__vector_keyword);
else
return ident;
}
return 0;
}
/* Called to decide whether a conditional macro should be expanded.
Since we have exactly one such macro (i.e, 'vector'), we do not
need to examine the 'tok' parameter. */
static cpp_hashnode *
spu_macro_to_expand (cpp_reader *pfile, const cpp_token *tok)
{
cpp_hashnode *expand_this = tok->val.node.node;
cpp_hashnode *ident;
ident = spu_categorize_keyword (tok);
if (ident == C_CPP_HASHNODE (__vector_keyword))
{
tok = cpp_peek_token (pfile, 0);
ident = spu_categorize_keyword (tok);
if (ident)
{
enum rid rid_code = (enum rid)(ident->rid_code);
if (cpp_macro_p (ident))
{
(void) cpp_get_token (pfile);
tok = cpp_peek_token (pfile, 0);
ident = spu_categorize_keyword (tok);
if (ident)
rid_code = (enum rid)(ident->rid_code);
}
if (rid_code == RID_UNSIGNED || rid_code == RID_LONG
|| rid_code == RID_SHORT || rid_code == RID_SIGNED
|| rid_code == RID_INT || rid_code == RID_CHAR
|| rid_code == RID_FLOAT || rid_code == RID_DOUBLE)
expand_this = C_CPP_HASHNODE (__vector_keyword);
}
}
return expand_this;
}
/* target hook for resolve_overloaded_builtin(). Returns a function call
RTX if we can resolve the overloaded builtin */
tree
spu_resolve_overloaded_builtin (location_t loc, tree fndecl, void *passed_args)
{
#define SCALAR_TYPE_P(t) (INTEGRAL_TYPE_P (t) \
|| SCALAR_FLOAT_TYPE_P (t) \
|| POINTER_TYPE_P (t))
vec<tree, va_gc> *fnargs = static_cast <vec<tree, va_gc> *> (passed_args);
unsigned int nargs = vec_safe_length (fnargs);
int new_fcode, fcode = DECL_MD_FUNCTION_CODE (fndecl);
struct spu_builtin_description *desc;
tree match = NULL_TREE;
/* The vector types are not available if the backend is not initialized. */
gcc_assert (!flag_preprocess_only);
desc = &spu_builtins[fcode];
if (desc->type != B_OVERLOAD)
return NULL_TREE;
/* Compare the signature of each internal builtin function with the
function arguments until a match is found. */
for (new_fcode = fcode + 1; spu_builtins[new_fcode].type == B_INTERNAL;
new_fcode++)
{
tree decl = targetm.builtin_decl (new_fcode, true);
tree params = TYPE_ARG_TYPES (TREE_TYPE (decl));
tree param;
bool all_scalar;
unsigned int p;
/* Check whether all parameters are scalar. */
all_scalar = true;
for (param = params; param != void_list_node; param = TREE_CHAIN (param))
if (!SCALAR_TYPE_P (TREE_VALUE (param)))
all_scalar = false;
for (param = params, p = 0;
param != void_list_node;
param = TREE_CHAIN (param), p++)
{
tree var, arg_type, param_type = TREE_VALUE (param);
if (p >= nargs)
{
error ("insufficient arguments to overloaded function %s",
desc->name);
return error_mark_node;
}
var = (*fnargs)[p];
if (TREE_CODE (var) == NON_LVALUE_EXPR)
var = TREE_OPERAND (var, 0);
if (TREE_CODE (var) == ERROR_MARK)
return NULL_TREE; /* Let somebody else deal with the problem. */
arg_type = TREE_TYPE (var);
/* The intrinsics spec does not specify precisely how to
resolve generic intrinsics. We require an exact match
for vector types and let C do it's usual parameter type
checking/promotions for scalar arguments, except for the
first argument of intrinsics which don't have a vector
parameter. */
if ((!SCALAR_TYPE_P (param_type)
|| !SCALAR_TYPE_P (arg_type)
|| (all_scalar && p == 0))
&& !lang_hooks.types_compatible_p (param_type, arg_type))
break;
}
if (param == void_list_node)
{
if (p != nargs)
{
error ("too many arguments to overloaded function %s",
desc->name);
return error_mark_node;
}
match = decl;
break;
}
}
if (match == NULL_TREE)
{
error ("parameter list does not match a valid signature for %s()",
desc->name);
return error_mark_node;
}
return build_function_call_vec (loc, vNULL, match, fnargs, NULL);
#undef SCALAR_TYPE_P
}
void
spu_cpu_cpp_builtins (struct cpp_reader *pfile)
{
cpp_define (pfile, "__SPU__");
cpp_assert (pfile, "cpu=spu");
cpp_assert (pfile, "machine=spu");
if (spu_arch == PROCESSOR_CELLEDP)
cpp_define (pfile, "__SPU_EDP__");
if (cpp_get_options (pfile)->lang != CLK_ASM)
cpp_define (pfile, "__vector=__attribute__((__spu_vector__))");
switch (spu_ea_model)
{
case 32:
cpp_define (pfile, "__EA32__");
break;
case 64:
cpp_define (pfile, "__EA64__");
break;
default:
gcc_unreachable ();
}
if (!flag_iso && cpp_get_options (pfile)->lang != CLK_ASM)
{
/* Define this when supporting context-sensitive keywords. */
cpp_define (pfile, "__VECTOR_KEYWORD_SUPPORTED__");
cpp_define (pfile, "vector=vector");
/* Initialize vector keywords. */
__vector_keyword = get_identifier ("__vector");
C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL;
vector_keyword = get_identifier ("vector");
C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL;
/* Enable context-sensitive macros. */
cpp_get_callbacks (pfile)->macro_to_expand = spu_macro_to_expand;
}
}
void
spu_c_common_override_options (void)
{
if (!TARGET_STD_MAIN)
{
/* Don't give warnings about the main() function. */
warn_main = 0;
}
}

75
gcc/config/spu/spu-elf.h
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@ -1,75 +0,0 @@
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef OBJECT_FORMAT_ELF
#error elf.h included before elfos.h
#endif
#define BSS_SECTION_ASM_OP "\t.section .bss"
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
/* The following macros define "native" directory locations; on the SPU,
these are used only when building the compiler with --with-sysroot.
This can be used to build a pair of PPU and SPU cross-compilers with
a common sysroot; the SPU compiler will search for its files in
${sysroot}/include and ${sysroot}/lib. */
/* STANDARD_STARTFILE_PREFIX_1 is "/lib", which we keep.
STANDARD_STARTFILE_PREFIX_2 is "/usr/lib" -- we remove this. */
#undef STANDARD_STARTFILE_PREFIX_2
#define STANDARD_STARTFILE_PREFIX_2 ""
/* We do not provide any "/usr/local/include" directory on SPU. */
#undef LOCAL_INCLUDE_DIR
/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add
the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
provides part of the support for getting C++ file-scope static
object constructed before entering `main'. */
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{mstdmain: %{pg|p:gcrt2.o%s;:crt2.o%s}}\
%{!mstdmain: %{pg|p:gcrt1.o%s;:crt1.o%s}}\
crti.o%s crtbegin.o%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO 1
#define SET_ASM_OP "\t.set\t"
#undef TARGET_ASM_NAMED_SECTION
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
#define EH_FRAME_THROUGH_COLLECT2 1
#define LINK_SPEC "%{mlarge-mem: --defsym __stack=0xfffffff0 }"
#define LIB_SPEC "-( %{!shared:%{g*:-lg}} -lc -lgloss -) \
%{mno-atomic-updates:-lgcc_cachemgr_nonatomic; :-lgcc_cachemgr} \
%{mcache-size=128:-lgcc_cache128k; \
mcache-size=64 :-lgcc_cache64k; \
mcache-size=32 :-lgcc_cache32k; \
mcache-size=16 :-lgcc_cache16k; \
mcache-size=8 :-lgcc_cache8k; \
:-lgcc_cache64k}"

29
gcc/config/spu/spu-modes.def
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@ -1,29 +0,0 @@
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Vector modes. */
VECTOR_MODES (INT, 2); /* V2QI */
VECTOR_MODES (INT, 4); /* V4QI V2HI */
VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
/* cse_insn needs an INT_MODE larger than WORD_MODE, otherwise some
parts of it will go into an infinite loop. */
INT_MODE (OI, 32);

95
gcc/config/spu/spu-protos.h
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@ -1,95 +0,0 @@
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef _SPU_PROTOS_
#define _SPU_PROTOS_
extern void spu_cpu_cpp_builtins (struct cpp_reader * pfile);
extern void builtin_define_std (const char *);
extern void spu_c_common_override_options (void);
extern int valid_subreg (rtx op);
extern void spu_expand_extv (rtx * ops, int unsignedp);
extern void spu_expand_insv (rtx * ops);
extern int spu_expand_block_move (rtx * ops);
extern void spu_emit_branch_or_set (int is_set, rtx cmp, rtx * operands);
extern int spu_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
extern HOST_WIDE_INT const_double_to_hwint (rtx x);
extern void print_operand_address (FILE * file, register rtx addr);
extern void print_operand (FILE * file, rtx x, int code);
extern int spu_split_immediate (rtx * ops);
extern int spu_saved_regs_size (void);
extern int direct_return (void);
extern void spu_expand_prologue (void);
extern void spu_expand_epilogue (bool sibcall_p);
extern rtx spu_return_addr (int count, rtx frame);
#ifdef RTX_CODE
extern rtx hwint_to_const_double (machine_mode mode, HOST_WIDE_INT v);
extern rtx spu_const (machine_mode mode, HOST_WIDE_INT val);
extern rtx spu_const_from_ints (machine_mode mode,
int a, int b, int c, int d);
extern rtx spu_float_const (const char *string,
machine_mode mode);
extern int immediate_load_p (rtx op, machine_mode mode);
extern int logical_immediate_p (rtx op, machine_mode mode);
extern int iohl_immediate_p (rtx op, machine_mode mode);
extern int arith_immediate_p (rtx op, machine_mode mode,
HOST_WIDE_INT low, HOST_WIDE_INT high);
extern bool exp2_immediate_p (rtx op, machine_mode mode, int low,
int high);
extern int spu_constant_address_p (rtx x);
extern bool spu_legitimate_constant_p (machine_mode, rtx);
extern int spu_initial_elimination_offset (int from, int to);
extern rtx spu_function_value (const_tree type, const_tree func);
extern int spu_expand_mov (rtx * ops, machine_mode mode);
extern int spu_split_load (rtx * ops);
extern int spu_split_store (rtx * ops);
extern int fsmbi_const_p (rtx x);
extern int cpat_const_p (rtx x, machine_mode mode);
extern rtx gen_cpat_const (rtx * ops);
extern void constant_to_array (machine_mode mode, rtx x,
unsigned char *arr);
extern rtx array_to_constant (machine_mode mode, const unsigned char *arr);
extern rtx spu_gen_exp2 (machine_mode mode, rtx x);
extern void spu_allocate_stack (rtx op0, rtx op1);
extern void spu_restore_stack_nonlocal (rtx op0, rtx op1);
extern void spu_restore_stack_block (rtx op0, rtx op1);
extern rtx spu_gen_subreg (machine_mode mode, rtx x);
extern int spu_safe_dma(HOST_WIDE_INT channel);
extern void spu_builtin_splats (rtx ops[]);
extern void spu_builtin_extract (rtx ops[]);
extern void spu_builtin_insert (rtx ops[]);
extern void spu_builtin_promote (rtx ops[]);
extern void spu_expand_sign_extend (rtx ops[]);
extern void spu_expand_vector_init (rtx target, rtx vals);
extern rtx spu_legitimize_reload_address (rtx, machine_mode, int, int);
extern void spu_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
rtx orig_before, rtx orig_after);
#endif /* RTX_CODE */
extern void spu_init_expanders (void);
extern void spu_split_convert (rtx *);
extern void spu_function_profiler (FILE *, int);
/* spu-c.c */
extern tree spu_resolve_overloaded_builtin (location_t, tree fndecl,
void *fnargs);
extern rtx spu_expand_builtin (tree exp, rtx target, rtx subtarget,
machine_mode mode, int ignore);
extern rtx spu_expand_builtin (tree, rtx, rtx, machine_mode, int);
#endif /* _SPU_PROTOS_ */

7469
gcc/config/spu/spu.c
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517
gcc/config/spu/spu.h
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@ -1,517 +0,0 @@
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Run-time Target */
#define TARGET_CPU_CPP_BUILTINS() spu_cpu_cpp_builtins(pfile)
#define C_COMMON_OVERRIDE_OPTIONS spu_c_common_override_options()
#define INIT_EXPANDERS spu_init_expanders()
/* Which processor to generate code or schedule for. */
enum processor_type
{
PROCESSOR_CELL,
PROCESSOR_CELLEDP
};
extern GTY(()) int spu_arch;
extern GTY(()) int spu_tune;
/* Support for a compile-time default architecture and tuning. The rules are:
--with-arch is ignored if -march is specified.
--with-tune is ignored if -mtune is specified. */
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:-march=%(VALUE)}" }, \
{"tune", "%{!mtune=*:-mtune=%(VALUE)}" }
/* Default target_flags if no switches specified. */
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_ERROR_RELOC | MASK_SAFE_DMA | MASK_BRANCH_HINTS \
| MASK_SAFE_HINTS | MASK_ADDRESS_SPACE_CONVERSION)
#endif
/* Storage Layout */
#define BITS_BIG_ENDIAN 1
#define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1
/* GCC uses word_mode in many places, assuming that it is the fastest
integer mode. That is not the case for SPU though. We can't use
32 here because (of some reason I can't remember.) */
#define BITS_PER_WORD 128
#define UNITS_PER_WORD (BITS_PER_WORD/BITS_PER_UNIT)
/* When building libgcc, we need to assume 4 words per units even
though UNITS_PER_WORD is 16, because the SPU has basically a 32-bit
instruction set although register size is 128 bits. In particular,
this causes libgcc to contain __divdi3 instead of __divti3 etc.
However, we allow this default to be re-defined on the command
line, so that we can use the LIB2_SIDITI_CONV_FUNCS mechanism
to get (in addition) TImode versions of some routines. */
#ifndef LIBGCC2_UNITS_PER_WORD
#define LIBGCC2_UNITS_PER_WORD 4
#endif
#define POINTER_SIZE 32
#define PARM_BOUNDARY 128
#define STACK_BOUNDARY 128
/* We want it 8-byte aligned so we can properly use dual-issue
instructions, which can only happen on an 8-byte aligned address. */
#define FUNCTION_BOUNDARY 64
/* We would like to allow a larger alignment for data objects (for DMA)
but the aligned attribute is limited by BIGGEST_ALIGNMENT. We don't
define BIGGEST_ALIGNMENT as larger because it is used in other places
and would end up wasting space. (Is this still true?) */
#define BIGGEST_ALIGNMENT 128
#define MINIMUM_ATOMIC_ALIGNMENT 128
/* Make all static objects 16-byte aligned. This allows us to assume
they are also padded to 16-bytes, which means we can use a single
load or store instruction to access them. Do the same for objects
on the stack. (Except a bug (?) allows some stack objects to be
unaligned.) */
#define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
#define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
#define EMPTY_FIELD_BOUNDARY 32
#define STRICT_ALIGNMENT 1
/* symbol_ref's of functions are not aligned to 16 byte boundary. */
#define ALIGNED_SYMBOL_REF_P(X) \
(GET_CODE (X) == SYMBOL_REF \
&& (SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1) == 0 \
&& (! SYMBOL_REF_FUNCTION_P (X) \
|| align_functions.levels[0].get_value () >= 16))
#define PCC_BITFIELD_TYPE_MATTERS 1
#define MAX_FIXED_MODE_SIZE 128
#define STACK_SAVEAREA_MODE(save_level) \
(save_level == SAVE_FUNCTION ? VOIDmode \
: save_level == SAVE_NONLOCAL ? SImode \
: Pmode)
#define STACK_SIZE_MODE SImode
/* Type Layout */
#define INT_TYPE_SIZE 32
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define DEFAULT_SIGNED_CHAR 0
#define STDINT_LONG32 0
/* Register Basics */
/* 128-130 are special registers that never appear in assembly code. */
#define FIRST_PSEUDO_REGISTER 131
#define FIXED_REGISTERS { \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1 \
}
#define CALL_USED_REGISTERS { \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1 \
}
/* Register Classes */
enum reg_class {
NO_REGS,
GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ "NO_REGS", \
"GENERAL_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS { \
{0, 0, 0, 0, 0}, /* no regs */ \
{0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}, /* general regs */ \
{0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}} /* all regs */
#define REGNO_REG_CLASS(REGNO) ((void)(REGNO), GENERAL_REGS)
#define BASE_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
#define REGNO_OK_FOR_BASE_P(regno) \
((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0))
#define REGNO_OK_FOR_INDEX_P(regno) \
((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0))
#define INT_REG_OK_FOR_INDEX_P(X,STRICT) \
((!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
#define INT_REG_OK_FOR_BASE_P(X,STRICT) \
((!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
#define REGISTER_TARGET_PRAGMAS() do { \
c_register_addr_space ("__ea", ADDR_SPACE_EA); \
targetm.resolve_overloaded_builtin = spu_resolve_overloaded_builtin; \
}while (0)
/* Frame Layout */
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#define STACK_POINTER_OFFSET 32
#define FIRST_PARM_OFFSET(FNDECL) (0)
#define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16)
#define RETURN_ADDR_RTX(COUNT,FP) (spu_return_addr (COUNT, FP))
/* Should this be defined? Would it simplify our implementation. */
/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(Pmode, LINK_REGISTER_REGNUM)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
#define ARG_POINTER_CFA_OFFSET(FNDECL) \
(crtl->args.pretend_args_size - STACK_POINTER_OFFSET)
/* Stack Checking */
/* We store the Available Stack Size in the second slot of the stack
register. We emit stack checking code during the prologue. */
#define STACK_CHECK_BUILTIN 1
/* Frame Registers, and other registers */
#define STACK_POINTER_REGNUM 1
/* Will be eliminated. */
#define FRAME_POINTER_REGNUM 128
/* This is not specified in any ABI, so could be set to anything. */
#define HARD_FRAME_POINTER_REGNUM 127
/* Will be eliminated. */
#define ARG_POINTER_REGNUM 129
#define STATIC_CHAIN_REGNUM 2
#define LINK_REGISTER_REGNUM 0
/* Used to keep track of instructions that have clobbered the hint
* buffer. Users can also specify it in inline asm. */
#define HBR_REGNUM 130
#define MAX_REGISTER_ARGS 72
#define FIRST_ARG_REGNUM 3
#define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + MAX_REGISTER_ARGS - 1)
#define MAX_REGISTER_RETURN 72
#define FIRST_RETURN_REGNUM 3
#define LAST_RETURN_REGNUM (FIRST_RETURN_REGNUM + MAX_REGISTER_RETURN - 1)
/* Elimination */
#define ELIMINABLE_REGS \
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = spu_initial_elimination_offset((FROM),(TO)))
/* Stack Arguments */
#define ACCUMULATE_OUTGOING_ARGS 1
#define REG_PARM_STACK_SPACE(FNDECL) 0
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
/* Register Arguments */
#define CUMULATIVE_ARGS int
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
((CUM) = 0)
#define PAD_VARARGS_DOWN 0
#define FUNCTION_ARG_REGNO_P(N) ((N) >= (FIRST_ARG_REGNUM) && (N) <= (LAST_ARG_REGNUM))
/* Scalar Return */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
(spu_function_value((VALTYPE),(FUNC)))
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RETURN_REGNUM)
#define FUNCTION_VALUE_REGNO_P(N) ((N) >= (FIRST_RETURN_REGNUM) && (N) <= (LAST_RETURN_REGNUM))
/* Machine-specific symbol_ref flags. */
#define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0)
/* Aggregate Return */
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Function Entry */
#define EXIT_IGNORE_STACK 0
#define EPILOGUE_USES(REGNO) ((REGNO)==1 ? 1 : 0)
/* Profiling */
#define FUNCTION_PROFILER(FILE, LABELNO) \
spu_function_profiler ((FILE), (LABELNO));
#define NO_PROFILE_COUNTERS 1
#define PROFILE_BEFORE_PROLOGUE 1
/* Trampolines */
#define TRAMPOLINE_SIZE (TARGET_LARGE_MEM ? 20 : 16)
#define TRAMPOLINE_ALIGNMENT 128
/* Addressing Modes */
#define CONSTANT_ADDRESS_P(X) spu_constant_address_p(X)
#define MAX_REGS_PER_ADDRESS 2
#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
do { \
rtx new_rtx = spu_legitimize_reload_address (AD, MODE, OPNUM, \
(int)(TYPE)); \
if (new_rtx) \
{ \
(AD) = new_rtx; \
goto WIN; \
} \
} while (0)
/* Costs */
#define BRANCH_COST(speed_p, predictable_p) spu_branch_cost
#define SLOW_BYTE_ACCESS 0
#define MOVE_RATIO(speed) ((speed)? 32 : 4)
#define NO_FUNCTION_CSE 1
/* Sections */
#define TEXT_SECTION_ASM_OP ".text"
#define DATA_SECTION_ASM_OP ".data"
#define JUMP_TABLES_IN_TEXT_SECTION 1
/* PIC */
#define PIC_OFFSET_TABLE_REGNUM 126
/* File Framework */
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
/* Uninitialized Data */
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
( fputs (".comm ", (FILE)), \
assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (ROUNDED)))
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
( fputs (".lcomm ", (FILE)), \
assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (ROUNDED)))
/* Label Output */
#define ASM_OUTPUT_LABEL(FILE,NAME) \
do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
asm_fprintf (FILE, "%U%s", default_strip_name_encoding (NAME))
#define ASM_OUTPUT_SYMBOL_REF(FILE, X) \
do \
{ \
tree decl; \
assemble_name (FILE, XSTR ((X), 0)); \
if ((decl = SYMBOL_REF_DECL ((X))) != 0 \
&& TREE_CODE (decl) == VAR_DECL \
&& TYPE_ADDR_SPACE (TREE_TYPE (decl))) \
fputs ("@ppu", FILE); \
} while (0)
/* Instruction Output */
#define REGISTER_NAMES \
{"$lr", "$sp", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", \
"$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39", "$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47", \
"$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55", "$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63", \
"$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71", "$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79", \
"$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87", "$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95", \
"$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103", "$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111", \
"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119", "$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127", \
"$vfp", "$vap", "hbr" \
}
#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
print_operand_address (FILE, ADDR)
#define LOCAL_LABEL_PREFIX "."
#define USER_LABEL_PREFIX ""
#define ASM_COMMENT_START "#"
/* Dispatch Tables */
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
fprintf (FILE, "\t.word .L%d\n", VALUE)
/* Alignment Output */
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
do { if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); } while (0)
/* Misc */
#define CASE_VECTOR_MODE SImode
#define MOVE_MAX 16
#define STORE_FLAG_VALUE -1
#define Pmode SImode
#define FUNCTION_MODE QImode
/* Address spaces. */
#define ADDR_SPACE_EA 1
/* Builtins. */
enum spu_builtin_type
{
B_INSN,
B_JUMP,
B_BISLED,
B_CALL,
B_HINT,
B_OVERLOAD,
B_INTERNAL
};
struct spu_builtin_description
{
int fcode;
int icode;
const char *name;
enum spu_builtin_type type;
/* The first element of parm is always the return type. The rest
are a zero terminated list of parameters. */
int parm[5];
};
extern struct spu_builtin_description spu_builtins[];

5255
gcc/config/spu/spu.md
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105
gcc/config/spu/spu.opt
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@ -1,105 +0,0 @@
; Options for the SPU port of the compiler
; Copyright (C) 2006-2019 Free Software Foundation, Inc.
; This file is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3 of the License, or (at your option)
; any later version.
; This file is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
mwarn-reloc
Target Report Mask(WARN_RELOC)
Emit warnings when run-time relocations are generated.
merror-reloc
Target Report Mask(ERROR_RELOC)
Emit errors when run-time relocations are generated.
mbranch-cost=
Target RejectNegative Joined UInteger Var(spu_branch_cost) Init(20)
Specify cost of branches (Default 20).
msafe-dma
Target Report RejectNegative Mask(SAFE_DMA)
Make sure loads and stores are not moved past DMA instructions.
munsafe-dma
Target Report RejectNegative InverseMask(SAFE_DMA)
volatile must be specified on any memory that is effected by DMA.
mdual-nops
Target Report Var(spu_dual_nops,10) Init(10)
Insert nops when it might improve performance by allowing dual issue (default).
mdual-nops=
Target RejectNegative Joined UInteger Var(spu_dual_nops)
Insert nops when it might improve performance by allowing dual issue (default).
mstdmain
Target Report Mask(STD_MAIN)
Use standard main function as entry for startup.
mbranch-hints
Target Report Mask(BRANCH_HINTS)
Generate branch hints for branches.
mhint-max-nops=
Target RejectNegative Joined UInteger Var(spu_max_nops) Init(2)
Maximum number of nops to insert for a hint (Default 2).
mhint-max-distance=
Target RejectNegative Joined Var(spu_max_distance_str)
Approximate maximum number of instructions to allow between a hint and its branch [125].
msmall-mem
Target Report RejectNegative InverseMask(LARGE_MEM)
Generate code for 18 bit addressing.
mlarge-mem
Target Report RejectNegative Mask(LARGE_MEM)
Generate code for 32 bit addressing.
mfixed-range=
Target RejectNegative Joined Var(spu_fixed_range_string)
Specify range of registers to make fixed.
msafe-hints
Target Report Mask(SAFE_HINTS)
Insert hbrp instructions after hinted branch targets to avoid the SPU hang issue.
march=
Target RejectNegative Joined Var(spu_arch_string)
Generate code for given CPU.
mtune=
Target RejectNegative Joined Var(spu_tune_string)
Schedule code for given CPU.
mea32
Target Report RejectNegative Var(spu_ea_model,32) Init(32)
Access variables in 32-bit PPU objects (default).
mea64
Target Report RejectNegative Var(spu_ea_model,64)
Access variables in 64-bit PPU objects.
maddress-space-conversion
Target Report Mask(ADDRESS_SPACE_CONVERSION)
Allow conversions between __ea and generic pointers (default).
mcache-size=
Target Report RejectNegative Joined UInteger
Size (in KB) of software data cache.
matomic-updates
Target Report
Atomically write back software data cache lines (default).

39
gcc/config/spu/spu_cache.h
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@ -1,39 +0,0 @@
/* Copyright (C) 2008-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _SPU_CACHE_H
#define _SPU_CACHE_H
void *__cache_fetch_dirty (__ea void *ea, int n_bytes_dirty);
void *__cache_fetch (__ea void *ea);
void __cache_evict (__ea void *ea);
void __cache_flush (void);
void __cache_touch (__ea void *ea);
#define cache_fetch_dirty(_ea, _n_bytes_dirty) \
__cache_fetch_dirty(_ea, _n_bytes_dirty)
#define cache_fetch(_ea) __cache_fetch(_ea)
#define cache_touch(_ea) __cache_touch(_ea)
#define cache_evict(_ea) __cache_evict(_ea)
#define cache_flush() __cache_flush()
#endif

421
gcc/config/spu/spu_internals.h
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/* Definitions of Synergistic Processing Unit (SPU). */
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _SPU_INTERNALS_H
#define _SPU_INTERNALS_H
/* For a typical GCC implementation, the vector keyword is defined here
* as a macro. If this macro conflicts with user code the user needs to
* undefine it. An extended GCC implementation may implement this
* keyword differently, such that it never conflicts, and will define
* the macro __VECTOR_KEYWORD_SUPPORTED__. */
#ifndef __VECTOR_KEYWORD_SUPPORTED__
#define vector __vector
#endif
/* The spu specific instruction macros, si_*(), correspond 1-1 with
* SPU instructions in the ISA. The arguments are the same with the
* following exceptions:
* - any instruction which both reads and writes rt will have an
* extra parameter in the macro.
* - instructions which append zero to the immediate field assume
* the value given in a macro already has the zeroes appended.
* - integer/float convert functions expect a value from 0 to 127,
* i.e., the bias is added by the compiler.
*
* Parameters named 'imm' accept an integer literal.
* Parameters named 'r[abcdt]' accept a qword argument.
* Parameters named 'scalar' accept a scalar argument.
*/
#define qword __vector signed char
#define si_lqd(ra,imm) __builtin_si_lqd(ra,imm)
#define si_lqx(ra,rb) __builtin_si_lqx(ra,rb)
#define si_lqa(imm) __builtin_si_lqa(imm)
#define si_lqr(imm) __builtin_si_lqr(imm)
#define si_stqd(rt,ra,imm) __builtin_si_stqd(rt,ra,imm)
#define si_stqx(rt,ra,rb) __builtin_si_stqx(rt,ra,rb)
#define si_stqa(rt,imm) __builtin_si_stqa(rt,imm)
#define si_stqr(rt,imm) __builtin_si_stqr(rt,imm)
#define si_cbd(ra,imm) __builtin_si_cbd(ra,imm)
#define si_cbx(ra,rb) __builtin_si_cbx(ra,rb)
#define si_chd(ra,imm) __builtin_si_chd(ra,imm)
#define si_chx(ra,rb) __builtin_si_chx(ra,rb)
#define si_cwd(ra,imm) __builtin_si_cwd(ra,imm)
#define si_cwx(ra,rb) __builtin_si_cwx(ra,rb)
#define si_cdd(ra,imm) __builtin_si_cdd(ra,imm)
#define si_cdx(ra,rb) __builtin_si_cdx(ra,rb)
#define si_ilh(imm) __builtin_si_ilh(imm)
#define si_ilhu(imm) __builtin_si_ilhu(imm)
#define si_il(imm) __builtin_si_il(imm)
#define si_ila(imm) __builtin_si_ila(imm)
#define si_iohl(ra,imm) __builtin_si_iohl(ra,imm)
#define si_fsmbi(imm) __builtin_si_fsmbi(imm)
#define si_ah(ra,rb) __builtin_si_ah(ra,rb)
#define si_ahi(ra,imm) __builtin_si_ahi(ra,imm)
#define si_a(ra,rb) __builtin_si_a(ra,rb)
#define si_ai(ra,imm) __builtin_si_ai(ra,imm)
#define si_addx(ra,rb,rt) __builtin_si_addx(ra,rb,rt)
#define si_cg(ra,rb) __builtin_si_cg(ra,rb)
#define si_cgx(ra,rb,rt) __builtin_si_cgx(ra,rb,rt)
#define si_sfh(ra,rb) __builtin_si_sfh(ra,rb)
#define si_sfhi(imm,ra) __builtin_si_sfhi(imm,ra)
#define si_sf(ra,rb) __builtin_si_sf(ra,rb)
#define si_sfi(ra,imm) __builtin_si_sfi(ra,imm)
#define si_sfx(ra,rb,rt) __builtin_si_sfx(ra,rb,rt)
#define si_bg(ra,rb) __builtin_si_bg(ra,rb)
#define si_bgx(ra,rb,rt) __builtin_si_bgx(ra,rb,rt)
#define si_mpy(ra,rb) __builtin_si_mpy(ra,rb)
#define si_mpyu(ra,rb) __builtin_si_mpyu(ra,rb)
#define si_mpyi(ra,imm) __builtin_si_mpyi(ra,imm)
#define si_mpyui(ra,imm) __builtin_si_mpyui(ra,imm)
#define si_mpya(ra,rb,rc) __builtin_si_mpya(ra,rb,rc)
#define si_mpyh(ra,rb) __builtin_si_mpyh(ra,rb)
#define si_mpys(ra,rb) __builtin_si_mpys(ra,rb)
#define si_mpyhh(ra,rb) __builtin_si_mpyhh(ra,rb)
#define si_mpyhhu(ra,rb) __builtin_si_mpyhhu(ra,rb)
#define si_mpyhha(ra,rb,rc) __builtin_si_mpyhha(ra,rb,rc)
#define si_mpyhhau(ra,rb,rc) __builtin_si_mpyhhau(ra,rb,rc)
#define si_clz(ra) __builtin_si_clz(ra)
#define si_cntb(ra) __builtin_si_cntb(ra)
#define si_fsmb(ra) __builtin_si_fsmb(ra)
#define si_fsmh(ra) __builtin_si_fsmh(ra)
#define si_fsm(ra) __builtin_si_fsm(ra)
#define si_gbb(ra) __builtin_si_gbb(ra)
#define si_gbh(ra) __builtin_si_gbh(ra)
#define si_gb(ra) __builtin_si_gb(ra)
#define si_avgb(ra,rb) __builtin_si_avgb(ra,rb)
#define si_absdb(ra,rb) __builtin_si_absdb(ra,rb)
#define si_sumb(ra,rb) __builtin_si_sumb(ra,rb)
#define si_xsbh(ra) __builtin_si_xsbh(ra)
#define si_xshw(ra) __builtin_si_xshw(ra)
#define si_xswd(ra) __builtin_si_xswd(ra)
#define si_and(ra,rb) __builtin_si_and(ra,rb)
#define si_andc(ra,rb) __builtin_si_andc(ra,rb)
#define si_andbi(ra,imm) __builtin_si_andbi(ra,imm)
#define si_andhi(ra,imm) __builtin_si_andhi(ra,imm)
#define si_andi(ra,imm) __builtin_si_andi(ra,imm)
#define si_or(ra,rb) __builtin_si_or(ra,rb)
#define si_orc(ra,rb) __builtin_si_orc(ra,rb)
#define si_orbi(ra,imm) __builtin_si_orbi(ra,imm)
#define si_orhi(ra,imm) __builtin_si_orhi(ra,imm)
#define si_ori(ra,imm) __builtin_si_ori(ra,imm)
#define si_orx(ra) __builtin_si_orx(ra)
#define si_xor(ra,rb) __builtin_si_xor(ra,rb)
#define si_xorbi(ra,imm) __builtin_si_xorbi(ra,imm)
#define si_xorhi(ra,imm) __builtin_si_xorhi(ra,imm)
#define si_xori(ra,imm) __builtin_si_xori(ra,imm)
#define si_nand(ra,rb) __builtin_si_nand(ra,rb)
#define si_nor(ra,rb) __builtin_si_nor(ra,rb)
#define si_eqv(ra,rb) __builtin_si_eqv(ra,rb)
#define si_selb(ra,rb,rc) __builtin_si_selb(ra,rb,rc)
#define si_shufb(ra,rb,rc) __builtin_si_shufb(ra,rb,rc)
#define si_shlh(ra,rb) __builtin_si_shlh(ra,rb)
#define si_shlhi(ra,imm) __builtin_si_shlhi(ra,imm)
#define si_shl(ra,rb) __builtin_si_shl(ra,rb)
#define si_shli(ra,imm) __builtin_si_shli(ra,imm)
#define si_shlqbi(ra,rb) __builtin_si_shlqbi(ra,rb)
#define si_shlqbii(ra,imm) __builtin_si_shlqbii(ra,imm)
#define si_shlqby(ra,rb) __builtin_si_shlqby(ra,rb)
#define si_shlqbyi(ra,imm) __builtin_si_shlqbyi(ra,imm)
#define si_shlqbybi(ra,rb) __builtin_si_shlqbybi(ra,rb)
#define si_roth(ra,rb) __builtin_si_roth(ra,rb)
#define si_rothi(ra,imm) __builtin_si_rothi(ra,imm)
#define si_rot(ra,rb) __builtin_si_rot(ra,rb)
#define si_roti(ra,imm) __builtin_si_roti(ra,imm)
#define si_rotqby(ra,rb) __builtin_si_rotqby(ra,rb)
#define si_rotqbyi(ra,imm) __builtin_si_rotqbyi(ra,imm)
#define si_rotqbybi(ra,rb) __builtin_si_rotqbybi(ra,rb)
#define si_rotqbi(ra,rb) __builtin_si_rotqbi(ra,rb)
#define si_rotqbii(ra,imm) __builtin_si_rotqbii(ra,imm)
#define si_rothm(ra,rb) __builtin_si_rothm(ra,rb)
#define si_rothmi(ra,imm) __builtin_si_rothmi(ra,imm)
#define si_rotm(ra,rb) __builtin_si_rotm(ra,rb)
#define si_rotmi(ra,imm) __builtin_si_rotmi(ra,imm)
#define si_rotqmby(ra,rb) __builtin_si_rotqmby(ra,rb)
#define si_rotqmbyi(ra,imm) __builtin_si_rotqmbyi(ra,imm)
#define si_rotqmbi(ra,rb) __builtin_si_rotqmbi(ra,rb)
#define si_rotqmbii(ra,imm) __builtin_si_rotqmbii(ra,imm)
#define si_rotqmbybi(ra,rb) __builtin_si_rotqmbybi(ra,rb)
#define si_rotmah(ra,rb) __builtin_si_rotmah(ra,rb)
#define si_rotmahi(ra,imm) __builtin_si_rotmahi(ra,imm)
#define si_rotma(ra,rb) __builtin_si_rotma(ra,rb)
#define si_rotmai(ra,imm) __builtin_si_rotmai(ra,imm)
#define si_heq(ra,rb) __builtin_si_heq(ra,rb)
#define si_heqi(ra,imm) __builtin_si_heqi(ra,imm)
#define si_hgt(ra,rb) __builtin_si_hgt(ra,rb)
#define si_hgti(ra,imm) __builtin_si_hgti(ra,imm)
#define si_hlgt(ra,rb) __builtin_si_hlgt(ra,rb)
#define si_hlgti(ra,imm) __builtin_si_hlgti(ra,imm)
#define si_ceqb(ra,rb) __builtin_si_ceqb(ra,rb)
#define si_ceqbi(ra,imm) __builtin_si_ceqbi(ra,imm)
#define si_ceqh(ra,rb) __builtin_si_ceqh(ra,rb)
#define si_ceqhi(ra,imm) __builtin_si_ceqhi(ra,imm)
#define si_ceq(ra,rb) __builtin_si_ceq(ra,rb)
#define si_ceqi(ra,imm) __builtin_si_ceqi(ra,imm)
#define si_cgtb(ra,rb) __builtin_si_cgtb(ra,rb)
#define si_cgtbi(ra,imm) __builtin_si_cgtbi(ra,imm)
#define si_cgth(ra,rb) __builtin_si_cgth(ra,rb)
#define si_cgthi(ra,imm) __builtin_si_cgthi(ra,imm)
#define si_cgt(ra,rb) __builtin_si_cgt(ra,rb)
#define si_cgti(ra,imm) __builtin_si_cgti(ra,imm)
#define si_clgtb(ra,rb) __builtin_si_clgtb(ra,rb)
#define si_clgtbi(ra,imm) __builtin_si_clgtbi(ra,imm)
#define si_clgth(ra,rb) __builtin_si_clgth(ra,rb)
#define si_clgthi(ra,imm) __builtin_si_clgthi(ra,imm)
#define si_clgt(ra,rb) __builtin_si_clgt(ra,rb)
#define si_clgti(ra,imm) __builtin_si_clgti(ra,imm)
#define si_bisled(ra) __builtin_si_bisled(ra,0)
#define si_bisledd(ra) __builtin_si_bisledd(ra,0)
#define si_bislede(ra) __builtin_si_bislede(ra,0)
#define si_fa(ra,rb) __builtin_si_fa(ra,rb)
#define si_dfa(ra,rb) __builtin_si_dfa(ra,rb)
#define si_fs(ra,rb) __builtin_si_fs(ra,rb)
#define si_dfs(ra,rb) __builtin_si_dfs(ra,rb)
#define si_fm(ra,rb) __builtin_si_fm(ra,rb)
#define si_dfm(ra,rb) __builtin_si_dfm(ra,rb)
#define si_fma(ra,rb,rc) __builtin_si_fma(ra,rb,rc)
#define si_dfma(ra,rb,rc) __builtin_si_dfma(ra,rb,rc)
#define si_dfnma(ra,rb,rc) __builtin_si_dfnma(ra,rb,rc)
#define si_fnms(ra,rb,rc) __builtin_si_fnms(ra,rb,rc)
#define si_dfnms(ra,rb,rc) __builtin_si_dfnms(ra,rb,rc)
#define si_fms(ra,rb,rc) __builtin_si_fms(ra,rb,rc)
#define si_dfms(ra,rb,rc) __builtin_si_dfms(ra,rb,rc)
#define si_frest(ra) __builtin_si_frest(ra)
#define si_frsqest(ra) __builtin_si_frsqest(ra)
#define si_fi(ra,rb) __builtin_si_fi(ra,rb)
#define si_csflt(ra,imm) __builtin_si_csflt(ra,imm)
#define si_cflts(ra,imm) __builtin_si_cflts(ra,imm)
#define si_cuflt(ra,imm) __builtin_si_cuflt(ra,imm)
#define si_cfltu(ra,imm) __builtin_si_cfltu(ra,imm)
#define si_frds(ra) __builtin_si_frds(ra)
#define si_fesd(ra) __builtin_si_fesd(ra)
#define si_fceq(ra,rb) __builtin_si_fceq(ra,rb)
#define si_fcmeq(ra,rb) __builtin_si_fcmeq(ra,rb)
#define si_fcgt(ra,rb) __builtin_si_fcgt(ra,rb)
#define si_fcmgt(ra,rb) __builtin_si_fcmgt(ra,rb)
#define si_stop(imm) __builtin_si_stop(imm)
#define si_stopd(ra,rb,rc) __builtin_si_stopd(ra,rb,rc)
#define si_lnop() __builtin_si_lnop()
#define si_nop() __builtin_si_nop()
#define si_sync() __builtin_si_sync()
#define si_syncc() __builtin_si_syncc()
#define si_dsync() __builtin_si_dsync()
#define si_mfspr(imm) __builtin_si_mfspr(imm)
#define si_mtspr(imm,ra) __builtin_si_mtspr(imm,ra)
#define si_fscrrd() __builtin_si_fscrrd()
#define si_fscrwr(ra) __builtin_si_fscrwr(ra)
#define si_rdch(imm) __builtin_si_rdch(imm)
#define si_rchcnt(imm) __builtin_si_rchcnt(imm)
#define si_wrch(imm,ra) __builtin_si_wrch(imm,ra)
/* celledp only instructions */
#ifdef __SPU_EDP__
#define si_dfceq(ra,rb) __builtin_si_dfceq(ra,rb)
#define si_dfcmeq(ra,rb) __builtin_si_dfcmeq(ra,rb)
#define si_dfcgt(ra,rb) __builtin_si_dfcgt(ra,rb)
#define si_dfcmgt(ra,rb) __builtin_si_dfcmgt(ra,rb)
#define si_dftsv(ra,imm) __builtin_si_dftsv(ra,imm)
#endif /* __SPU_EDP__ */
#define si_from_char(scalar) __builtin_si_from_char(scalar)
#define si_from_uchar(scalar) __builtin_si_from_uchar(scalar)
#define si_from_short(scalar) __builtin_si_from_short(scalar)
#define si_from_ushort(scalar) __builtin_si_from_ushort(scalar)
#define si_from_int(scalar) __builtin_si_from_int(scalar)
#define si_from_uint(scalar) __builtin_si_from_uint(scalar)
#define si_from_llong(scalar) __builtin_si_from_long(scalar)
#define si_from_ullong(scalar) __builtin_si_from_ulong(scalar)
#define si_from_float(scalar) __builtin_si_from_float(scalar)
#define si_from_double(scalar) __builtin_si_from_double(scalar)
#define si_from_ptr(scalar) __builtin_si_from_ptr(scalar)
#define si_to_char(ra) __builtin_si_to_char(ra)
#define si_to_uchar(ra) __builtin_si_to_uchar(ra)
#define si_to_short(ra) __builtin_si_to_short(ra)
#define si_to_ushort(ra) __builtin_si_to_ushort(ra)
#define si_to_int(ra) __builtin_si_to_int(ra)
#define si_to_uint(ra) __builtin_si_to_uint(ra)
#define si_to_llong(ra) __builtin_si_to_long(ra)
#define si_to_ullong(ra) __builtin_si_to_ulong(ra)
#define si_to_float(ra) __builtin_si_to_float(ra)
#define si_to_double(ra) __builtin_si_to_double(ra)
#define si_to_ptr(ra) __builtin_si_to_ptr(ra)
#define __align_hint(ptr,base,offset) __builtin_spu_align_hint(ptr,base,offset)
/* generic spu_* intrinsics */
#define spu_splats(scalar) __builtin_spu_splats(scalar)
#define spu_convtf(ra,imm) __builtin_spu_convtf(ra,imm)
#define spu_convts(ra,imm) __builtin_spu_convts(ra,imm)
#define spu_convtu(ra,imm) __builtin_spu_convtu(ra,imm)
#define spu_extend(ra) __builtin_spu_extend(ra)
#define spu_roundtf(ra) __builtin_spu_roundtf(ra)
#define spu_add(ra,rb) __builtin_spu_add(ra,rb)
#define spu_addx(ra,rb,rt) __builtin_spu_addx(ra,rb,rt)
#define spu_genc(ra,rb) __builtin_spu_genc(ra,rb)
#define spu_gencx(ra,rb,rt) __builtin_spu_gencx(ra,rb,rt)
#define spu_madd(ra,rb,rc) __builtin_spu_madd(ra,rb,rc)
#define spu_nmadd(ra,rb,rc) __builtin_spu_nmadd(ra,rb,rc)
#define spu_mhhadd(ra,rb,rc) __builtin_spu_mhhadd(ra,rb,rc)
#define spu_msub(ra,rb,rc) __builtin_spu_msub(ra,rb,rc)
#define spu_mul(ra,rb) __builtin_spu_mul(ra,rb)
#define spu_mulh(ra,rb) __builtin_spu_mulh(ra,rb)
#define spu_mule(ra,rb) __builtin_spu_mule(ra,rb)
#define spu_mulo(ra,rb) __builtin_spu_mulo(ra,rb)
#define spu_mulsr(ra,rb) __builtin_spu_mulsr(ra,rb)
#define spu_nmsub(ra,rb,rc) __builtin_spu_nmsub(ra,rb,rc)
#define spu_sub(ra,rb) __builtin_spu_sub(ra,rb)
#define spu_subx(ra,rb,rt) __builtin_spu_subx(ra,rb,rt)
#define spu_genb(ra,rb) __builtin_spu_genb(ra,rb)
#define spu_genbx(ra,rb,rt) __builtin_spu_genbx(ra,rb,rt)
#define spu_absd(ra,rb) __builtin_spu_absd(ra,rb)
#define spu_avg(ra,rb) __builtin_spu_avg(ra,rb)
#define spu_sumb(ra,rb) __builtin_spu_sumb(ra,rb)
#define spu_bisled(ra) __builtin_spu_bisled(ra, 0)
#define spu_bisled_d(ra) __builtin_spu_bisled_d(ra, 0)
#define spu_bisled_e(ra) __builtin_spu_bisled_e(ra, 0)
#define spu_cmpabseq(ra,rb) __builtin_spu_cmpabseq(ra,rb)
#define spu_cmpabsgt(ra,rb) __builtin_spu_cmpabsgt(ra,rb)
#define spu_cmpeq(ra,rb) __builtin_spu_cmpeq(ra,rb)
#define spu_cmpgt(ra,rb) __builtin_spu_cmpgt(ra,rb)
#define spu_testsv(ra,imm) __builtin_spu_testsv(ra,imm)
#define spu_hcmpeq(ra,rb) __builtin_spu_hcmpeq(ra,rb)
#define spu_hcmpgt(ra,rb) __builtin_spu_hcmpgt(ra,rb)
#define spu_cntb(ra) __builtin_spu_cntb(ra)
#define spu_cntlz(ra) __builtin_spu_cntlz(ra)
#define spu_gather(ra) __builtin_spu_gather(ra)
#define spu_maskb(ra) __builtin_spu_maskb(ra)
#define spu_maskh(ra) __builtin_spu_maskh(ra)
#define spu_maskw(ra) __builtin_spu_maskw(ra)
#define spu_sel(ra,rb,rc) __builtin_spu_sel(ra,rb,rc)
#define spu_shuffle(ra,rb,rc) __builtin_spu_shuffle(ra,rb,rc)
#define spu_and(ra,rb) __builtin_spu_and(ra,rb)
#define spu_andc(ra,rb) __builtin_spu_andc(ra,rb)
#define spu_eqv(ra,rb) __builtin_spu_eqv(ra,rb)
#define spu_nand(ra,rb) __builtin_spu_nand(ra,rb)
#define spu_nor(ra,rb) __builtin_spu_nor(ra,rb)
#define spu_or(ra,rb) __builtin_spu_or(ra,rb)
#define spu_orc(ra,rb) __builtin_spu_orc(ra,rb)
#define spu_orx(ra) __builtin_spu_orx(ra)
#define spu_xor(ra,rb) __builtin_spu_xor(ra,rb)
#define spu_rl(ra,rb) __builtin_spu_rl(ra,rb)
#define spu_rlqw(ra,count) __builtin_spu_rlqw(ra,count)
#define spu_rlqwbyte(ra,count) __builtin_spu_rlqwbyte(ra,count)
#define spu_rlqwbytebc(ra,count) __builtin_spu_rlqwbytebc(ra,count)
#define spu_rlmask(ra,rb) __builtin_spu_rlmask(ra,rb)
#define spu_rlmaska(ra,rb) __builtin_spu_rlmaska(ra,rb)
#define spu_rlmaskqw(ra,rb) __builtin_spu_rlmaskqw(ra,rb)
#define spu_rlmaskqwbyte(ra,rb) __builtin_spu_rlmaskqwbyte(ra,rb)
#define spu_rlmaskqwbytebc(ra,rb) __builtin_spu_rlmaskqwbytebc(ra,rb)
#define spu_sl(ra,rb) __builtin_spu_sl(ra,rb)
#define spu_slqw(ra,rb) __builtin_spu_slqw(ra,rb)
#define spu_slqwbyte(ra,rb) __builtin_spu_slqwbyte(ra,rb)
#define spu_slqwbytebc(ra,rb) __builtin_spu_slqwbytebc(ra,rb)
#define spu_sr(ra,rb) __builtin_spu_sr(ra,rb)
#define spu_sra(ra,rb) __builtin_spu_sra(ra,rb)
#define spu_srqw(ra,rb) __builtin_spu_srqw(ra,rb)
#define spu_srqwbyte(ra,rb) __builtin_spu_srqwbyte(ra,rb)
#define spu_srqwbytebc(ra,rb) __builtin_spu_srqwbytebc(ra,rb)
#define spu_extract(ra,pos) __builtin_spu_extract(ra,pos)
#define spu_insert(scalar,ra,pos) __builtin_spu_insert(scalar,ra,pos)
#define spu_promote(scalar,pos) __builtin_spu_promote(scalar,pos)
#ifdef __cplusplus
extern "C" {
#endif
/* The type checking for some of these won't be accurate but they need
* to be defines because of the immediate values. */
#define spu_idisable() __builtin_spu_idisable()
#define spu_ienable() __builtin_spu_ienable()
#define spu_mfspr(imm) si_to_uint(si_mfspr((imm)))
#define spu_mtspr(imm, ra) si_mtspr((imm),si_from_uint (ra))
#define spu_mffpscr() ((vec_uint4)si_fscrrd())
#define spu_mtfpscr(a) si_fscrwr((qword)a)
#define spu_dsync() si_dsync()
#define spu_stop(imm) si_stop(imm)
#define spu_sync() si_sync()
#define spu_sync_c() si_syncc()
#define spu_readch(imm) si_to_uint(si_rdch((imm)))
#define spu_readchqw(imm) ((vec_uint4)si_rdch((imm)))
#define spu_readchcnt(imm) si_to_uint(si_rchcnt((imm)))
#define spu_writech(imm, ra) si_wrch((imm), si_from_uint(ra))
#define spu_writechqw(imm, ra) si_wrch((imm), (qword)(ra))
/* The following functions are static and always_inline to make sure
* they don't show up in object files which they aren't used in. */
static __inline__ vec_float4 spu_re (vec_float4 ra) __attribute__((__always_inline__));
static __inline__ vec_float4 spu_rsqrte (vec_float4 ra) __attribute__((__always_inline__));
static __inline__ vec_float4
spu_re (vec_float4 ra)
{
return (vec_float4) si_fi ((qword) (ra), si_frest ((qword) (ra)));
}
static __inline__ vec_float4
spu_rsqrte (vec_float4 ra)
{
return (vec_float4) si_fi ((qword) (ra), si_frsqest ((qword) (ra)));
}
/* composite intrinsics */
static __inline__ void spu_mfcdma32(volatile void *ls, unsigned int ea, unsigned int size, unsigned int tagid, unsigned int cmd) __attribute__((__always_inline__));
static __inline__ void spu_mfcdma64(volatile void *ls, unsigned int eahi, unsigned int ealow, unsigned int size, unsigned int tagid, unsigned int cmd) __attribute__((__always_inline__));
static __inline__ unsigned int spu_mfcstat(unsigned int type) __attribute__((__always_inline__));
static __inline__ void
spu_mfcdma32(volatile void *ls, unsigned int ea, unsigned int size, unsigned int tagid, unsigned int cmd)
{
si_wrch(MFC_LSA,si_from_ptr(ls));
si_wrch(MFC_EAL,si_from_uint(ea));
si_wrch(MFC_Size,si_from_uint(size));
si_wrch(MFC_TagID,si_from_uint(tagid));
si_wrch(MFC_Cmd,si_from_uint(cmd));
}
static __inline__ void
spu_mfcdma64(volatile void *ls, unsigned int eahi, unsigned int ealow, unsigned int size, unsigned int tagid, unsigned int cmd)
{
si_wrch(MFC_LSA,si_from_ptr(ls));
si_wrch(MFC_EAH,si_from_uint(eahi));
si_wrch(MFC_EAL,si_from_uint(ealow));
si_wrch(MFC_Size,si_from_uint(size));
si_wrch(MFC_TagID,si_from_uint(tagid));
si_wrch(MFC_Cmd,si_from_uint(cmd));
}
static __inline__ unsigned int
spu_mfcstat(unsigned int type)
{
si_wrch(MFC_WrTagUpdate,si_from_uint(type));
return si_to_uint(si_rdch(MFC_RdTagStat));
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* SPUINTRIN_H */

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/* Definitions of Synergistic Processing Unit (SPU). */
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _SPU_INTRINSICS_H
#define _SPU_INTRINSICS_H
#define vec_uchar16 __vector unsigned char
#define vec_char16 __vector signed char
#define vec_ushort8 __vector unsigned short
#define vec_short8 __vector signed short
#define vec_uint4 __vector unsigned int
#define vec_int4 __vector signed int
#define vec_ullong2 __vector unsigned long long
#define vec_llong2 __vector signed long long
#define vec_float4 __vector float
#define vec_double2 __vector double
/* SPU Channel Defines
*/
#define SPU_RdEventStat 0
#define SPU_WrEventMask 1
#define SPU_WrEventAck 2
#define SPU_RdSigNotify1 3
#define SPU_RdSigNotify2 4
#define SPU_WrDec 7
#define SPU_RdDec 8
#define SPU_RdEventMask 11
#define SPU_RdMachStat 13
#define SPU_WrSRR0 14
#define SPU_RdSRR0 15
#define SPU_WrOutMbox 28
#define SPU_RdInMbox 29
#define SPU_WrOutIntrMbox 30
/* MFC Channel Defines.
*/
#define MFC_WrMSSyncReq 9
#define MFC_RdTagMask 12
#define MFC_LSA 16
#define MFC_EAH 17
#define MFC_EAL 18
#define MFC_Size 19
#define MFC_TagID 20
#define MFC_Cmd 21
#define MFC_WrTagMask 22
#define MFC_WrTagUpdate 23
#define MFC_RdTagStat 24
#define MFC_RdListStallStat 25
#define MFC_WrListStallAck 26
#define MFC_RdAtomicStat 27
/* Bit flag mnemonics for test special value.
*/
#define SPU_SV_NEG_DENORM 0x01 /* negative denormalized number */
#define SPU_SV_POS_DENORM 0x02 /* positive denormalized number */
#define SPU_SV_NEG_ZERO 0x04 /* negative zero */
#define SPU_SV_POS_ZERO 0x08 /* positive zero */
#define SPU_SV_NEG_INFINITY 0x10 /* negative infinity */
#define SPU_SV_POS_INFINITY 0x20 /* positive infinity */
#define SPU_SV_NAN 0x40 /* not a number */
#include <spu_internals.h>
#endif /* _SPU_INTRINSICS_H */

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/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef __SPU_MFCIO_H__
#define __SPU_MFCIO_H__ 1
#include <spu_intrinsics.h>
#ifdef __IN_LIBGCC2
typedef unsigned long long uint64_t;
#else
#include <stdint.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************/
/* DMA list element structure*/
/****************************************************************/
#ifdef __GNUC__
__extension__
#endif
typedef struct mfc_list_element {
uint64_t notify : 1; /** Stall-and-notify bit */
uint64_t reserved : 16;
uint64_t size : 15; /** Transfer size */
uint64_t eal : 32; /** Lower word of effective address */
} mfc_list_element_t;
/****************************************************************/
/* DMA max/min size definitions. */
/****************************************************************/
#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
#define MFC_MIN_DMA_LIST_ELEMENTS 1
#define MFC_MAX_DMA_LIST_ELEMENTS 2048
#define MFC_MIN_DMA_LIST_SIZE (MFC_MIN_DMA_LIST_ELEMENTS << 3) /* 8 bytes */
#define MFC_MAX_DMA_LIST_SIZE (MFC_MAX_DMA_LIST_ELEMENTS << 3) /* 16K bytes */
/****************************************************************/
/* MFC DMA command modifiers to identify classes of operations. */
/****************************************************************/
/* Note: These commands modifier may be used in conjunction with the base
command types (i.e. MFC_PUT_CMD, MFC_GET_CMD, and MFC_SNDSIG_CMD)
to construct the various command permutations. */
#define MFC_BARRIER_ENABLE 0x0001
#define MFC_FENCE_ENABLE 0x0002
#define MFC_LIST_ENABLE 0x0004
#define MFC_RESULT_ENABLE 0x0010
/****************************************************************/
/* MFC DMA Put Commands */
/****************************************************************/
#define MFC_PUT_CMD 0x0020
#define MFC_PUTB_CMD (MFC_PUT_CMD | MFC_BARRIER_ENABLE)
#define MFC_PUTF_CMD (MFC_PUT_CMD | MFC_FENCE_ENABLE)
#define MFC_PUTL_CMD (MFC_PUT_CMD | MFC_LIST_ENABLE)
#define MFC_PUTLB_CMD (MFC_PUTL_CMD | MFC_BARRIER_ENABLE)
#define MFC_PUTLF_CMD (MFC_PUTL_CMD | MFC_FENCE_ENABLE)
#define MFC_PUTR_CMD (MFC_PUT_CMD | MFC_RESULT_ENABLE)
#define MFC_PUTRB_CMD (MFC_PUTR_CMD | MFC_BARRIER_ENABLE)
#define MFC_PUTRF_CMD (MFC_PUTR_CMD | MFC_FENCE_ENABLE)
#define MFC_PUTRL_CMD (MFC_PUTR_CMD | MFC_LIST_ENABLE)
#define MFC_PUTRLB_CMD (MFC_PUTRL_CMD | MFC_BARRIER_ENABLE)
#define MFC_PUTRLF_CMD (MFC_PUTRL_CMD | MFC_FENCE_ENABLE)
/****************************************************************/
/* MFC DMA Get Commands */
/****************************************************************/
#define MFC_GET_CMD 0x0040
#define MFC_GETB_CMD (MFC_GET_CMD | MFC_BARRIER_ENABLE)
#define MFC_GETF_CMD (MFC_GET_CMD | MFC_FENCE_ENABLE)
#define MFC_GETL_CMD (MFC_GET_CMD | MFC_LIST_ENABLE)
#define MFC_GETLB_CMD (MFC_GETL_CMD | MFC_BARRIER_ENABLE)
#define MFC_GETLF_CMD (MFC_GETL_CMD | MFC_FENCE_ENABLE)
/****************************************************************/
/* MFC Synchronization Commands */
/****************************************************************/
#define MFC_SNDSIG_CMD 0x00A0
#define MFC_SNDSIGB_CMD (MFC_SNDSIG_CMD | MFC_BARRIER_ENABLE)
#define MFC_SNDSIGF_CMD (MFC_SNDSIG_CMD | MFC_FENCE_ENABLE)
#define MFC_BARRIER_CMD 0x00C0
#define MFC_EIEIO_CMD 0x00C8
#define MFC_SYNC_CMD 0x00CC
/****************************************************************/
/* MFC Atomic Commands */
/****************************************************************/
#define MFC_GETLLAR_CMD 0x00D0
#define MFC_PUTLLC_CMD 0x00B4
#define MFC_PUTLLUC_CMD 0x00B0
#define MFC_PUTQLLUC_CMD 0x00B8
/****************************************************************/
/* MFC SL1 Storage Control Commands */
/****************************************************************/
#define MFC_SDCRT_CMD 0x0080
#define MFC_SDCRTST_CMD 0x0081
#define MFC_SDCRZ_CMD 0x0089
#define MFC_SDCRST_CMD 0x008D
#define MFC_SDCRF_CMD 0x008F
/****************************************************************/
/* Channel Defines */
/****************************************************************/
/* Events Defines for channels
* 0 (SPU_RdEventStat),
* 1 (SPU_WrEventMask), and
* 2 (SPU_WrEventAck).
*/
#define MFC_TAG_STATUS_UPDATE_EVENT 0x00000001
#define MFC_LIST_STALL_NOTIFY_EVENT 0x00000002
#define MFC_COMMAND_QUEUE_AVAILABLE_EVENT 0x00000008
#define MFC_IN_MBOX_AVAILABLE_EVENT 0x00000010
#define MFC_DECREMENTER_EVENT 0x00000020
#define MFC_OUT_INTR_MBOX_AVAILABLE_EVENT 0x00000040
#define MFC_OUT_MBOX_AVAILABLE_EVENT 0x00000080
#define MFC_SIGNAL_NOTIFY_2_EVENT 0x00000100
#define MFC_SIGNAL_NOTIFY_1_EVENT 0x00000200
#define MFC_LLR_LOST_EVENT 0x00000400
#define MFC_PRIV_ATTN_EVENT 0x00000800
#define MFC_MULTI_SRC_SYNC_EVENT 0x00001000
/* Tag Status Update defines for channel 23 (MFC_WrTagUpdate) */
#define MFC_TAG_UPDATE_IMMEDIATE 0x0
#define MFC_TAG_UPDATE_ANY 0x1
#define MFC_TAG_UPDATE_ALL 0x2
/* Atomic Command Status defines for channel 27 (MFC_RdAtomicStat) */
#define MFC_PUTLLC_STATUS 0x00000001
#define MFC_PUTLLUC_STATUS 0x00000002
#define MFC_GETLLAR_STATUS 0x00000004
/****************************************************************/
/* Definitions for constructing a 32-bit command word */
/* including the transfer and replacement class id and the */
/* command opcode. */
/****************************************************************/
#define MFC_CMD_WORD(_tid, _rid, _cmd) (((_tid)<<24)|((_rid)<<16)|(_cmd))
/* Addressing Utilities */
#define mfc_ea2h(ea) (unsigned int)((unsigned long long)(ea)>>32)
#define mfc_ea2l(ea) (unsigned int)(ea)
#define mfc_hl2ea(h,l) si_to_ullong(si_selb(si_from_uint(h),\
si_rotqbyi(si_from_uint(l), -4),\
si_fsmbi(0x0f0f)))
#define mfc_ceil128(v) (((v) + 127) & ~127)
/* MFC DMA */
#define mfc_put( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUT_CMD))
#define mfc_putf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTF_CMD))
#define mfc_putb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTB_CMD))
#define mfc_get( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GET_CMD))
#define mfc_getf( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETF_CMD))
#define mfc_getb( ls,ea,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETB_CMD))
/* MFC list DMA */
#define mfc_putl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTL_CMD))
#define mfc_putlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLF_CMD))
#define mfc_putlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_PUTLB_CMD))
#define mfc_getl( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETL_CMD))
#define mfc_getlf( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLF_CMD))
#define mfc_getlb( ls,ea,lsa,size,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),(unsigned int)(lsa),size,tag,MFC_CMD_WORD(tid,rid,MFC_GETLB_CMD))
/* MFC Atomic Update DMA */
#define mfc_getllar( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_GETLLAR_CMD))
#define mfc_putllc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLC_CMD))
#define mfc_putlluc( ls,ea,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128, 0,MFC_CMD_WORD(tid,rid,MFC_PUTLLUC_CMD))
#define mfc_putqlluc(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),128,tag,MFC_CMD_WORD(tid,rid,MFC_PUTQLLUC_CMD))
/* MFC Synchronization Commands */
#define mfc_sndsig( ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIG_CMD))
#define mfc_sndsigb(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGB_CMD))
#define mfc_sndsigf(ls,ea,tag,tid,rid) spu_mfcdma64(ls,mfc_ea2h(ea),mfc_ea2l(ea),4,tag,MFC_CMD_WORD(tid,rid,MFC_SNDSIGF_CMD))
#define mfc_barrier(tag) spu_mfcdma32(0,0,0,tag,MFC_BARRIER_CMD)
#define mfc_eieio(tag,tid,rid) spu_mfcdma32(0,0,0,tag,MFC_CMD_WORD(tid,rid,MFC_EIEIO_CMD))
#define mfc_sync(tag) spu_mfcdma32(0,0,0,tag,MFC_SYNC_CMD)
/* MFC SL1 Storage Control Commands */
#define mfc_sdcrt( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRT_CMD))
#define mfc_sdcrtst(ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRTST_CMD))
#define mfc_sdcrz( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRZ_CMD))
#define mfc_sdcrst( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRST_CMD))
#define mfc_sdcrf( ea,size,tag,tid,rid) spu_mfcdma64(0,mfc_ea2h(ea),mfc_ea2l(ea),size,tag,MFC_CMD_WORD(tid,rid,MFC_SDCRF_CMD))
/* DMA Queue */
#define mfc_stat_cmd_queue() spu_readchcnt(MFC_Cmd)
/* MFC Tag-Status */
#define mfc_write_tag_mask(mask) spu_writech(MFC_WrTagMask,mask)
#define mfc_read_tag_mask() spu_readch(MFC_RdTagMask)
#define mfc_write_tag_update(ts) spu_writech(MFC_WrTagUpdate,ts)
#define mfc_write_tag_update_immediate() mfc_write_tag_update(MFC_TAG_UPDATE_IMMEDIATE)
#define mfc_write_tag_update_any() mfc_write_tag_update(MFC_TAG_UPDATE_ANY)
#define mfc_write_tag_update_all() mfc_write_tag_update(MFC_TAG_UPDATE_ALL)
#define mfc_stat_tag_update() spu_readchcnt(MFC_WrTagUpdate)
#define mfc_read_tag_status() spu_readch(MFC_RdTagStat)
#define mfc_read_tag_status_immediate() (mfc_write_tag_update_immediate(), mfc_read_tag_status())
#define mfc_read_tag_status_any() (mfc_write_tag_update_any(), mfc_read_tag_status())
#define mfc_read_tag_status_all() (mfc_write_tag_update_all(), mfc_read_tag_status())
#define mfc_stat_tag_status() spu_readchcnt(MFC_RdTagStat)
/* MFC List Stall-and-Notify Tag */
#define mfc_read_list_stall_status() spu_readch(MFC_RdListStallStat)
#define mfc_stat_list_stall_status() spu_readchcnt(MFC_RdListStallStat)
#define mfc_write_list_stall_ack(tag) spu_writech(MFC_WrListStallAck,tag)
/* Atomic DMA */
#define mfc_read_atomic_status() spu_readch(MFC_RdAtomicStat)
#define mfc_stat_atomic_status() spu_readchcnt(MFC_RdAtomicStat)
/* MFC Multi-source Synchronization */
#define mfc_write_multi_src_sync_request() spu_writech(MFC_WrMSSyncReq,0)
#define mfc_stat_multi_src_sync_request() spu_readchcnt(MFC_WrMSSyncReq)
/* SPU Signal */
#define spu_read_signal1() spu_readch(SPU_RdSigNotify1)
#define spu_stat_signal1() spu_readchcnt(SPU_RdSigNotify1)
#define spu_read_signal2() spu_readch(SPU_RdSigNotify2)
#define spu_stat_signal2() spu_readchcnt(SPU_RdSigNotify2)
/* SPU/PPE Mailbox */
#define spu_read_in_mbox() spu_readch(SPU_RdInMbox)
#define spu_stat_in_mbox() spu_readchcnt(SPU_RdInMbox)
#define spu_write_out_mbox(a) spu_writech(SPU_WrOutMbox,a)
#define spu_stat_out_mbox() spu_readchcnt(SPU_WrOutMbox)
#define spu_write_out_intr_mbox(a) spu_writech(SPU_WrOutIntrMbox,a)
#define spu_stat_out_intr_mbox() spu_readchcnt(SPU_WrOutIntrMbox)
/* SPU Decrementer */
#define spu_read_decrementer() spu_readch(SPU_RdDec)
#define spu_write_decrementer(cnt) spu_writech(SPU_WrDec,(cnt))
/* SPU Event */
#define spu_read_event_status() spu_readch(SPU_RdEventStat)
#define spu_stat_event_status() spu_readchcnt(SPU_RdEventStat)
#define spu_write_event_mask(mask) spu_writech(SPU_WrEventMask,(mask))
#define spu_write_event_ack(ack) spu_writech(SPU_WrEventAck,(ack))
#define spu_read_event_mask() spu_readch(SPU_RdEventMask)
/* SPU State Management */
#define spu_read_machine_status() spu_readch(SPU_RdMachStat)
#define spu_write_srr0(srr0) spu_writech(SPU_WrSRR0,srr0)
#define spu_read_srr0() spu_readch(SPU_RdSRR0)
/* Interrupt-Safe Critical Sections */
static __inline__ unsigned int mfc_begin_critical_section (void)
__attribute__ ((__always_inline__));
static __inline__ unsigned int
mfc_begin_critical_section (void)
{
#ifdef SPU_MFCIO_INTERRUPT_SAFE
unsigned int __status = spu_read_machine_status ();
spu_idisable ();
return __status;
#else
return 0;
#endif
}
static __inline__ void mfc_end_critical_section (unsigned int)
__attribute__ ((__always_inline__));
static __inline__ void
mfc_end_critical_section (unsigned int __status __attribute__ ((__unused__)))
{
#ifdef SPU_MFCIO_INTERRUPT_SAFE
if (__status & 1)
spu_ienable ();
#endif
}
/* MFC Tag Manager */
#define MFC_TAG_INVALID 0xFFFFFFFF
#define MFC_TAG_VALID 0x00000000
#define mfc_tag_reserve() \
__mfc_tag_reserve()
#define mfc_tag_release(tag) \
__mfc_tag_release((tag))
#define mfc_multi_tag_reserve(nr_tags) \
__mfc_multi_tag_reserve((nr_tags))
#define mfc_multi_tag_release(tag, nr_tags) \
__mfc_multi_tag_release((tag),(nr_tags))
extern unsigned int __mfc_tag_reserve (void);
extern unsigned int __mfc_tag_release (unsigned int);
extern unsigned int __mfc_multi_tag_reserve (unsigned int);
extern unsigned int __mfc_multi_tag_release (unsigned int, unsigned int);
#ifdef __cplusplus
}
#endif
#endif /* __SPU_MFCIO_H__ */

34
gcc/config/spu/t-spu-elf
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@ -1,34 +0,0 @@
# Copyright (C) 2006-2019 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 3 of the License, or (at your option)
# any later version.
#
# This file is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Multi-lib support.
MULTILIB_OPTIONS=mea64
spu.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
$(RTL_H) $(REGS_H) hard-reg-set.h dumpfile.h \
real.h insn-config.h conditions.h insn-attr.h flags.h $(RECOG_H) \
$(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \
output.h $(BASIC_BLOCK_H) $(GGC_H) $(HASHTAB_H) \
$(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h $(CFGLOOP_H) \
$(srcdir)/config/spu/spu-protos.h \
$(srcdir)/config/spu/spu-builtins.def
spu-c.o: $(srcdir)/config/spu/spu-c.c \
$(srcdir)/config/spu/spu-protos.h \
$(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(CPPLIB_H) \
$(TM_P_H) $(C_COMMON_H) $(C_PRAGMA_H) coretypes.h $(TM_H) insn-codes.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/spu/spu-c.c

36
gcc/config/spu/vec_types.h
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@ -1,36 +0,0 @@
/* Copyright (C) 2006-2019 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This file is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifndef _VEC_TYPES_H_
#define _VEC_TYPES_H_ 1
#include <spu_intrinsics.h>
/* Define additional PowerPC SIMD/Vector Multi-media eXtension
* single keyword vector data types for use in mapping VMX code
* to the SPU.
*/
#define vec_bchar16 __vector unsigned char
#define vec_bshort8 __vector unsigned short
#define vec_pixel8 __vector unsigned short
#define vec_bint4 __vector unsigned int
#endif /* _VEC_TYPES_H_ */

3985
gcc/config/spu/vmx2spu.h
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File diff suppressed because it is too large Load Diff

2
gcc/configure vendored
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@ -27962,7 +27962,7 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | m32c | m68k \
| microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \
| microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
| tilegx | tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;

2
gcc/configure.ac
View File

@ -4999,7 +4999,7 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arc | arm | avr | bfin | cris | csky | i386 | m32c | m68k \
| microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc | spu \
| microblaze | mips | nds32 | nios2 | pa | riscv | rs6000 | score | sparc \
| tilegx | tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;

113
gcc/doc/extend.texi
View File

@ -1385,7 +1385,7 @@ As an extension, GNU C supports named address spaces as
defined in the N1275 draft of ISO/IEC DTR 18037. Support for named
address spaces in GCC will evolve as the draft technical report
changes. Calling conventions for any target might also change. At
present, only the AVR, SPU, M32C, RL78, and x86 targets support
present, only the AVR, M32C, RL78, and x86 targets support
address spaces other than the generic address space.
Address space identifiers may be used exactly like any other C type
@ -1573,23 +1573,6 @@ with 32-bit pointers (20-bit addresses) rather than the default 16-bit
addresses. Non-far variables are assumed to appear in the topmost
64@tie{}KiB of the address space.
@subsection SPU Named Address Spaces
@cindex @code{__ea} SPU Named Address Spaces
On the SPU target variables may be declared as
belonging to another address space by qualifying the type with the
@code{__ea} address space identifier:
@smallexample
extern int __ea i;
@end smallexample
@noindent
The compiler generates special code to access the variable @code{i}.
It may use runtime library
support, or generate special machine instructions to access that address
space.
@subsection x86 Named Address Spaces
@cindex x86 named address spaces
@ -2486,7 +2469,6 @@ GCC plugins may provide their own attributes.
* RX Function Attributes::
* S/390 Function Attributes::
* SH Function Attributes::
* SPU Function Attributes::
* Symbian OS Function Attributes::
* V850 Function Attributes::
* Visium Function Attributes::
@ -5839,24 +5821,6 @@ On SH targets this function attribute is similar to @code{interrupt_handler}
but it does not save and restore all registers.
@end table
@node SPU Function Attributes
@subsection SPU Function Attributes
These function attributes are supported by the SPU back end:
@table @code
@item naked
@cindex @code{naked} function attribute, SPU
This attribute allows the compiler to construct the
requisite function declaration, while allowing the body of the
function to be assembly code. The specified function will not have
prologue/epilogue sequences generated by the compiler. Only basic
@code{asm} statements can safely be included in naked functions
(@pxref{Basic Asm}). While using extended @code{asm} or a mixture of
basic @code{asm} and C code may appear to work, they cannot be
depended upon to work reliably and are not supported.
@end table
@node Symbian OS Function Attributes
@subsection Symbian OS Function Attributes
@ -6707,7 +6671,6 @@ attributes.
* Nvidia PTX Variable Attributes::
* PowerPC Variable Attributes::
* RL78 Variable Attributes::
* SPU Variable Attributes::
* V850 Variable Attributes::
* x86 Variable Attributes::
* Xstormy16 Variable Attributes::
@ -7622,14 +7585,6 @@ The RL78 back end supports the @code{saddr} variable attribute. This
specifies placement of the corresponding variable in the SADDR area,
which can be accessed more efficiently than the default memory region.
@node SPU Variable Attributes
@subsection SPU Variable Attributes
@cindex @code{spu_vector} variable attribute, SPU
The SPU supports the @code{spu_vector} attribute for variables. For
documentation of this attribute please see the documentation in
@ref{SPU Type Attributes}.
@node V850 Variable Attributes
@subsection V850 Variable Attributes
@ -7737,7 +7692,6 @@ attributes.
* ARM Type Attributes::
* MeP Type Attributes::
* PowerPC Type Attributes::
* SPU Type Attributes::
* x86 Type Attributes::
@end menu
@ -8328,15 +8282,6 @@ __attribute__((altivec(bool__))) unsigned
These attributes mainly are intended to support the @code{__vector},
@code{__pixel}, and @code{__bool} AltiVec keywords.
@node SPU Type Attributes
@subsection SPU Type Attributes
@cindex @code{spu_vector} type attribute, SPU
The SPU supports the @code{spu_vector} attribute for types. This attribute
allows one to declare vector data types supported by the Sony/Toshiba/IBM SPU
Language Extensions Specification. It is intended to support the
@code{__vector} keyword.
@node x86 Type Attributes
@subsection x86 Type Attributes
@ -13621,7 +13566,6 @@ instructions, but allow the compiler to schedule those calls.
* S/390 System z Built-in Functions::
* SH Built-in Functions::
* SPARC VIS Built-in Functions::
* SPU Built-in Functions::
* TI C6X Built-in Functions::
* TILE-Gx Built-in Functions::
* TILEPro Built-in Functions::
@ -21160,61 +21104,6 @@ long __builtin_vis_fpcmpur16shl (v4hi, v4hi, int);
long __builtin_vis_fpcmpur32shl (v2si, v2si, int);
@end smallexample
@node SPU Built-in Functions
@subsection SPU Built-in Functions
GCC provides extensions for the SPU processor as described in the
Sony/Toshiba/IBM SPU Language Extensions Specification. GCC's
implementation differs in several ways.
@itemize @bullet
@item
The optional extension of specifying vector constants in parentheses is
not supported.
@item
A vector initializer requires no cast if the vector constant is of the
same type as the variable it is initializing.
@item
If @code{signed} or @code{unsigned} is omitted, the signedness of the
vector type is the default signedness of the base type. The default
varies depending on the operating system, so a portable program should
always specify the signedness.
@item
By default, the keyword @code{__vector} is added. The macro
@code{vector} is defined in @code{<spu_intrinsics.h>} and can be
undefined.
@item
GCC allows using a @code{typedef} name as the type specifier for a
vector type.
@item
For C, overloaded functions are implemented with macros so the following
does not work:
@smallexample
spu_add ((vector signed int)@{1, 2, 3, 4@}, foo);
@end smallexample
@noindent
Since @code{spu_add} is a macro, the vector constant in the example
is treated as four separate arguments. Wrap the entire argument in
parentheses for this to work.
@item
The extended version of @code{__builtin_expect} is not supported.
@end itemize
@emph{Note:} Only the interface described in the aforementioned
specification is supported. Internally, GCC uses built-in functions to
implement the required functionality, but these are not supported and
are subject to change without notice.
@node TI C6X Built-in Functions
@subsection TI C6X Built-in Functions

147
gcc/doc/invoke.texi
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@ -1214,17 +1214,6 @@ See RS/6000 and PowerPC Options.
-mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol
-mlra -mno-lra}
@emph{SPU Options}
@gccoptlist{-mwarn-reloc -merror-reloc @gol
-msafe-dma -munsafe-dma @gol
-mbranch-hints @gol
-msmall-mem -mlarge-mem -mstdmain @gol
-mfixed-range=@var{register-range} @gol
-mea32 -mea64 @gol
-maddress-space-conversion -mno-address-space-conversion @gol
-mcache-size=@var{cache-size} @gol
-matomic-updates -mno-atomic-updates}
@emph{System V Options}
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
@ -15717,7 +15706,6 @@ platform.
* SH Options::
* Solaris 2 Options::
* SPARC Options::
* SPU Options::
* System V Options::
* TILE-Gx Options::
* TILEPro Options::
@ -26772,141 +26760,6 @@ when making stack frame references. This is the default in 64-bit mode.
Otherwise, assume no such offset is present.
@end table
@node SPU Options
@subsection SPU Options
@cindex SPU options
These @samp{-m} options are supported on the SPU:
@table @gcctabopt
@item -mwarn-reloc
@itemx -merror-reloc
@opindex mwarn-reloc
@opindex merror-reloc
The loader for SPU does not handle dynamic relocations. By default, GCC
gives an error when it generates code that requires a dynamic
relocation. @option{-mno-error-reloc} disables the error,
@option{-mwarn-reloc} generates a warning instead.
@item -msafe-dma
@itemx -munsafe-dma
@opindex msafe-dma
@opindex munsafe-dma
Instructions that initiate or test completion of DMA must not be
reordered with respect to loads and stores of the memory that is being
accessed.
With @option{-munsafe-dma} you must use the @code{volatile} keyword to protect
memory accesses, but that can lead to inefficient code in places where the
memory is known to not change. Rather than mark the memory as volatile,
you can use @option{-msafe-dma} to tell the compiler to treat
the DMA instructions as potentially affecting all memory.
@item -mbranch-hints
@opindex mbranch-hints
By default, GCC generates a branch hint instruction to avoid
pipeline stalls for always-taken or probably-taken branches. A hint
is not generated closer than 8 instructions away from its branch.
There is little reason to disable them, except for debugging purposes,
or to make an object a little bit smaller.
@item -msmall-mem
@itemx -mlarge-mem
@opindex msmall-mem
@opindex mlarge-mem
By default, GCC generates code assuming that addresses are never larger
than 18 bits. With @option{-mlarge-mem} code is generated that assumes
a full 32-bit address.
@item -mstdmain
@opindex mstdmain
By default, GCC links against startup code that assumes the SPU-style
main function interface (which has an unconventional parameter list).
With @option{-mstdmain}, GCC links your program against startup
code that assumes a C99-style interface to @code{main}, including a
local copy of @code{argv} strings.
@item -mfixed-range=@var{register-range}
@opindex mfixed-range
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator cannot use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
@item -mea32
@itemx -mea64
@opindex mea32
@opindex mea64
Compile code assuming that pointers to the PPU address space accessed
via the @code{__ea} named address space qualifier are either 32 or 64
bits wide. The default is 32 bits. As this is an ABI-changing option,
all object code in an executable must be compiled with the same setting.
@item -maddress-space-conversion
@itemx -mno-address-space-conversion
@opindex maddress-space-conversion
@opindex mno-address-space-conversion
Allow/disallow treating the @code{__ea} address space as superset
of the generic address space. This enables explicit type casts
between @code{__ea} and generic pointer as well as implicit
conversions of generic pointers to @code{__ea} pointers. The
default is to allow address space pointer conversions.
@item -mcache-size=@var{cache-size}
@opindex mcache-size
This option controls the version of libgcc that the compiler links to an
executable and selects a software-managed cache for accessing variables
in the @code{__ea} address space with a particular cache size. Possible
options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64}
and @samp{128}. The default cache size is 64KB.
@item -matomic-updates
@itemx -mno-atomic-updates
@opindex matomic-updates
@opindex mno-atomic-updates
This option controls the version of libgcc that the compiler links to an
executable and selects whether atomic updates to the software-managed
cache of PPU-side variables are used. If you use atomic updates, changes
to a PPU variable from SPU code using the @code{__ea} named address space
qualifier do not interfere with changes to other PPU variables residing
in the same cache line from PPU code. If you do not use atomic updates,
such interference may occur; however, writing back cache lines is
more efficient. The default behavior is to use atomic updates.
@item -mdual-nops
@itemx -mdual-nops=@var{n}
@opindex mdual-nops
By default, GCC inserts NOPs to increase dual issue when it expects
it to increase performance. @var{n} can be a value from 0 to 10. A
smaller @var{n} inserts fewer NOPs. 10 is the default, 0 is the
same as @option{-mno-dual-nops}. Disabled with @option{-Os}.
@item -mhint-max-nops=@var{n}
@opindex mhint-max-nops
Maximum number of NOPs to insert for a branch hint. A branch hint must
be at least 8 instructions away from the branch it is affecting. GCC
inserts up to @var{n} NOPs to enforce this, otherwise it does not
generate the branch hint.
@item -mhint-max-distance=@var{n}
@opindex mhint-max-distance
The encoding of the branch hint instruction limits the hint to be within
256 instructions of the branch it is affecting. By default, GCC makes
sure it is within 125.
@item -msafe-hints
@opindex msafe-hints
Work around a hardware bug that causes the SPU to stall indefinitely.
By default, GCC inserts the @code{hbrp} instruction to make sure
this stall won't happen.
@end table
@node System V Options
@subsection Options for System V

70
gcc/doc/md.texi
View File

@ -3736,76 +3736,6 @@ Vector zero
@end table
@item SPU---@file{config/spu/spu.h}
@table @code
@item a
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
@item c
An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
@item d
An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
@item f
An immediate which can be loaded with @code{fsmbi}.
@item A
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
@item B
An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
@item C
An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
@item D
An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
@item I
A constant in the range [@minus{}64, 63] for shift/rotate instructions.
@item J
An unsigned 7-bit constant for conversion/nop/channel instructions.
@item K
A signed 10-bit constant for most arithmetic instructions.
@item M
A signed 16 bit immediate for @code{stop}.
@item N
An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
@item O
An unsigned 7-bit constant whose 3 least significant bits are 0.
@item P
An unsigned 3-bit constant for 16-byte rotates and shifts
@item R
Call operand, reg, for indirect calls
@item S
Call operand, symbol, for relative calls.
@item T
Call operand, const_int, for absolute calls.
@item U
An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
@item W
An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
@item Y
An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
@item Z
An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
@end table
@item TI C6X family---@file{config/c6x/constraints.md}
@table @code
@item a

10
gcc/doc/sourcebuild.texi
View File

@ -2011,9 +2011,6 @@ PowerPC target supports PowerPC 405.
@item ppc_recip_hw
PowerPC target supports executing reciprocal estimate instructions.
@item spu_auto_overlay
SPU target has toolchain that supports automatic overlay generation.
@item vmx_hw
PowerPC target supports executing AltiVec instructions.
@ -2423,13 +2420,6 @@ Target supports compiling @code{vpclmul} instructions.
Target supports compiling @code{xop} instructions.
@end table
@subsubsection Local to tests in @code{gcc.target/spu/ea}
@table @code
@item ealib
Target @code{__ea} library functions are available.
@end table
@subsubsection Local to tests in @code{gcc.test-framework}
@table @code

165
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,168 @@
2019-09-03 Ulrich Weigand <uweigand@de.ibm.com>
* lib/compat.exp: Remove references to spu.
* lib/fortran-torture.exp: Likewise.
* lib/gcc-dg.exp: Likewise.
* lib/gfortran.exp: Likewise.
* lib/target-supports.exp: Likewise.
* lib/target-utils.exp: Likewise.
* c-c++-common/torture/complex-sign-add.c: Remove references to spu.
* c-c++-common/torture/complex-sign-mixed-add.c: Likewise.
* c-c++-common/torture/complex-sign-mixed-div.c: Likewise.
* c-c++-common/torture/complex-sign-mixed-mul.c: Likewise.
* c-c++-common/torture/complex-sign-mixed-sub.c: Likewise.
* c-c++-common/torture/complex-sign-mul-minus-one.c: Likewise.
* c-c++-common/torture/complex-sign-mul-one.c: Likewise.
* c-c++-common/torture/complex-sign-mul.c: Likewise.
* c-c++-common/torture/complex-sign-sub.c: Likewise.
* g++.dg/opt/temp1.C: Remove references to spu.
* g++.dg/opt/vt1.C: Likewise.
* g++.dg/torture/type-generic-1.C: Likewise.
* g++.dg/warn/pr30551-2.C: Likewise.
* g++.dg/warn/pr30551.C: Likewise.
* g++.old-deja/g++.jason/thunk2.C: Likewise.
* g++.old-deja/g++.other/comdat5.C: Likewise.
* g++.old-deja/g++.other/local-alloc1.C: Likewise.
* gcc.c-torture/compile/20001226-1.c: Remove references to spu.
* gcc.c-torture/execute/20030222-1.c: Likewise.
* gcc.c-torture/execute/20031003-1.c: Likewise.
* gcc.c-torture/execute/20101011-1.c: Likewise.
* gcc.c-torture/execute/conversion.c: Likewise.
* gcc.c-torture/execute/ieee/compare-fp-4.x: Likewise.
* gcc.c-torture/execute/ieee/fp-cmp-2.x: Likewise.
* gcc.c-torture/execute/ieee/inf-1.c: Likewise.
* gcc.c-torture/execute/ieee/inf-2.c: Likewise.
* gcc.c-torture/execute/ieee/mul-subnormal-single-1.x: Likewise.
* gcc.c-torture/execute/ieee/rbug.c: Likewise.
* gcc.c-torture/execute/pr39228.c: Likewise.
* gcc.c-torture/execute/ieee/20010114-2.x: Remove file.
* gcc.c-torture/execute/ieee/20030331-1.x: Remove file.
* gcc.c-torture/execute/ieee/920518-1.x: Remove file.
* gcc.c-torture/execute/ieee/compare-fp-1.x: Remove file.
* gcc.c-torture/execute/ieee/fp-cmp-4f.x: Remove file.
* gcc.c-torture/execute/ieee/fp-cmp-8f.x: Remove file.
* gcc.dg/20020312-2.c: Remove references to spu.
* gcc.dg/20030702-1.c: Likewise.
* gcc.dg/and-1.c: Likewise.
* gcc.dg/builtin-inf-1.c: Likewise.
* gcc.dg/builtins-1.c: Likewise.
* gcc.dg/builtins-43.c: Likewise.
* gcc.dg/builtins-44.c: Likewise.
* gcc.dg/builtins-45.c: Likewise.
* gcc.dg/float-range-1.c: Likewise.
* gcc.dg/float-range-3.c: Likewise.
* gcc.dg/float-range-4.c: Likewise.
* gcc.dg/float-range-5.c: Likewise.
* gcc.dg/fold-overflow-1.c: Likewise.
* gcc.dg/format/ms_unnamed-1.c: Likewise.
* gcc.dg/format/unnamed-1.c: Likewise.
* gcc.dg/hex-round-1.c: Likewise.
* gcc.dg/hex-round-2.c: Likewise.
* gcc.dg/lower-subreg-1.c: Likewise.
* gcc.dg/nrv3.c: Likewise.
* gcc.dg/pr15784-3.c: Likewise.
* gcc.dg/pr27095.c: Likewise.
* gcc.dg/pr28243.c: Likewise.
* gcc.dg/pr28796-2.c: Likewise.
* gcc.dg/pr30551-3.c: Likewise.
* gcc.dg/pr30551-6.c: Likewise.
* gcc.dg/pr30551.c: Likewise.
* gcc.dg/pr70317.c: Likewise.
* gcc.dg/sms-1.c: Likewise.
* gcc.dg/sms-2.c: Likewise.
* gcc.dg/sms-3.c: Likewise.
* gcc.dg/sms-4.c: Likewise.
* gcc.dg/sms-5.c: Likewise.
* gcc.dg/sms-6.c: Likewise.
* gcc.dg/sms-7.c: Likewise.
* gcc.dg/stack-usage-1.c: Likewise.
* gcc.dg/strlenopt-73.c: Likewise.
* gcc.dg/titype-1.c: Likewise.
* gcc.dg/tls/thr-cse-1.c: Likewise.
* gcc.dg/torture/builtin-attr-1.c: Likewise.
* gcc.dg/torture/builtin-complex-1.c: Likewise.
* gcc.dg/torture/builtin-cproj-1.c: Likewise.
* gcc.dg/torture/builtin-frexp-1.c: Likewise.
* gcc.dg/torture/builtin-ldexp-1.c: Likewise.
* gcc.dg/torture/builtin-logb-1.c: Likewise.
* gcc.dg/torture/builtin-math-2.c: Likewise.
* gcc.dg/torture/builtin-math-5.c: Likewise.
* gcc.dg/torture/builtin-modf-1.c: Likewise.
* gcc.dg/torture/fp-int-convert.h: Likewise.
* gcc.dg/torture/pr25947-1.c: Likewise.
* gcc.dg/torture/type-generic-1.c: Likewise.
* gcc.dg/tree-ssa/20040204-1.c: Likewise.
* gcc.dg/tree-ssa/ivopts-1.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-3.c: Likewise.
* gcc.dg/tree-ssa/vector-6.c: Likewise.
* gcc.dg/uninit-C-O0.c: Likewise.
* gcc.dg/uninit-C.c: Likewise.
* gcc.dg/vect/no-math-errno-slp-32.c: Likewise.
* gcc.dg/vect/no-math-errno-vect-pow-1.c: Likewise.
* gcc.dg/vect/vect-float-extend-1.c: Likewise.
* gcc.dg/vect/vect-float-truncate-1.c: Likewise.
* gcc.dg/vect/vect.exp: Likewise.
* gcc.gd/vect/costmodel/spu/: Remove directory.
* gcc.target/spu/: Remove directory.
* gfortran.dg/bessel_6.f90: Remove references to spu.
* gfortran.dg/bessel_7.f90: Likewise.
* gfortran.dg/char4_iunit_1.f03: Likewise.
* gfortran.dg/chmod_1.f90: Likewise.
* gfortran.dg/chmod_2.f90: Likewise.
* gfortran.dg/chmod_3.f90: Likewise.
* gfortran.dg/default_format_1.f90: Likewise.
* gfortran.dg/default_format_denormal_1.f90: Likewise.
* gfortran.dg/erf_2.F90: Likewise.
* gfortran.dg/erf_3.F90: Likewise.
* gfortran.dg/init_flag_10.f90: Likewise.
* gfortran.dg/init_flag_3.f90: Likewise.
* gfortran.dg/int_conv_2.f90: Likewise.
* gfortran.dg/integer_exponentiation_3.F90: Likewise.
* gfortran.dg/integer_exponentiation_5.F90: Likewise.
* gfortran.dg/isnan_1.f90: Likewise.
* gfortran.dg/isnan_2.f90: Likewise.
* gfortran.dg/maxloc_2.f90: Likewise.
* gfortran.dg/maxlocval_2.f90: Likewise.
* gfortran.dg/maxlocval_4.f90: Likewise.
* gfortran.dg/minloc_1.f90: Likewise.
* gfortran.dg/minlocval_1.f90: Likewise.
* gfortran.dg/minlocval_4.f90: Likewise.
* gfortran.dg/module_nan.f90: Likewise.
* gfortran.dg/namelist_42.f90: Likewise.
* gfortran.dg/namelist_43.f90: Likewise.
* gfortran.dg/nan_1.f90: Likewise.
* gfortran.dg/nan_2.f90: Likewise.
* gfortran.dg/nan_3.f90: Likewise.
* gfortran.dg/nan_4.f90: Likewise.
* gfortran.dg/nan_5.f90: Likewise.
* gfortran.dg/nan_6.f90: Likewise.
* gfortran.dg/nearest_1.f90: Likewise.
* gfortran.dg/nearest_3.f90: Likewise.
* gfortran.dg/open_errors.f90: Likewise.
* gfortran.dg/pr20257.f90: Likewise.
* gfortran.dg/read_infnan_1.f90: Likewise.
* gfortran.dg/real_const_3.f90: Likewise.
* gfortran.dg/realloc_on_assign_2.f03: Likewise.
* gfortran.dg/reassoc_4.f: Likewise.
* gfortran.dg/scalar_mask_2.f90: Likewise.
* gfortran.dg/scratch_1.f90: Likewise.
* gfortran.dg/stat_1.f90: Likewise.
* gfortran.dg/stat_2.f90: Likewise.
* gfortran.dg/transfer_simplify_1.f90: Likewise.
* gfortran.dg/typebound_operator_9.f03: Likewise.
* gfortran.fortran-torture/execute/intrinsic_nearest.x: Remove
references to spu.
* gfortran.fortran-torture/execute/intrinsic_set_exponent.x: Likewise.
* gfortran.fortran-torture/execute/nan_inf_fmt.x: Likewise.
* gfortran.fortran-torture/execute/getarg_1.x: Remove file.
2019-09-03 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR middle-end/91603

2
gcc/testsuite/c-c++-common/torture/complex-sign-add.c
View File

@ -28,9 +28,7 @@
void
check_add_float (void)
{
#ifndef __SPU__
CHECK_ADD (float, __builtin_copysignf, 0.0f, 0.0if);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mixed-add.c
View File

@ -29,9 +29,7 @@
void
check_add_float (void)
{
#ifndef __SPU__
CHECK_ADD (float, __builtin_copysignf, 0.0f, 0.0if);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mixed-div.c
View File

@ -20,9 +20,7 @@
void
check_div_float (void)
{
#ifndef __SPU__
CHECK_DIV (float, __builtin_copysignf, 0.0f, 0.0if, 1.0f);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mixed-mul.c
View File

@ -28,9 +28,7 @@
void
check_mul_float (void)
{
#ifndef __SPU__
CHECK_MUL (float, __builtin_copysignf, 0.0f, 0.0if);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mixed-sub.c
View File

@ -29,9 +29,7 @@
void
check_sub_float (void)
{
#ifndef __SPU__
CHECK_SUB (float, __builtin_copysignf, 0.0f, 0.0if);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mul-minus-one.c
View File

@ -36,9 +36,7 @@
void
check_mul_float (void)
{
#ifndef __SPU__
CHECK_MUL (float, __builtin_copysignf, 0.0f, 0.0if, 1.0f);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mul-one.c
View File

@ -36,9 +36,7 @@
void
check_mul_float (void)
{
#ifndef __SPU__
CHECK_MUL (float, __builtin_copysignf, 0.0f, 0.0if, 1.0f);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-mul.c
View File

@ -28,9 +28,7 @@
void
check_mul_float (void)
{
#ifndef __SPU__
CHECK_MUL (float, __builtin_copysignf, 0.0f, 0.0if);
#endif
}
void

2
gcc/testsuite/c-c++-common/torture/complex-sign-sub.c
View File

@ -28,9 +28,7 @@
void
check_sub_float (void)
{
#ifndef __SPU__
CHECK_SUB (float, __builtin_copysignf, 0.0f, 0.0if);
#endif
}
void

5
gcc/testsuite/g++.dg/opt/temp1.C
View File

@ -24,12 +24,7 @@ void *memcpy (void *dest, const void *src, __SIZE_TYPE__ n)
}
struct T {
#ifdef __SPU__
/* SPU returns aggregates up to 1172 bytes in registers. */
int a[300];
#else
int a[128];
#endif
T &operator+=(T const &v) __attribute__((noinline));
T operator+(T const &v) const { T t = *this; t += v; return t; }
};

1
gcc/testsuite/g++.dg/opt/vt1.C
View File

@ -1,7 +1,6 @@
// Test whether vtable for S is not put into read-only section.
// { dg-do compile { target fpic } }
// { dg-options "-O2 -fpic -fno-rtti" }
// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } }
// { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } }
// Origin: Jakub Jelinek <jakub@redhat.com>

1
gcc/testsuite/g++.dg/torture/type-generic-1.C
View File

@ -3,7 +3,6 @@
/* { dg-do run } */
/* { dg-add-options ieee } */
/* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
/* { dg-skip-if "No subnormal support" { csky-*-* } { "-mhard-float" } } */
#include "../../gcc.dg/tg-tests.h"

1
gcc/testsuite/g++.dg/warn/pr30551-2.C
View File

@ -1,6 +1,5 @@
// PR 30551 -Wmain is enabled by -pedantic/-pedantic-errors.
// { dg-do compile }
// { dg-options "-pedantic-errors" }
// { dg-skip-if "-Wmain not enabled with -pedantic on SPU" { spu-*-* } }
int main(char a) {} /* { dg-error "first argument of .*main.* should be .int." "int" } */
/* { dg-error "main.* takes only zero or two arguments" "zero or two" { target *-*-* } .-1 } */

1
gcc/testsuite/g++.dg/warn/pr30551.C
View File

@ -1,6 +1,5 @@
// PR 30551 -Wmain is enabled by default.
// { dg-do compile }
// { dg-options "" }
// { dg-skip-if "-Wmain not enabled on SPU" { spu-*-* } }
int main(char a) {} /* { dg-warning "first argument of .*main.* should be .int." "int" } */
/* { dg-warning "main.* takes only zero or two arguments" "zero or two" { target *-*-* } .-1 } */

1
gcc/testsuite/g++.old-deja/g++.jason/thunk2.C
View File

@ -1,6 +1,5 @@
// { dg-do run { target fpic } }
// { dg-options "-fPIC" }
// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } }
// Test that non-variadic function calls using thunks and PIC work right.
struct A {

1
gcc/testsuite/g++.old-deja/g++.other/comdat5.C
View File

@ -2,6 +2,5 @@
// { dg-do link { target fpic } }
// { dg-additional-sources " comdat5-aux.cc" }
// { dg-options "-O2 -fPIC" }
// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } }
#include "comdat4.C"

1
gcc/testsuite/g++.old-deja/g++.other/local-alloc1.C
View File

@ -1,6 +1,5 @@
// { dg-do assemble { target fpic } }
// { dg-options "-O0 -fpic" }
// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } }
// Origin: Jakub Jelinek <jakub@redhat.com>
struct bar {

1
gcc/testsuite/gcc.c-torture/compile/20001226-1.c
View File

@ -1,7 +1,6 @@
/* { dg-do assemble } */
/* { dg-skip-if "too much code for avr" { "avr-*-*" } } */
/* { dg-skip-if "too much code for pdp11" { "pdp11-*-*" } } */
/* { dg-xfail-if "PR36698" { spu-*-* } { "-O0" } { "" } } */
/* { dg-skip-if "" { m32c-*-* } } */
/* { dg-timeout-factor 4.0 } */

1
gcc/testsuite/gcc.c-torture/execute/20030222-1.c
View File

@ -3,7 +3,6 @@
succeeded at all. We use volatile to make sure the long long is
actually truncated to int, in case a single register is wide enough
for a long long. */
/* { dg-skip-if "asm would require extra shift-left-4-byte" { spu-*-* } } */
/* { dg-skip-if "asm requires register allocation" { nvptx-*-* } } */
#include <limits.h>

6
gcc/testsuite/gcc.c-torture/execute/20031003-1.c
View File

@ -19,14 +19,8 @@ int main()
#if INT_MAX == 2147483647
if (f1() != 2147483647)
abort ();
#ifdef __SPU__
/* SPU float rounds towards zero. */
if (f2() != 0x7fffff80)
abort ();
#else
if (f2() != 2147483647)
abort ();
#endif
#endif
return 0;
}

3
gcc/testsuite/gcc.c-torture/execute/20101011-1.c
View File

@ -10,9 +10,6 @@
#elif defined (__riscv)
/* On RISC-V division by zero does not trap. */
# define DO_TEST 0
#elif defined (__SPU__)
/* On SPU division by zero does not trap. */
# define DO_TEST 0
#elif defined (__sh__)
/* On SH division by zero does not trap. */
# define DO_TEST 0

12
gcc/testsuite/gcc.c-torture/execute/conversion.c
View File

@ -284,15 +284,9 @@ test_float_to_integer()
abort();
if (f2u(1.99) != 1)
abort();
#ifdef __SPU__
/* SPU float rounds towards zero. */
if (f2u((float) ((~0U) >> 1)) != 0x7fffff80)
abort();
#else
if (f2u((float) ((~0U) >> 1)) != (~0U) >> 1 && /* 0x7fffffff */
f2u((float) ((~0U) >> 1)) != ((~0U) >> 1) + 1)
abort();
#endif
if (f2u((float) ~((~0U) >> 1)) != ~((~0U) >> 1)) /* 0x80000000 */
abort();
@ -445,15 +439,9 @@ test_float_to_longlong_integer()
abort();
if (f2ull(1.99) != 1LL)
abort();
#ifdef __SPU__
/* SPU float rounds towards zero. */
if (f2ull((float) ((~0ULL) >> 1)) != 0x7fffff8000000000ULL)
abort();
#else
if (f2ull((float) ((~0ULL) >> 1)) != (~0ULL) >> 1 && /* 0x7fffffff */
f2ull((float) ((~0ULL) >> 1)) != ((~0ULL) >> 1) + 1)
abort();
#endif
if (f2ull((float) ~((~0ULL) >> 1)) != ~((~0ULL) >> 1)) /* 0x80000000 */
abort();

6
gcc/testsuite/gcc.c-torture/execute/ieee/20010114-2.x
View File

@ -1,6 +0,0 @@
if [istarget "spu-*-*"] {
# This doesn't work on the SPU because single precision floats are
# always rounded toward 0.
return 1
}
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/20030331-1.x
View File

@ -1,6 +0,0 @@
if [istarget "spu-*-*"] {
# This doesn't work on the SPU because single precision floats are
# always rounded toward 0.
return 1
}
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/920518-1.x
View File

@ -1,6 +0,0 @@
if [istarget "spu-*-*"] {
# This doesn't work on the SPU because single precision floats are
# always rounded toward 0.
return 1
}
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/compare-fp-1.x
View File

@ -1,6 +0,0 @@
if [istarget "spu-*-*"] {
# The SPU single-precision floating point format does not
# support Nan & Inf.
return 1
}
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/compare-fp-4.x
View File

@ -13,11 +13,5 @@ if [istarget "arm*-*-vxworks*"] {
}
}
if [istarget "spu-*-*"] {
# The SPU single-precision floating point format does not
# support Nan & Inf.
return 1
}
lappend additional_flags "-fno-trapping-math"
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/fp-cmp-2.x
View File

@ -13,10 +13,4 @@ if [istarget "arm*-*-vxworks*"] {
}
}
if [istarget "spu-*-*"] {
# The SPU single-precision floating point format does not
# support Nan & Inf.
return 1
}
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/fp-cmp-4f.x
View File

@ -1,6 +0,0 @@
if [istarget "spu-*-*"] {
# The SPU single-precision floating point format does not
# support Nan & Inf.
return 1
}
return 0

6
gcc/testsuite/gcc.c-torture/execute/ieee/fp-cmp-8f.x
View File

@ -1,6 +0,0 @@
if [istarget "spu-*-*"] {
# The SPU single-precision floating point format does not
# support Nan & Inf.
return 1
}
return 0

9
gcc/testsuite/gcc.c-torture/execute/ieee/inf-1.c
View File

@ -2,10 +2,7 @@ extern void abort (void);
int main()
{
#ifndef __SPU__
/* The SPU single-precision floating point format does not support Inf. */
float fi = __builtin_inff();
#endif
double di = __builtin_inf();
long double li = __builtin_infl();
@ -13,28 +10,22 @@ int main()
double dh = __builtin_huge_val();
long double lh = __builtin_huge_vall();
#ifndef __SPU__
if (fi + fi != fi)
abort ();
#endif
if (di + di != di)
abort ();
if (li + li != li)
abort ();
#ifndef __SPU__
if (fi != fh)
abort ();
#endif
if (di != dh)
abort ();
if (li != lh)
abort ();
#ifndef __SPU__
if (fi <= 0)
abort ();
#endif
if (di <= 0)
abort ();
if (li <= 0)

4
gcc/testsuite/gcc.c-torture/execute/ieee/inf-2.c
View File

@ -25,9 +25,6 @@ void test(double f, double i)
void testf(float f, float i)
{
#ifndef __SPU__
/* The SPU single-precision floating point format does not support Inf. */
if (f == __builtin_inff())
abort ();
if (f == -__builtin_inff())
@ -47,7 +44,6 @@ void testf(float f, float i)
abort ();
if (f < -__builtin_inff())
abort ();
#endif
}
void testl(long double f, long double i)

5
gcc/testsuite/gcc.c-torture/execute/ieee/mul-subnormal-single-1.x
View File

@ -13,11 +13,6 @@ if {[istarget "m68k-*-*"] && [check_effective_target_coldfire_fpu]} {
# not aware of any system that has this.
set torture_execute_xfail "m68k-*-*"
}
if [istarget "spu-*-*"] {
# The SPU single-precision floating point format does not
# support subnormals.
return 1
}
if { [istarget "tic6x-*-*"] && [check_effective_target_ti_c67x] } {
# C6X floating point hardware turns denormals to zero in multiplications.
set torture_execute_xfail "tic6x-*-*"

6
gcc/testsuite/gcc.c-torture/execute/ieee/rbug.c
View File

@ -41,14 +41,8 @@ main ()
k = 0x8234508000000001ULL;
x = s (k);
k = (unsigned long long) x;
#ifdef __SPU__
/* SPU float rounds towards zero. */
if (k != 0x8234500000000000ULL)
abort ();
#else
if (k != 0x8234510000000000ULL)
abort ();
#endif
exit (0);
}

1
gcc/testsuite/gcc.c-torture/execute/pr39228.c
View File

@ -1,5 +1,4 @@
/* { dg-add-options ieee } */
/* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
extern void abort (void);

2
gcc/testsuite/gcc.dg/20020312-2.c
View File

@ -96,8 +96,6 @@ extern void abort (void);
/* No pic register. */
#elif defined(__m32c__)
/* No pic register. */
#elif defined(__SPU__)
# define PIC_REG "126"
#elif defined (__frv__)
# ifdef __FRV_FDPIC__
# define PIC_REG "gr15"

1
gcc/testsuite/gcc.dg/20030702-1.c
View File

@ -2,7 +2,6 @@
correctly in combine. */
/* { dg-do compile { target fpic } } */
/* { dg-options "-O2 -fpic -fprofile-arcs" } */
/* { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } */
/* { dg-require-profiling "-fprofile-generate" } */
int fork (void);

6
gcc/testsuite/gcc.dg/and-1.c
View File

@ -1,8 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler "and" { target powerpc*-*-* spu-*-* } } } */
/* There should be no nand for this testcase (for either PPC or SPU). */
/* { dg-final { scan-assembler-not "nand" { target powerpc*-*-* spu-*-* } } } */
/* { dg-final { scan-assembler "and" { target powerpc*-*-* } } } */
/* There should be no nand for this testcase (for PPC). */
/* { dg-final { scan-assembler-not "nand" { target powerpc*-*-* } } } */
int f(int y)
{

2
gcc/testsuite/gcc.dg/builtin-inf-1.c
View File

@ -1,7 +1,7 @@
/* { dg-do compile } */
float fi = __builtin_inff();
/* { dg-error "does not support infinity" "INF unsupported" { target pdp11*-*-* vax-*-* spu-*-* } .-1 } */
/* { dg-error "does not support infinity" "INF unsupported" { target pdp11*-*-* vax-*-* } .-1 } */
double di = __builtin_inf();
/* { dg-error "does not support infinity" "INF unsupported" { target pdp11*-*-* vax-*-* } .-1 } */
long double li = __builtin_infl();

2
gcc/testsuite/gcc.dg/builtins-1.c
View File

@ -144,7 +144,7 @@ FPTEST2ARG2_REENT (gamma, int *) /* gamma_r */
FPTEST0 (huge_val)
FPTEST2 (hypot)
FPTEST1 (ilogb)
FPTEST0 (inf) /* { dg-warning "target format does not support infinity" "inf" {target pdp11*-*-* spu-*-*} } */
FPTEST0 (inf) /* { dg-warning "target format does not support infinity" "inf" {target pdp11*-*-* } } */
FPTEST1 (j0)
FPTEST1 (j1)
FPTEST2ARG1 (jn, int)

5
gcc/testsuite/gcc.dg/builtins-43.c
View File

@ -12,20 +12,15 @@ int
main ()
{
double nan = __builtin_nan ("");
#ifndef __SPU__
/* The SPU single-precision floating point format does not support NANs. */
float nanf = __builtin_nanf ("");
#endif
long double nanl = __builtin_nanl ("");
if (!__builtin_isnan (nan))
link_error ();
#ifndef __SPU__
if (!__builtin_isnan (nanf))
link_error ();
if (!__builtin_isnanf (nanf))
link_error ();
#endif
if (!__builtin_isnan (nanl))
link_error ();
if (!__builtin_isnanl (nanl))

7
gcc/testsuite/gcc.dg/builtins-44.c
View File

@ -13,20 +13,15 @@ int
main ()
{
double pinf = __builtin_inf ();
#ifndef __SPU__
/* The SPU single-precision floating point format does not support Inf. */
float pinff = __builtin_inff ();
#endif
long double pinfl = __builtin_infl ();
if (__builtin_isinf (pinf) != 1)
link_error ();
#ifndef __SPU__
if (__builtin_isinf (pinff) != 1)
link_error ();
if (__builtin_isinff (pinff) != 1)
link_error ();
#endif
if (__builtin_isinf (pinfl) != 1)
link_error ();
if (__builtin_isinfl (pinfl) != 1)
@ -34,10 +29,8 @@ main ()
if (__builtin_isinf_sign (-pinf) != -1)
link_error ();
#ifndef __SPU__
if (__builtin_isinf_sign (-pinff) != -1)
link_error ();
#endif
if (__builtin_isinf_sign (-pinfl) != -1)
link_error ();

10
gcc/testsuite/gcc.dg/builtins-45.c
View File

@ -13,34 +13,24 @@ int
main ()
{
double nan = __builtin_nan ("");
#ifndef __SPU__
/* The SPU single-precision floating point format does not support NANs. */
float nanf = __builtin_nanf ("");
#endif
long double nanl = __builtin_nanl ("");
double pinf = __builtin_inf ();
#ifndef __SPU__
/* The SPU single-precision floating point format does not support Inf. */
float pinff = __builtin_inff ();
#endif
long double pinfl = __builtin_infl ();
if (__builtin_finite (pinf))
link_error ();
#ifndef __SPU__
if (__builtin_finitef (pinff))
link_error ();
#endif
if (__builtin_finitel (pinfl))
link_error ();
if (__builtin_finite (nan))
link_error ();
#ifndef __SPU__
if (__builtin_finitef (nanf))
link_error ();
#endif
if (__builtin_finitel (nanl))
link_error ();

1
gcc/testsuite/gcc.dg/float-range-1.c
View File

@ -4,7 +4,6 @@
/* Origin: Joseph Myers <jsm@polyomino.org.uk> */
/* { dg-do compile } */
/* { dg-options "-ansi -pedantic-errors -Woverflow" } */
/* { dg-skip-if "No Inf support" { spu-*-* } } */
void
f (void)

1
gcc/testsuite/gcc.dg/float-range-3.c
View File

@ -1,7 +1,6 @@
/* PR 23572 : warnings for out of range floating-point constants. */
/* { dg-do compile } */
/* { dg-options "-std=c99" } */
/* { dg-skip-if "No Inf support" { spu-*-* } } */
#include <math.h>
#ifndef INFINITY

1
gcc/testsuite/gcc.dg/float-range-4.c
View File

@ -1,7 +1,6 @@
/* PR 23572 : warnings for out of range floating-point constants. */
/* { dg-do compile } */
/* { dg-options "-Wno-overflow -std=c99" } */
/* { dg-skip-if "No Inf support" { spu-*-* } } */
#include <math.h>
#ifndef INFINITY

1
gcc/testsuite/gcc.dg/float-range-5.c
View File

@ -2,7 +2,6 @@
Test that they are NOT pedantic warnings. */
/* { dg-do compile } */
/* { dg-options "-pedantic-errors -std=c99" } */
/* { dg-skip-if "No Inf support" { spu-*-* } } */
#include <math.h>
#ifndef INFINITY

1
gcc/testsuite/gcc.dg/fold-overflow-1.c
View File

@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-require-effective-target int32plus } */
/* { dg-skip-if "No Inf support" { spu-*-* } } */
/* { dg-options "-O -ftrapping-math" } */
/* There should be exactly 2 +Inf in the assembly file. */

2
gcc/testsuite/gcc.dg/format/ms_unnamed-1.c
View File

@ -10,7 +10,7 @@
/* Definition of TItype follows same logic as in gcc.dg/titype-1.c,
but must be a #define to avoid giving the type a name. */
#if (defined(__LP64__) && !defined(__hppa__)) || defined(__SPU__)
#if defined(__LP64__) && !defined(__hppa__)
#define TItype int __attribute__ ((mode (TI)))
#else
#define TItype long

2
gcc/testsuite/gcc.dg/format/unnamed-1.c
View File

@ -10,7 +10,7 @@
/* Definition of TItype follows same logic as in gcc.dg/titype-1.c,
but must be a #define to avoid giving the type a name. */
#if (defined(__LP64__) && !defined(__hppa__)) || defined(__SPU__)
#if defined(__LP64__) && !defined(__hppa__)
#define TItype int __attribute__ ((mode (TI)))
#else
#define TItype long

1
gcc/testsuite/gcc.dg/hex-round-1.c
View File

@ -1,7 +1,6 @@
/* Test for hexadecimal float rounding: bug 21720. */
/* { dg-do link } */
/* { dg-options "-O -std=gnu99" } */
/* { dg-skip-if "SPU float rounds towards zero" { spu-*-* } } */
#include <float.h>

1
gcc/testsuite/gcc.dg/hex-round-2.c
View File

@ -2,7 +2,6 @@
in number. */
/* { dg-do link } */
/* { dg-options "-O -std=gnu99" } */
/* { dg-skip-if "SPU float rounds towards zero" { spu-*-* } } */
#include <float.h>

2
gcc/testsuite/gcc.dg/lower-subreg-1.c
View File

@ -1,4 +1,4 @@
/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */
/* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* tilegx-*-* } } } } } */
/* { dg-options "-O -fdump-rtl-subreg1" } */
/* { dg-additional-options "-mno-stv" { target ia32 } } */
/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } } */

5
gcc/testsuite/gcc.dg/nrv3.c
View File

@ -3,12 +3,7 @@
/* { dg-do compile } */
/* { dg-options "-O -fdump-tree-optimized" } */
#ifdef __SPU__
/* SPU returns aggregates up to 1172 bytes in registers. */
typedef struct { int x[300]; void *y; } S;
#else
typedef struct { int x[20]; void *y; } S;
#endif
typedef struct { int a; S b; } T;
S nrv_candidate (void);
void use_result (S, int);

1
gcc/testsuite/gcc.dg/pr15784-3.c
View File

@ -1,5 +1,4 @@
/* { dg-do compile } */
/* { dg-skip-if "No NaN support" { spu-*-* } } */
/* SH4 without -mieee defaults to -ffinite-math-only. */
/* { dg-options "-fdump-tree-gimple -fno-finite-math-only" } */
/* Test for folding abs(x) where appropriate. */

4
gcc/testsuite/gcc.dg/pr27095.c
View File

@ -19,7 +19,7 @@ main (int argc, char **argv)
memset (x, argc, strlen (x));
return 0;
}
/* { dg-final { scan-assembler-not "(?n)strlen\(.*\n\)+.*strlen" { target { ! { powerpc*-*-darwin* hppa*-*-hpux* ia64-*-hpux* alpha*-*-* spu-*-* tic6x-*-* } } } } } */
/* { dg-final { scan-assembler-not "(?n)strlen\(.*\n\)+.*strlen" { target { ! { powerpc*-*-darwin* hppa*-*-hpux* ia64-*-hpux* alpha*-*-* tic6x-*-* } } } } } */
/* hppa*-*-hpux* has an IMPORT statement for strlen (plus the branch). */
/* *-*-darwin* has something similar. */
/* tic6x emits a comment at the point where the delayed branch happens. */
@ -29,5 +29,3 @@ main (int argc, char **argv)
/* { dg-final { scan-assembler-not "(?n)strlen\(.*\n\)+.*strlen\(.*\n\)+.*strlen\(.*\n\)+.*strlen" { target ia64-*-hpux* } } } */
/* alpha-*-* has a GOT load and the call. */
/* { dg-final { scan-assembler-not "(?n)jsr .*,strlen\(.*\n\)+.*jsr .*,strlen" { target alpha*-*-* } } } */
/* spu-*-* has a branch hint and the call. */
/* { dg-final { scan-assembler-not "(?n)brsl.*,strlen\(.*\n\)+.*brsl.*,strlen" { target spu-*-* } } } */

1
gcc/testsuite/gcc.dg/pr28243.c
View File

@ -4,7 +4,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target fpic } */
/* { dg-options "-O2 -ftracer -fPIC" } */
/* { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } */
struct displayfuncs {
void (*init) ();

1
gcc/testsuite/gcc.dg/pr28796-2.c
View File

@ -1,7 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -funsafe-math-optimizations -fno-finite-math-only -DUNSAFE" } */
/* { dg-add-options ieee } */
/* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
#include "tg-tests.h"

1
gcc/testsuite/gcc.dg/pr30551-3.c
View File

@ -1,7 +1,6 @@
/* PR 30551 -Wmain is enabled by -pedantic-errors. */
/* { dg-do compile } */
/* { dg-options "-pedantic-errors" } */
/* { dg-skip-if "-Wmain not enabled with -pedantic on SPU" { spu-*-* } } */
void main(char a) {} /* { dg-error "first argument of .main. should be .int." "int" } */
/* { dg-error ".main. takes only zero or two arguments" "zero or two" { target *-*-* } .-1 } */
/* { dg-error "return type of .main. is not .int." "return type" { target *-*-* } .-2 } */

1
gcc/testsuite/gcc.dg/pr30551-6.c
View File

@ -1,7 +1,6 @@
/* PR 30551 -Wmain is enabled by -pedantic. */
/* { dg-do compile } */
/* { dg-options "-pedantic" } */
/* { dg-skip-if "-Wmain not enabled with -pedantic on SPU" { spu-*-* } } */
void main(char a) {} /* { dg-warning "first argument of .main. should be .int." "int" } */
/* { dg-warning ".main. takes only zero or two arguments" "zero or two" { target *-*-* } .-1 } */
/* { dg-warning "return type of .main. is not .int." "return type" { target *-*-* } .-2 } */

1
gcc/testsuite/gcc.dg/pr30551.c
View File

@ -1,7 +1,6 @@
/* PR 30551 -Wmain is enabled by -Wall. */
/* { dg-do compile } */
/* { dg-options "-Wall" } */
/* { dg-skip-if "-Wmain not enabled with -Wall on SPU" { spu-*-* } } */
void main(char a) {} /* { dg-warning "first argument of .main. should be .int." "int" } */
/* { dg-warning ".main. takes only zero or two arguments" "zero or two" { target *-*-* } .-1 } */
/* { dg-warning "return type of .main. is not .int." "return type" { target *-*-* } .-2 } */

2
gcc/testsuite/gcc.dg/pr70317.c
View File

@ -1,6 +1,6 @@
/* PR tree-optimization/70317 */
/* { dg-do compile } */
/* { dg-skip-if "No NaN support" { spu*-*-* vax*-*-* pdp11*-*-* } } */
/* { dg-skip-if "No NaN support" { vax*-*-* pdp11*-*-* } } */
/* { dg-options "-O2 -fdump-tree-optimized" } */
/* { dg-additional-options "-fno-common" { target hppa*-*-hpux* } } */

2
gcc/testsuite/gcc.dg/sms-1.c
View File

@ -40,5 +40,5 @@ main ()
return 0;
}
/* { dg-final { scan-rtl-dump-times "SMS succeeded" 1 "sms" { target powerpc*-*-* spu-*-* } } } */
/* { dg-final { scan-rtl-dump-times "SMS succeeded" 1 "sms" { target powerpc*-*-* } } } */

Some files were not shown because too many files have changed in this diff Show More