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[AArch64] Add truncation for partial SVE modes
This patch adds support for "truncating" to a partial SVE vector from either a full SVE vector or a wider partial vector. This truncation is actually a no-op and so should have zero cost in the vector cost model. 2019-11-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (trunc<SVE_HSDI:mode><SVE_PARTIAL_I:mode>2): New pattern. * config/aarch64/aarch64.c (aarch64_integer_truncation_p): New function. (aarch64_sve_adjust_stmt_cost): Call it. gcc/testsuite/ * gcc.target/aarch64/sve/mask_struct_load_1.c: Add --param aarch64-sve-compare-costs=0. * gcc.target/aarch64/sve/mask_struct_load_2.c: Likewise. * gcc.target/aarch64/sve/mask_struct_load_3.c: Likewise. * gcc.target/aarch64/sve/mask_struct_load_4.c: Likewise. * gcc.target/aarch64/sve/mask_struct_load_5.c: Likewise. * gcc.target/aarch64/sve/pack_1.c: Likewise. * gcc.target/aarch64/sve/truncate_1.c: New test. From-SVN: r278344
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Richard Sandiford
Richard Sandiford
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@ -1,3 +1,11 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve.md
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(trunc<SVE_HSDI:mode><SVE_PARTIAL_I:mode>2): New pattern.
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* config/aarch64/aarch64.c (aarch64_integer_truncation_p): New
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function.
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(aarch64_sve_adjust_stmt_cost): Call it.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve.md
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@ -72,6 +72,7 @@
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;; ---- [INT] General unary arithmetic corresponding to rtx codes
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;; ---- [INT] General unary arithmetic corresponding to unspecs
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;; ---- [INT] Sign and zero extension
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;; ---- [INT] Truncation
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;; ---- [INT] Logical inverse
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;; ---- [FP<-INT] General unary arithmetic that maps to unspecs
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;; ---- [FP] General unary arithmetic corresponding to unspecs
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@ -2888,6 +2889,29 @@
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[(set_attr "movprfx" "*,yes,yes")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Truncation
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;; -------------------------------------------------------------------------
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;; The patterns in this section are synthetic.
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;; -------------------------------------------------------------------------
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;; Truncate to a partial SVE vector from either a full vector or a
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;; wider partial vector. This is a no-op, because we can just ignore
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;; the unused upper bits of the source.
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(define_insn_and_split "trunc<SVE_HSDI:mode><SVE_PARTIAL_I:mode>2"
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[(set (match_operand:SVE_PARTIAL_I 0 "register_operand" "=w")
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(truncate:SVE_PARTIAL_I
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(match_operand:SVE_HSDI 1 "register_operand" "w")))]
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"TARGET_SVE && (~<SVE_HSDI:narrower_mask> & <SVE_PARTIAL_I:self_mask>) == 0"
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"#"
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"&& reload_completed"
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[(set (match_dup 0) (match_dup 1))]
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{
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operands[1] = aarch64_replace_reg_mode (operands[1],
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<SVE_PARTIAL_I:MODE>mode);
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}
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Logical inverse
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;; -------------------------------------------------------------------------
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@ -12901,6 +12901,21 @@ aarch64_extending_load_p (stmt_vec_info stmt_info)
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&& DR_IS_READ (STMT_VINFO_DATA_REF (def_stmt_info)));
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}
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/* Return true if STMT_INFO is an integer truncation. */
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static bool
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aarch64_integer_truncation_p (stmt_vec_info stmt_info)
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{
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gassign *assign = dyn_cast <gassign *> (stmt_info->stmt);
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if (!assign || !CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (assign)))
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return false;
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tree lhs_type = TREE_TYPE (gimple_assign_lhs (assign));
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tree rhs_type = TREE_TYPE (gimple_assign_rhs1 (assign));
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return (INTEGRAL_TYPE_P (lhs_type)
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&& INTEGRAL_TYPE_P (rhs_type)
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&& TYPE_PRECISION (lhs_type) < TYPE_PRECISION (rhs_type));
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}
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/* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
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for STMT_INFO, which has cost kind KIND. Adjust the cost as necessary
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for SVE targets. */
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@ -12919,6 +12934,11 @@ aarch64_sve_adjust_stmt_cost (vect_cost_for_stmt kind, stmt_vec_info stmt_info,
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if (kind == vector_stmt && aarch64_extending_load_p (stmt_info))
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stmt_cost = 0;
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/* For similar reasons, vector_stmt integer truncations are a no-op,
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because we can just ignore the unused upper bits of the source. */
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if (kind == vector_stmt && aarch64_integer_truncation_p (stmt_info))
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stmt_cost = 0;
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return stmt_cost;
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}
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@ -1,3 +1,14 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/mask_struct_load_1.c: Add
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--param aarch64-sve-compare-costs=0.
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* gcc.target/aarch64/sve/mask_struct_load_2.c: Likewise.
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* gcc.target/aarch64/sve/mask_struct_load_3.c: Likewise.
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* gcc.target/aarch64/sve/mask_struct_load_4.c: Likewise.
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* gcc.target/aarch64/sve/mask_struct_load_5.c: Likewise.
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* gcc.target/aarch64/sve/pack_1.c: Likewise.
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* gcc.target/aarch64/sve/truncate_1.c: New test.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/load_extend_1.c: New test.
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math --param aarch64-sve-compare-costs=0" } */
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#include <stdint.h>
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math --param aarch64-sve-compare-costs=0" } */
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#include <stdint.h>
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math --param aarch64-sve-compare-costs=0" } */
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#include <stdint.h>
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math --param aarch64-sve-compare-costs=0" } */
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#include <stdint.h>
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
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/* { dg-options "-O2 -ftree-vectorize -ffast-math --param aarch64-sve-compare-costs=0" } */
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#include <stdint.h>
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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/* { dg-options "-O2 -ftree-vectorize --param aarch64-sve-compare-costs=0" } */
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#include <stdint.h>
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44
gcc/testsuite/gcc.target/aarch64/sve/truncate_1.c
Normal file
44
gcc/testsuite/gcc.target/aarch64/sve/truncate_1.c
Normal file
@ -0,0 +1,44 @@
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define TEST_LOOP(TYPE1, TYPE2, SHIFT) \
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void \
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f_##TYPE1##_##TYPE2 (TYPE2 *restrict dst, TYPE1 *restrict src1, \
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TYPE1 *restrict src2, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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dst[i] = (TYPE1) (src1[i] + src2[i]) >> SHIFT; \
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}
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#define TEST_ALL(T) \
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T (uint16_t, uint8_t, 2) \
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T (uint32_t, uint8_t, 18) \
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T (uint64_t, uint8_t, 34) \
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T (uint32_t, uint16_t, 3) \
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T (uint64_t, uint16_t, 19) \
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T (uint64_t, uint32_t, 4)
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TEST_ALL (TEST_LOOP)
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/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.h,} 2 } } */
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/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s,} 4 } } */
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/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 6 } } */
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/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, z[0-9]+\.h, #2\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, z[0-9]+\.s, #18\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.d, z[0-9]+\.d, #34\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, z[0-9]+\.s, #3\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.d, z[0-9]+\.d, #19\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.d, z[0-9]+\.d, #4\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.h,} 1 } } */
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/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.s,} 1 } } */
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/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.d,} 1 } } */
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/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.s,} 1 } } */
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/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.d,} 1 } } */
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/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.d,} 1 } } */
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