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[AArch32] ACLE intrinsics bfloat16 vmmla and vfma<b/t> for AArch32 AdvSIMD
Commit rest of the 43031fbdda7d4edbd607365a4f3bbec069fe3983 content. I screwed up on the "git add" commands there.
This commit is contained in:
Kyrylo Tkachov
parent
9412b35aff
commit
2d22ab64c4
@ -1,3 +1,31 @@
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2020-03-05 Delia Burduv <delia.burduv@arm.com>
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* config/arm/arm_neon.h (vbfmmlaq_f32): New.
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(vbfmlalbq_f32): New.
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(vbfmlaltq_f32): New.
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(vbfmlalbq_lane_f32): New.
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(vbfmlaltq_lane_f32): New.
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(vbfmlalbq_laneq_f32): New.
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(vbfmlaltq_laneq_f32): New.
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* config/arm/arm_neon_builtins.def (vmmla): New.
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(vfmab): New.
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(vfmat): New.
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(vfmab_lane): New.
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(vfmat_lane): New.
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(vfmab_laneq): New.
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(vfmat_laneq): New.
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* config/arm/iterators.md (BF_MA): New int iterator.
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(bt): New int attribute.
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(VQXBF): Copy of VQX with V8BF.
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* config/arm/neon.md (neon_vmmlav8bf): New insn.
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(neon_vfma<bt>v8bf): New insn.
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(neon_vfma<bt>_lanev8bf): New insn.
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(neon_vfma<bt>_laneqv8bf): New expand.
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(neon_vget_high<mode>): Changed iterator to VQXBF.
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* config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
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(UNSPEC_BFMAB): New UNSPEC.
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(UNSPEC_BFMAT): New UNSPEC.
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2020-03-05 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/93399
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@ -19426,6 +19426,59 @@ vcvtq_high_bf16_f32 (bfloat16x8_t inactive, float32x4_t __a)
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return __builtin_neon_vbfcvtv4sf_highv8bf (inactive, __a);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmmlaq_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x8_t __b)
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{
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return __builtin_neon_vmmlav8bf (__r, __a, __b);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmlalbq_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x8_t __b)
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{
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return __builtin_neon_vfmabv8bf (__r, __a, __b);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmlaltq_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x8_t __b)
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{
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return __builtin_neon_vfmatv8bf (__r, __a, __b);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmlalbq_lane_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x4_t __b,
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const int __index)
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{
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return __builtin_neon_vfmab_lanev8bf (__r, __a, __b, __index);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmlaltq_lane_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x4_t __b,
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const int __index)
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{
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return __builtin_neon_vfmat_lanev8bf (__r, __a, __b, __index);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmlalbq_laneq_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x8_t __b,
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const int __index)
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{
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return __builtin_neon_vfmab_laneqv8bf (__r, __a, __b, __index);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vbfmlaltq_laneq_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x8_t __b,
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const int __index)
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{
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return __builtin_neon_vfmat_laneqv8bf (__r, __a, __b, __index);
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}
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#pragma GCC pop_options
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#ifdef __cplusplus
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@ -391,3 +391,12 @@ VAR2 (UNOP, vbfcvt, v4bf, v8bf)
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VAR1 (UNOP, vbfcvt_high, v8bf)
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VAR2 (UNOP, vbfcvtv4sf, v4bf, v8bf)
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VAR1 (BINOP, vbfcvtv4sf_high, v8bf)
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VAR1 (TERNOP, vmmla, v8bf)
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VAR1 (TERNOP, vfmab, v8bf)
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VAR1 (TERNOP, vfmat, v8bf)
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VAR1 (MAC_LANE, vfmab_lane, v8bf)
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VAR1 (MAC_LANE, vfmat_lane, v8bf)
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VAR1 (MAC_LANE, vfmab_laneq, v8bf)
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VAR1 (MAC_LANE, vfmat_laneq, v8bf)
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@ -106,6 +106,9 @@
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;; Quad-width vector modes plus 64-bit elements.
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(define_mode_iterator VQX [V16QI V8HI V8HF V8BF V4SI V4SF V2DI])
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;; Quad-width vector modes plus 64-bit elements and V8BF.
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(define_mode_iterator VQXBF [V16QI V8HI V8HF (V8BF "TARGET_BF16_SIMD") V4SI V4SF V2DI])
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;; Quad-width vector modes without floating-point elements.
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(define_mode_iterator VQI [V16QI V8HI V4SI])
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@ -493,6 +496,8 @@
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(define_int_iterator MATMUL [UNSPEC_MATMUL_S UNSPEC_MATMUL_U UNSPEC_MATMUL_US])
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(define_int_iterator BF_MA [UNSPEC_BFMAB UNSPEC_BFMAT])
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;;----------------------------------------------------------------------------
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;; Mode attributes
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;;----------------------------------------------------------------------------
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@ -1209,3 +1214,6 @@
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])
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(define_int_attr smlaw_op [(UNSPEC_SMLAWB "smlawb") (UNSPEC_SMLAWT "smlawt")])
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;; An iterator for VFMA<bt>
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(define_int_attr bt [(UNSPEC_BFMAB "b") (UNSPEC_BFMAT "t")])
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@ -3924,7 +3924,7 @@ if (BYTES_BIG_ENDIAN)
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(define_expand "neon_vget_high<mode>"
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[(match_operand:<V_HALF> 0 "s_register_operand")
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(match_operand:VQX 1 "s_register_operand")]
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(match_operand:VQXBF 1 "s_register_operand")]
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"TARGET_NEON"
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{
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emit_move_insn (operands[0],
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@ -6737,3 +6737,64 @@ if (BYTES_BIG_ENDIAN)
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"TARGET_BF16_FP"
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""
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)
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(define_insn "neon_vmmlav8bf"
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[(set (match_operand:V4SF 0 "register_operand" "=w")
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(plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
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(unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w")
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(match_operand:V8BF 3 "register_operand" "w")]
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UNSPEC_BFMMLA)))]
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"TARGET_BF16_SIMD"
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"vmmla.bf16\\t%q0, %q2, %q3"
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[(set_attr "type" "neon_fp_mla_s_q")]
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)
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(define_insn "neon_vfma<bt>v8bf"
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[(set (match_operand:V4SF 0 "register_operand" "=w")
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(plus: V4SF (match_operand:V4SF 1 "register_operand" "0")
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(unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w")
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(match_operand:V8BF 3 "register_operand" "w")]
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BF_MA)))]
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"TARGET_BF16_SIMD"
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"vfma<bt>.bf16\\t%q0, %q2, %q3"
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[(set_attr "type" "neon_fp_mla_s_q")]
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)
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(define_insn "neon_vfma<bt>_lanev8bf"
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[(set (match_operand:V4SF 0 "register_operand" "=w")
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(plus: V4SF (match_operand:V4SF 1 "register_operand" "0")
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(unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w")
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(match_operand:V4BF 3 "register_operand" "x")
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(match_operand:SI 4 "const_int_operand" "n")]
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BF_MA)))]
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"TARGET_BF16_SIMD"
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"vfma<bt>.bf16\\t%q0, %q2, %P3[%c4]"
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[(set_attr "type" "neon_fp_mla_s_scalar_q")]
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)
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(define_expand "neon_vfma<bt>_laneqv8bf"
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[(set (match_operand:V4SF 0 "register_operand" "=w")
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(plus: V4SF (match_operand:V4SF 1 "register_operand" "0")
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(unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w")
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(match_operand:V8BF 3 "register_operand" "x")
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(match_operand:SI 4 "const_int_operand" "n")]
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BF_MA)))]
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"TARGET_BF16_SIMD"
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{
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int lane = INTVAL (operands[4]);
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gcc_assert (IN_RANGE(lane, 0, 7));
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if (lane < 4)
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{
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emit_insn (gen_neon_vfma<bt>_lanev8bf (operands[0], operands[1], operands[2], operands[3], operands[4]));
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}
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else
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{
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rtx op_highpart = gen_reg_rtx (V4BFmode);
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emit_insn (gen_neon_vget_highv8bf (op_highpart, operands[3]));
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operands[4] = GEN_INT (lane - 4);
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emit_insn (gen_neon_vfma<bt>_lanev8bf (operands[0], operands[1], operands[2], op_highpart, operands[4]));
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}
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DONE;
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}
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[(set_attr "type" "neon_fp_mla_s_scalar_q")]
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)
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@ -508,4 +508,7 @@
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UNSPEC_MATMUL_US
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UNSPEC_BFCVT
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UNSPEC_BFCVT_HIGH
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UNSPEC_BFMMLA
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UNSPEC_BFMAB
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UNSPEC_BFMAT
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])
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