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Patch to fix sparc multiply failures, reported by Laurent Bonnaud.
* sparc.md (mulsidi3): Call const v8plus and v8plus routines. (mulsidi3_v8plus, const_mulsidi3_v8plus): Delete asterisk from name. (smuldi3_highpart): Call const v8plus routine. (smulsi3_highpart_v8plus): Renamed from smulsidi3_highpart_v8plus. (const_smulsi3_highpart_v8plus): New pattern. (smulsi3_highpart_sp32): Renamed from smulsidi3_highpart_sp32. (umulsidi3): Call const v8plus routine. (umulsi3_highpart): Handle const before v8plus. Call const v8plus routine. (umulsi3_highpart_v8plus): Renamed from umulsidi3_highpart_v8plus. (umulsi3_highpart_sp32): Renamed from umulsidi3_highpart_sp32. From-SVN: r19470
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@ -1,3 +1,17 @@
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Tue Apr 28 17:53:33 1998 Jim Wilson <wilson@cygnus.com>
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* sparc.md (mulsidi3): Call const v8plus and v8plus routines.
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(mulsidi3_v8plus, const_mulsidi3_v8plus): Delete asterisk from name.
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(smuldi3_highpart): Call const v8plus routine.
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(smulsi3_highpart_v8plus): Renamed from smulsidi3_highpart_v8plus.
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(const_smulsi3_highpart_v8plus): New pattern.
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(smulsi3_highpart_sp32): Renamed from smulsidi3_highpart_sp32.
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(umulsidi3): Call const v8plus routine.
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(umulsi3_highpart): Handle const before v8plus. Call const v8plus
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routine.
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(umulsi3_highpart_v8plus): Renamed from umulsidi3_highpart_v8plus.
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(umulsi3_highpart_sp32): Renamed from umulsidi3_highpart_sp32.
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Tue Apr 28 08:55:26 1998 Michael Meissner <meissner@cygnus.com>
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* m32r.c (*_oper{and|ator}): Change enum arguments and return
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@ -4049,14 +4049,25 @@ return \"srl %1,0,%0\";
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{
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if (CONSTANT_P (operands[2]))
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{
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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emit_insn (gen_const_mulsidi3 (operands[0], operands[1], operands[2]));
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DONE;
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}
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
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DONE;
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}
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}")
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;; V9 puts the 64 bit product in a 64 bit register. Only out or global
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;; registers can hold 64 bit values in the V8plus environment.
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(define_insn "*mulsidi3_v8plus"
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(define_insn "mulsidi3_v8plus"
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[(set (match_operand:DI 0 "register_operand" "=h,r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
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@ -4067,7 +4078,7 @@ return \"srl %1,0,%0\";
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smul %1,%2,%3\;srlx %3,32,%H0\;mov %3,%L0"
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[(set_attr "length" "2,3")])
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(define_insn "*const_mulsidi3_v8plus"
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(define_insn "const_mulsidi3_v8plus"
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[(set (match_operand:DI 0 "register_operand" "=h,r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
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(match_operand:SI 2 "small_int" "I,I")))
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@ -4117,18 +4128,26 @@ return \"srl %1,0,%0\";
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{
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if (CONSTANT_P (operands[2]))
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{
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
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operands[1],
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operands[2],
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GEN_INT (32)));
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DONE;
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}
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emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
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DONE;
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}
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_smulsidi3_highpart_v8plus (operands[0], operands[1],
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operands[2], GEN_INT (32)));
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emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
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operands[2], GEN_INT (32)));
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DONE;
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}
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}")
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(define_insn "smulsidi3_highpart_v8plus"
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(define_insn "smulsi3_highpart_v8plus"
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[(set (match_operand:SI 0 "register_operand" "=h,r")
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
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@ -4141,7 +4160,20 @@ return \"srl %1,0,%0\";
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smul %1,%2,%4\;srlx %4,%3,%0"
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[(set_attr "length" "2")])
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(define_insn "*smulsidi3_highpart_sp32"
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(define_insn "const_smulsi3_highpart_v8plus"
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[(set (match_operand:SI 0 "register_operand" "=h,r")
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
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(match_operand:SI 2 "register_operand" "r,r"))
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(match_operand:SI 3 "const_int_operand" "i,i"))))
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(clobber (match_scratch:SI 4 "=X,&h"))]
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"TARGET_V8PLUS"
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"@
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smul %1,%2,%0\;srlx %0,%3,%0
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smul %1,%2,%4\;srlx %4,%3,%0"
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[(set_attr "length" "2")])
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(define_insn "*smulsi3_highpart_sp32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
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@ -4170,6 +4202,12 @@ return \"srl %1,0,%0\";
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{
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if (CONSTANT_P (operands[2]))
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{
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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emit_insn (gen_const_umulsidi3 (operands[0], operands[1], operands[2]));
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DONE;
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}
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@ -4239,20 +4277,28 @@ return \"srl %1,0,%0\";
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"TARGET_HARD_MUL"
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"
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{
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_umulsidi3_highpart_v8plus (operands[0], operands[1],
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operands[2], GEN_INT (32)));
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DONE;
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}
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if (CONSTANT_P (operands[2]))
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{
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
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operands[1],
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operands[2],
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GEN_INT (32)));
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DONE;
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}
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emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
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DONE;
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}
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if (TARGET_V8PLUS)
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{
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emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
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operands[2], GEN_INT (32)));
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DONE;
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}
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}")
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(define_insn "umulsidi3_highpart_v8plus"
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(define_insn "umulsi3_highpart_v8plus"
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[(set (match_operand:SI 0 "register_operand" "=h,r")
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(truncate:SI
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(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
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@ -4278,7 +4324,7 @@ return \"srl %1,0,%0\";
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umul %1,%2,%4\;srlx %4,%3,%0"
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[(set_attr "length" "2")])
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(define_insn "*umulsidi3_highpart_sp32"
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(define_insn "*umulsi3_highpart_sp32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(truncate:SI
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(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
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