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Enable QI/HImode vector moves
2019-12-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (VEC_1REG_MODE): Remove V64QI and V64HI. (VEC_1REG_ALT): Likewise. (VEC_ALL1REG_MODE): New mode iterator. (VEC_1REG_INT_MODE): Remove V64QI and V64HI. (VEC_1REG_INT_ALT): Likewise. (VEC_ALL1REG_INT_MODE): New mode interator. (VEC_ALL1REG_INT_ALT): Likewise. (VEC_REG_MODE): Remove V64QI and V64HI. (VEC_ALLREG_MODE): New mode interator. (vec_merge): Change to VEC_ALLREG_MODE. (vec_merge_with_clobber): Likewise. (vec_merge_with_vcc): Likewise. (mov<mode>): Likewise. (mov<mode>_unspec): Likewise. (*mov<mode>): Change to VEC_ALL1REG_MODE. (mov<mode>_exec): Likewise. (*mov<mode>_exec_match): Likewise. (mov<mode>_sgprbase): Likewise. (reload_in<mode>): Change to VEC_ALLREG_MODE. (reload_out<mode>): Likewise. (scalar address splits): Likewise. (*vec_set<mode>): Change to VEC_ALL1REG_MODE. (vec_set<mode>): Change to VEC_ALLREG_MODE. (*vec_set<mode>_1): Change to VEC_ALL1REG_MODE. (vec_duplicate<mode><exec>): Likewise. (vec_extract<mode><scalar_mode>): Likewise. (vec_init<mode><scalar_mode>): Change to VEC_ALLREG_MODE. (gather_load<mode>): Likewise. (gather<mode>_exec): Likewise. (gather<mode>_expr<exec>): Likewise. (gather<mode>_insn_1offset<exec>): Likewise. (gather<mode>_insn_1offset_ds<exec>): Likewise. (gather<mode>_insn_2offsets<exec>): Likewise. (ds_bpermute<mode>): Change to VEC_ALL1REG_MODE. (VEC_INT_MODE): Remove V64QI and V64HI. (vcond_mask_<mode>di): Change to VEC_ALLREG_MODE. (vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Change to VEC_ALL1REG_MODE. (vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise. (vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Likewise. (vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise. (maskload<mode>di): Change to VEC_ALL1REG_MODE. (maskstore<mode>di): Likewise. (mask_gather_load<mode>): Likewise. (mov_from_lane63_<mode>): Likewise. * config/gcn/gcn.c (gcn_vector_mode_supported_p): Renable V64QImode and V64HImode vectorization. (gcn_related_vector_mode): New function. (TARGET_VECTORIZE_RELATED_MODE): New define. From-SVN: r279053
This commit is contained in:
Andrew Stubbs
Andrew Stubbs
parent
2297a38e0c
commit
2b99bed844
@ -1,3 +1,55 @@
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2019-12-06 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md (VEC_1REG_MODE): Remove V64QI and V64HI.
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(VEC_1REG_ALT): Likewise.
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(VEC_ALL1REG_MODE): New mode iterator.
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(VEC_1REG_INT_MODE): Remove V64QI and V64HI.
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(VEC_1REG_INT_ALT): Likewise.
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(VEC_ALL1REG_INT_MODE): New mode interator.
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(VEC_ALL1REG_INT_ALT): Likewise.
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(VEC_REG_MODE): Remove V64QI and V64HI.
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(VEC_ALLREG_MODE): New mode interator.
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(vec_merge): Change to VEC_ALLREG_MODE.
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(vec_merge_with_clobber): Likewise.
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(vec_merge_with_vcc): Likewise.
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(mov<mode>): Likewise.
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(mov<mode>_unspec): Likewise.
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(*mov<mode>): Change to VEC_ALL1REG_MODE.
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(mov<mode>_exec): Likewise.
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(*mov<mode>_exec_match): Likewise.
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(mov<mode>_sgprbase): Likewise.
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(reload_in<mode>): Change to VEC_ALLREG_MODE.
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(reload_out<mode>): Likewise.
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(scalar address splits): Likewise.
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(*vec_set<mode>): Change to VEC_ALL1REG_MODE.
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(vec_set<mode>): Change to VEC_ALLREG_MODE.
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(*vec_set<mode>_1): Change to VEC_ALL1REG_MODE.
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(vec_duplicate<mode><exec>): Likewise.
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(vec_extract<mode><scalar_mode>): Likewise.
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(vec_init<mode><scalar_mode>): Change to VEC_ALLREG_MODE.
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(gather_load<mode>): Likewise.
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(gather<mode>_exec): Likewise.
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(gather<mode>_expr<exec>): Likewise.
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(gather<mode>_insn_1offset<exec>): Likewise.
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(gather<mode>_insn_1offset_ds<exec>): Likewise.
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(gather<mode>_insn_2offsets<exec>): Likewise.
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(ds_bpermute<mode>): Change to VEC_ALL1REG_MODE.
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(VEC_INT_MODE): Remove V64QI and V64HI.
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(vcond_mask_<mode>di): Change to VEC_ALLREG_MODE.
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(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Change to
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VEC_ALL1REG_MODE.
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(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise.
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(vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Likewise.
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(vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise.
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(maskload<mode>di): Change to VEC_ALL1REG_MODE.
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(maskstore<mode>di): Likewise.
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(mask_gather_load<mode>): Likewise.
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(mov_from_lane63_<mode>): Likewise.
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* config/gcn/gcn.c (gcn_vector_mode_supported_p): Renable V64QImode
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and V64HImode vectorization.
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(gcn_related_vector_mode): New function.
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(TARGET_VECTORIZE_RELATED_MODE): New define.
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2019-12-06 Tobias Burnus <tobias@codesourcery.com>
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Kwok Cheung Yeung <kcy@codesourcery.com>
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@ -18,13 +18,19 @@
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; Vector modes for one vector register
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(define_mode_iterator VEC_1REG_MODE
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[V64QI V64HI V64SI V64HF V64SF])
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[V64SI V64HF V64SF])
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(define_mode_iterator VEC_1REG_ALT
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[V64SI V64HF V64SF])
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(define_mode_iterator VEC_ALL1REG_MODE
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[V64QI V64HI V64SI V64HF V64SF])
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(define_mode_iterator VEC_1REG_INT_MODE
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[V64QI V64HI V64SI])
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[V64SI])
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(define_mode_iterator VEC_1REG_INT_ALT
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[V64SI])
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(define_mode_iterator VEC_ALL1REG_INT_MODE
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[V64QI V64HI V64SI])
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(define_mode_iterator VEC_ALL1REG_INT_ALT
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[V64QI V64HI V64SI])
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; Vector modes for two vector registers
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@ -33,6 +39,9 @@
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; All of above
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(define_mode_iterator VEC_REG_MODE
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[V64SI V64HF V64SF ; Single reg
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V64DI V64DF]) ; Double reg
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(define_mode_iterator VEC_ALLREG_MODE
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[V64QI V64HI V64SI V64HF V64SF ; Single reg
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V64DI V64DF]) ; Double reg
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@ -57,38 +66,40 @@
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"" "_exec")
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(define_subst "vec_merge"
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[(set (match_operand:VEC_REG_MODE 0)
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(match_operand:VEC_REG_MODE 1))]
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[(set (match_operand:VEC_ALLREG_MODE 0)
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(match_operand:VEC_ALLREG_MODE 1))]
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""
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[(set (match_dup 0)
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(vec_merge:VEC_REG_MODE
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(vec_merge:VEC_ALLREG_MODE
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(match_dup 1)
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(match_operand:VEC_REG_MODE 3 "gcn_register_or_unspec_operand" "U0")
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(match_operand:VEC_ALLREG_MODE 3
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"gcn_register_or_unspec_operand" "U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" "e")))])
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(define_subst "vec_merge_with_clobber"
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[(set (match_operand:VEC_REG_MODE 0)
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(match_operand:VEC_REG_MODE 1))
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[(set (match_operand:VEC_ALLREG_MODE 0)
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(match_operand:VEC_ALLREG_MODE 1))
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(clobber (match_operand 2))]
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""
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[(set (match_dup 0)
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(vec_merge:VEC_REG_MODE
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(vec_merge:VEC_ALLREG_MODE
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(match_dup 1)
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(match_operand:VEC_REG_MODE 3 "gcn_register_or_unspec_operand" "U0")
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(match_operand:VEC_ALLREG_MODE 3
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"gcn_register_or_unspec_operand" "U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" "e")))
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(clobber (match_dup 2))])
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(define_subst "vec_merge_with_vcc"
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[(set (match_operand:VEC_REG_MODE 0)
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(match_operand:VEC_REG_MODE 1))
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[(set (match_operand:VEC_ALLREG_MODE 0)
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(match_operand:VEC_ALLREG_MODE 1))
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(set (match_operand:DI 2)
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(match_operand:DI 3))]
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""
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[(parallel
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[(set (match_dup 0)
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(vec_merge:VEC_REG_MODE
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(vec_merge:VEC_ALLREG_MODE
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(match_dup 1)
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(match_operand:VEC_REG_MODE 4
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(match_operand:VEC_ALLREG_MODE 4
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"gcn_register_or_unspec_operand" "U0")
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(match_operand:DI 5 "gcn_exec_reg_operand" "e")))
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(set (match_dup 2)
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@ -121,8 +132,8 @@
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; gather/scatter, maskload/store, etc.
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(define_expand "mov<mode>"
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[(set (match_operand:VEC_REG_MODE 0 "nonimmediate_operand")
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(match_operand:VEC_REG_MODE 1 "general_operand"))]
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[(set (match_operand:VEC_ALLREG_MODE 0 "nonimmediate_operand")
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(match_operand:VEC_ALLREG_MODE 1 "general_operand"))]
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""
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{
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if (MEM_P (operands[0]) && !lra_in_progress && !reload_completed)
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@ -160,28 +171,28 @@
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; A pseudo instruction that helps LRA use the "U0" constraint.
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(define_insn "mov<mode>_unspec"
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[(set (match_operand:VEC_REG_MODE 0 "nonimmediate_operand" "=v")
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(match_operand:VEC_REG_MODE 1 "gcn_unspec_operand" " U"))]
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[(set (match_operand:VEC_ALLREG_MODE 0 "nonimmediate_operand" "=v")
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(match_operand:VEC_ALLREG_MODE 1 "gcn_unspec_operand" " U"))]
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""
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""
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[(set_attr "type" "unknown")
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(set_attr "length" "0")])
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(define_insn "*mov<mode>"
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[(set (match_operand:VEC_1REG_MODE 0 "nonimmediate_operand" "=v,v")
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(match_operand:VEC_1REG_MODE 1 "general_operand" "vA,B"))]
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[(set (match_operand:VEC_ALL1REG_MODE 0 "nonimmediate_operand" "=v,v")
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(match_operand:VEC_ALL1REG_MODE 1 "general_operand" "vA,B"))]
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""
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"v_mov_b32\t%0, %1"
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[(set_attr "type" "vop1,vop1")
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(set_attr "length" "4,8")])
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(define_insn "mov<mode>_exec"
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[(set (match_operand:VEC_1REG_MODE 0 "nonimmediate_operand"
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[(set (match_operand:VEC_ALL1REG_MODE 0 "nonimmediate_operand"
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"=v, v, v, v, v, m")
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(vec_merge:VEC_1REG_MODE
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(match_operand:VEC_1REG_MODE 1 "general_operand"
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(vec_merge:VEC_ALL1REG_MODE
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(match_operand:VEC_ALL1REG_MODE 1 "general_operand"
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"vA, B, v,vA, m, v")
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(match_operand:VEC_1REG_MODE 3 "gcn_alu_or_unspec_operand"
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(match_operand:VEC_ALL1REG_MODE 3 "gcn_alu_or_unspec_operand"
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"U0,U0,vA,vA,U0,U0")
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(match_operand:DI 2 "register_operand" " e, e,cV,Sv, e, e")))
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(clobber (match_scratch:V64DI 4 "=X, X, X, X,&v,&v"))]
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@ -200,9 +211,10 @@
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; read/modify/write which is necessary for maskstore.
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;(define_insn "*mov<mode>_exec_match"
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; [(set (match_operand:VEC_1REG_MODE 0 "nonimmediate_operand" "=v,v, v, m")
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; (vec_merge:VEC_1REG_MODE
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; (match_operand:VEC_1REG_MODE 1 "general_operand" "vA,B, m, v")
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; [(set (match_operand:VEC_ALL1REG_MODE 0 "nonimmediate_operand"
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; "=v,v, v, m")
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; (vec_merge:VEC_ALL1REG_MODE
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; (match_operand:VEC_ALL1REG_MODE 1 "general_operand" "vA,B, m, v")
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; (match_dup 0)
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; (match_operand:DI 2 "gcn_exec_reg_operand" " e,e, e, e")))
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; (clobber (match_scratch:V64DI 3 "=X,X,&v,&v"))]
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@ -304,9 +316,11 @@
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; flat_load v, vT
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(define_insn "mov<mode>_sgprbase"
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[(set (match_operand:VEC_1REG_MODE 0 "nonimmediate_operand" "= v, v, v, m")
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(unspec:VEC_1REG_MODE
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[(match_operand:VEC_1REG_MODE 1 "general_operand" " vA,vB, m, v")]
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[(set (match_operand:VEC_ALL1REG_MODE 0 "nonimmediate_operand"
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"= v, v, v, m")
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(unspec:VEC_ALL1REG_MODE
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[(match_operand:VEC_ALL1REG_MODE 1 "general_operand"
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" vA,vB, m, v")]
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UNSPEC_SGPRBASE))
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(clobber (match_operand:V64DI 2 "register_operand" "=&v,&v,&v,&v"))]
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"lra_in_progress || reload_completed"
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@ -339,8 +353,8 @@
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; gcn_secondary_reload. It allows a reload with a scratch register.
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(define_expand "reload_in<mode>"
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[(set (match_operand:VEC_REG_MODE 0 "register_operand" "= v")
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(match_operand:VEC_REG_MODE 1 "memory_operand" " m"))
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[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand" "= v")
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(match_operand:VEC_ALLREG_MODE 1 "memory_operand" " m"))
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(clobber (match_operand:V64DI 2 "register_operand" "=&v"))]
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""
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{
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@ -351,8 +365,8 @@
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; reload_out is similar to reload_in, above.
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(define_expand "reload_out<mode>"
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[(set (match_operand:VEC_REG_MODE 0 "memory_operand" "= m")
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(match_operand:VEC_REG_MODE 1 "register_operand" " v"))
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[(set (match_operand:VEC_ALLREG_MODE 0 "memory_operand" "= m")
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(match_operand:VEC_ALLREG_MODE 1 "register_operand" " v"))
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(clobber (match_operand:V64DI 2 "register_operand" "=&v"))]
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""
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{
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@ -363,9 +377,9 @@
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; Expand scalar addresses into gather/scatter patterns
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(define_split
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[(set (match_operand:VEC_REG_MODE 0 "memory_operand")
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(unspec:VEC_REG_MODE
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[(match_operand:VEC_REG_MODE 1 "general_operand")]
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[(set (match_operand:VEC_ALLREG_MODE 0 "memory_operand")
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(unspec:VEC_ALLREG_MODE
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[(match_operand:VEC_ALLREG_MODE 1 "general_operand")]
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UNSPEC_SGPRBASE))
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(clobber (match_scratch:V64DI 2))]
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""
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@ -381,10 +395,10 @@
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})
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(define_split
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[(set (match_operand:VEC_REG_MODE 0 "memory_operand")
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(vec_merge:VEC_REG_MODE
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(match_operand:VEC_REG_MODE 1 "general_operand")
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(match_operand:VEC_REG_MODE 2 "")
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[(set (match_operand:VEC_ALLREG_MODE 0 "memory_operand")
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(vec_merge:VEC_ALLREG_MODE
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(match_operand:VEC_ALLREG_MODE 1 "general_operand")
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(match_operand:VEC_ALLREG_MODE 2 "")
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(match_operand:DI 3 "gcn_exec_reg_operand")))
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(clobber (match_scratch:V64DI 4))]
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""
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@ -402,14 +416,14 @@
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})
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(define_split
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[(set (match_operand:VEC_REG_MODE 0 "nonimmediate_operand")
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(unspec:VEC_REG_MODE
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[(match_operand:VEC_REG_MODE 1 "memory_operand")]
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[(set (match_operand:VEC_ALLREG_MODE 0 "nonimmediate_operand")
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(unspec:VEC_ALLREG_MODE
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[(match_operand:VEC_ALLREG_MODE 1 "memory_operand")]
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UNSPEC_SGPRBASE))
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(clobber (match_scratch:V64DI 2))]
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""
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[(set (match_dup 0)
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(unspec:VEC_REG_MODE [(match_dup 5) (match_dup 6) (match_dup 7)
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(unspec:VEC_ALLREG_MODE [(match_dup 5) (match_dup 6) (match_dup 7)
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(mem:BLK (scratch))]
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UNSPEC_GATHER))]
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{
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@ -421,18 +435,18 @@
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})
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(define_split
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[(set (match_operand:VEC_REG_MODE 0 "nonimmediate_operand")
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(vec_merge:VEC_REG_MODE
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(match_operand:VEC_REG_MODE 1 "memory_operand")
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(match_operand:VEC_REG_MODE 2 "")
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[(set (match_operand:VEC_ALLREG_MODE 0 "nonimmediate_operand")
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(vec_merge:VEC_ALLREG_MODE
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(match_operand:VEC_ALLREG_MODE 1 "memory_operand")
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(match_operand:VEC_ALLREG_MODE 2 "")
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(match_operand:DI 3 "gcn_exec_reg_operand")))
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(clobber (match_scratch:V64DI 4))]
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""
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[(set (match_dup 0)
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(vec_merge:VEC_REG_MODE
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(unspec:VEC_REG_MODE [(match_dup 5) (match_dup 6) (match_dup 7)
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(mem:BLK (scratch))]
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UNSPEC_GATHER)
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(vec_merge:VEC_ALLREG_MODE
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(unspec:VEC_ALLREG_MODE [(match_dup 5) (match_dup 6) (match_dup 7)
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(mem:BLK (scratch))]
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UNSPEC_GATHER)
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(match_dup 2)
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(match_dup 3)))]
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{
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@ -455,11 +469,11 @@
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; FIXME these should take A immediates
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(define_insn "*vec_set<mode>"
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[(set (match_operand:VEC_1REG_MODE 0 "register_operand" "= v")
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(vec_merge:VEC_1REG_MODE
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||||
(vec_duplicate:VEC_1REG_MODE
|
||||
[(set (match_operand:VEC_ALL1REG_MODE 0 "register_operand" "= v")
|
||||
(vec_merge:VEC_ALL1REG_MODE
|
||||
(vec_duplicate:VEC_ALL1REG_MODE
|
||||
(match_operand:<SCALAR_MODE> 1 "register_operand" " Sv"))
|
||||
(match_operand:VEC_1REG_MODE 3 "gcn_register_or_unspec_operand"
|
||||
(match_operand:VEC_ALL1REG_MODE 3 "gcn_register_or_unspec_operand"
|
||||
" U0")
|
||||
(ashift (const_int 1)
|
||||
(match_operand:SI 2 "gcn_alu_operand" "SvB"))))]
|
||||
@ -489,20 +503,20 @@
|
||||
(set_attr "laneselect" "yes")])
|
||||
|
||||
(define_expand "vec_set<mode>"
|
||||
[(set (match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
(vec_merge:VEC_REG_MODE
|
||||
(vec_duplicate:VEC_REG_MODE
|
||||
[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(vec_merge:VEC_ALLREG_MODE
|
||||
(vec_duplicate:VEC_ALLREG_MODE
|
||||
(match_operand:<SCALAR_MODE> 1 "register_operand"))
|
||||
(match_dup 0)
|
||||
(ashift (const_int 1) (match_operand:SI 2 "gcn_alu_operand"))))]
|
||||
"")
|
||||
|
||||
(define_insn "*vec_set<mode>_1"
|
||||
[(set (match_operand:VEC_1REG_MODE 0 "register_operand" "=v")
|
||||
(vec_merge:VEC_1REG_MODE
|
||||
(vec_duplicate:VEC_1REG_MODE
|
||||
[(set (match_operand:VEC_ALL1REG_MODE 0 "register_operand" "=v")
|
||||
(vec_merge:VEC_ALL1REG_MODE
|
||||
(vec_duplicate:VEC_ALL1REG_MODE
|
||||
(match_operand:<SCALAR_MODE> 1 "register_operand" "Sv"))
|
||||
(match_operand:VEC_1REG_MODE 3 "gcn_register_or_unspec_operand"
|
||||
(match_operand:VEC_ALL1REG_MODE 3 "gcn_register_or_unspec_operand"
|
||||
"U0")
|
||||
(match_operand:SI 2 "const_int_operand" " i")))]
|
||||
"((unsigned) exact_log2 (INTVAL (operands[2])) < 64)"
|
||||
@ -534,9 +548,9 @@
|
||||
(set_attr "laneselect" "yes")])
|
||||
|
||||
(define_insn "vec_duplicate<mode><exec>"
|
||||
[(set (match_operand:VEC_1REG_MODE 0 "register_operand" "=v")
|
||||
(vec_duplicate:VEC_1REG_MODE
|
||||
(match_operand:<SCALAR_MODE> 1 "gcn_alu_operand" "SvB")))]
|
||||
[(set (match_operand:VEC_ALL1REG_MODE 0 "register_operand" "=v")
|
||||
(vec_duplicate:VEC_ALL1REG_MODE
|
||||
(match_operand:<SCALAR_MODE> 1 "gcn_alu_operand" "SvB")))]
|
||||
""
|
||||
"v_mov_b32\t%0, %1"
|
||||
[(set_attr "type" "vop3a")
|
||||
@ -554,8 +568,8 @@
|
||||
(define_insn "vec_extract<mode><scalar_mode>"
|
||||
[(set (match_operand:<SCALAR_MODE> 0 "register_operand" "=Sg")
|
||||
(vec_select:<SCALAR_MODE>
|
||||
(match_operand:VEC_1REG_MODE 1 "register_operand" " v")
|
||||
(parallel [(match_operand:SI 2 "gcn_alu_operand" "SvB")])))]
|
||||
(match_operand:VEC_ALL1REG_MODE 1 "register_operand" " v")
|
||||
(parallel [(match_operand:SI 2 "gcn_alu_operand" "SvB")])))]
|
||||
""
|
||||
"v_readlane_b32 %0, %1, %2"
|
||||
[(set_attr "type" "vop3a")
|
||||
@ -576,7 +590,7 @@
|
||||
(set_attr "laneselect" "yes")])
|
||||
|
||||
(define_expand "vec_init<mode><scalar_mode>"
|
||||
[(match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(match_operand 1)]
|
||||
""
|
||||
{
|
||||
@ -618,7 +632,7 @@
|
||||
;; - Multiple forms of address expression are supported, below.
|
||||
|
||||
(define_expand "gather_load<mode>"
|
||||
[(match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(match_operand:DI 1 "register_operand")
|
||||
(match_operand 2 "register_operand")
|
||||
(match_operand 3 "immediate_operand")
|
||||
@ -640,7 +654,7 @@
|
||||
})
|
||||
|
||||
(define_expand "gather<mode>_exec"
|
||||
[(match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(match_operand:DI 1 "register_operand")
|
||||
(match_operand:V64SI 2 "register_operand")
|
||||
(match_operand 3 "immediate_operand")
|
||||
@ -669,8 +683,8 @@
|
||||
|
||||
; Allow any address expression
|
||||
(define_expand "gather<mode>_expr<exec>"
|
||||
[(set (match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
(unspec:VEC_REG_MODE
|
||||
[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(unspec:VEC_ALLREG_MODE
|
||||
[(match_operand 1 "")
|
||||
(match_operand 2 "immediate_operand")
|
||||
(match_operand 3 "immediate_operand")
|
||||
@ -680,8 +694,8 @@
|
||||
{})
|
||||
|
||||
(define_insn "gather<mode>_insn_1offset<exec>"
|
||||
[(set (match_operand:VEC_REG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_REG_MODE
|
||||
[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_ALLREG_MODE
|
||||
[(plus:V64DI (match_operand:V64DI 1 "register_operand" " v")
|
||||
(vec_duplicate:V64DI
|
||||
(match_operand 2 "immediate_operand" " n")))
|
||||
@ -719,8 +733,8 @@
|
||||
(set_attr "length" "12")])
|
||||
|
||||
(define_insn "gather<mode>_insn_1offset_ds<exec>"
|
||||
[(set (match_operand:VEC_REG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_REG_MODE
|
||||
[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_ALLREG_MODE
|
||||
[(plus:V64SI (match_operand:V64SI 1 "register_operand" " v")
|
||||
(vec_duplicate:V64SI
|
||||
(match_operand 2 "immediate_operand" " n")))
|
||||
@ -741,8 +755,8 @@
|
||||
(set_attr "length" "12")])
|
||||
|
||||
(define_insn "gather<mode>_insn_2offsets<exec>"
|
||||
[(set (match_operand:VEC_REG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_REG_MODE
|
||||
[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_ALLREG_MODE
|
||||
[(plus:V64DI
|
||||
(plus:V64DI
|
||||
(vec_duplicate:V64DI
|
||||
@ -782,7 +796,7 @@
|
||||
(match_operand 1 "register_operand")
|
||||
(match_operand 2 "immediate_operand")
|
||||
(match_operand:SI 3 "gcn_alu_operand")
|
||||
(match_operand:VEC_REG_MODE 4 "register_operand")]
|
||||
(match_operand:VEC_ALLREG_MODE 4 "register_operand")]
|
||||
""
|
||||
{
|
||||
rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[0],
|
||||
@ -804,7 +818,7 @@
|
||||
(match_operand 1 "register_operand")
|
||||
(match_operand 2 "immediate_operand")
|
||||
(match_operand:SI 3 "gcn_alu_operand")
|
||||
(match_operand:VEC_REG_MODE 4 "register_operand")
|
||||
(match_operand:VEC_ALLREG_MODE 4 "register_operand")
|
||||
(match_operand:DI 5 "gcn_exec_reg_operand")]
|
||||
""
|
||||
{
|
||||
@ -832,7 +846,7 @@
|
||||
[(set (mem:BLK (scratch))
|
||||
(unspec:BLK
|
||||
[(match_operand:V64DI 0 "")
|
||||
(match_operand:VEC_REG_MODE 1 "register_operand")
|
||||
(match_operand:VEC_ALLREG_MODE 1 "register_operand")
|
||||
(match_operand 2 "immediate_operand")
|
||||
(match_operand 3 "immediate_operand")]
|
||||
UNSPEC_SCATTER))]
|
||||
@ -845,7 +859,7 @@
|
||||
[(plus:V64DI (match_operand:V64DI 0 "register_operand" "v")
|
||||
(vec_duplicate:V64DI
|
||||
(match_operand 1 "immediate_operand" "n")))
|
||||
(match_operand:VEC_REG_MODE 2 "register_operand" "v")
|
||||
(match_operand:VEC_ALLREG_MODE 2 "register_operand" "v")
|
||||
(match_operand 3 "immediate_operand" "n")
|
||||
(match_operand 4 "immediate_operand" "n")]
|
||||
UNSPEC_SCATTER))]
|
||||
@ -883,7 +897,7 @@
|
||||
[(plus:V64SI (match_operand:V64SI 0 "register_operand" "v")
|
||||
(vec_duplicate:V64SI
|
||||
(match_operand 1 "immediate_operand" "n")))
|
||||
(match_operand:VEC_REG_MODE 2 "register_operand" "v")
|
||||
(match_operand:VEC_ALLREG_MODE 2 "register_operand" "v")
|
||||
(match_operand 3 "immediate_operand" "n")
|
||||
(match_operand 4 "immediate_operand" "n")]
|
||||
UNSPEC_SCATTER))]
|
||||
@ -910,7 +924,7 @@
|
||||
(match_operand:V64SI 1 "register_operand" " v")))
|
||||
(vec_duplicate:V64DI (match_operand 2 "immediate_operand"
|
||||
" n")))
|
||||
(match_operand:VEC_REG_MODE 3 "register_operand" " v")
|
||||
(match_operand:VEC_ALLREG_MODE 3 "register_operand" " v")
|
||||
(match_operand 4 "immediate_operand" " n")
|
||||
(match_operand 5 "immediate_operand" " n")]
|
||||
UNSPEC_SCATTER))]
|
||||
@ -941,11 +955,11 @@
|
||||
;; {{{ Permutations
|
||||
|
||||
(define_insn "ds_bpermute<mode>"
|
||||
[(set (match_operand:VEC_1REG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_1REG_MODE
|
||||
[(match_operand:VEC_1REG_MODE 2 "register_operand" " v")
|
||||
(match_operand:V64SI 1 "register_operand" " v")
|
||||
(match_operand:DI 3 "gcn_exec_reg_operand" " e")]
|
||||
[(set (match_operand:VEC_ALL1REG_MODE 0 "register_operand" "=v")
|
||||
(unspec:VEC_ALL1REG_MODE
|
||||
[(match_operand:VEC_ALL1REG_MODE 2 "register_operand" " v")
|
||||
(match_operand:V64SI 1 "register_operand" " v")
|
||||
(match_operand:DI 3 "gcn_exec_reg_operand" " e")]
|
||||
UNSPEC_BPERMUTE))]
|
||||
""
|
||||
"ds_bpermute_b32\t%0, %1, %2\;s_waitcnt\tlgkmcnt(0)"
|
||||
@ -1968,7 +1982,7 @@
|
||||
;; }}}
|
||||
;; {{{ ALU generic case
|
||||
|
||||
(define_mode_iterator VEC_INT_MODE [V64QI V64HI V64SI V64DI])
|
||||
(define_mode_iterator VEC_INT_MODE [V64SI V64DI])
|
||||
|
||||
(define_code_iterator bitop [and ior xor])
|
||||
(define_code_iterator shiftop [ashift lshiftrt ashiftrt])
|
||||
@ -2552,19 +2566,19 @@
|
||||
|
||||
(define_expand "vcond_mask_<mode>di"
|
||||
[(parallel
|
||||
[(set (match_operand:VEC_REG_MODE 0 "register_operand" "")
|
||||
(vec_merge:VEC_REG_MODE
|
||||
(match_operand:VEC_REG_MODE 1 "gcn_vop3_operand" "")
|
||||
(match_operand:VEC_REG_MODE 2 "gcn_alu_operand" "")
|
||||
(match_operand:DI 3 "register_operand" "")))
|
||||
[(set (match_operand:VEC_ALLREG_MODE 0 "register_operand" "")
|
||||
(vec_merge:VEC_ALLREG_MODE
|
||||
(match_operand:VEC_ALLREG_MODE 1 "gcn_vop3_operand" "")
|
||||
(match_operand:VEC_ALLREG_MODE 2 "gcn_alu_operand" "")
|
||||
(match_operand:DI 3 "register_operand" "")))
|
||||
(clobber (scratch:V64DI))])]
|
||||
""
|
||||
"")
|
||||
|
||||
(define_expand "vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>"
|
||||
[(match_operand:VEC_1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_1REG_MODE 2 "gcn_alu_operand")
|
||||
(define_expand "vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>"
|
||||
[(match_operand:VEC_ALL1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 2 "gcn_alu_operand")
|
||||
(match_operator 3 "comparison_operator"
|
||||
[(match_operand:VEC_1REG_ALT 4 "gcn_alu_operand")
|
||||
(match_operand:VEC_1REG_ALT 5 "gcn_vop3_operand")])]
|
||||
@ -2573,15 +2587,15 @@
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di
|
||||
(tmp, operands[3], operands[4], operands[5]));
|
||||
emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
|
||||
emit_insn (gen_vcond_mask_<VEC_ALL1REG_MODE:mode>di
|
||||
(operands[0], operands[1], operands[2], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec"
|
||||
[(match_operand:VEC_1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_1REG_MODE 2 "gcn_alu_operand")
|
||||
(define_expand "vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec"
|
||||
[(match_operand:VEC_ALL1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 2 "gcn_alu_operand")
|
||||
(match_operator 3 "comparison_operator"
|
||||
[(match_operand:VEC_1REG_ALT 4 "gcn_alu_operand")
|
||||
(match_operand:VEC_1REG_ALT 5 "gcn_vop3_operand")])
|
||||
@ -2591,15 +2605,15 @@
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di_exec
|
||||
(tmp, operands[3], operands[4], operands[5], operands[6]));
|
||||
emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
|
||||
emit_insn (gen_vcond_mask_<VEC_ALL1REG_MODE:mode>di
|
||||
(operands[0], operands[1], operands[2], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>"
|
||||
[(match_operand:VEC_1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_1REG_MODE 2 "gcn_alu_operand")
|
||||
(define_expand "vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>"
|
||||
[(match_operand:VEC_ALL1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 2 "gcn_alu_operand")
|
||||
(match_operator 3 "comparison_operator"
|
||||
[(match_operand:VEC_1REG_INT_ALT 4 "gcn_alu_operand")
|
||||
(match_operand:VEC_1REG_INT_ALT 5 "gcn_vop3_operand")])]
|
||||
@ -2608,15 +2622,15 @@
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di
|
||||
(tmp, operands[3], operands[4], operands[5]));
|
||||
emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
|
||||
emit_insn (gen_vcond_mask_<VEC_ALL1REG_MODE:mode>di
|
||||
(operands[0], operands[1], operands[2], tmp));
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "vcondu<VEC_1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec"
|
||||
[(match_operand:VEC_1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_1REG_MODE 2 "gcn_alu_operand")
|
||||
(define_expand "vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec"
|
||||
[(match_operand:VEC_ALL1REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 1 "gcn_vop3_operand")
|
||||
(match_operand:VEC_ALL1REG_MODE 2 "gcn_alu_operand")
|
||||
(match_operator 3 "comparison_operator"
|
||||
[(match_operand:VEC_1REG_INT_ALT 4 "gcn_alu_operand")
|
||||
(match_operand:VEC_1REG_INT_ALT 5 "gcn_vop3_operand")])
|
||||
@ -2626,7 +2640,7 @@
|
||||
rtx tmp = gen_reg_rtx (DImode);
|
||||
emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di_exec
|
||||
(tmp, operands[3], operands[4], operands[5], operands[6]));
|
||||
emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
|
||||
emit_insn (gen_vcond_mask_<VEC_ALL1REG_MODE:mode>di
|
||||
(operands[0], operands[1], operands[2], tmp));
|
||||
DONE;
|
||||
})
|
||||
@ -2666,8 +2680,8 @@
|
||||
})
|
||||
|
||||
(define_expand "maskload<mode>di"
|
||||
[(match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_REG_MODE 1 "memory_operand")
|
||||
[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(match_operand:VEC_ALLREG_MODE 1 "memory_operand")
|
||||
(match_operand 2 "")]
|
||||
""
|
||||
{
|
||||
@ -2683,8 +2697,8 @@
|
||||
})
|
||||
|
||||
(define_expand "maskstore<mode>di"
|
||||
[(match_operand:VEC_REG_MODE 0 "memory_operand")
|
||||
(match_operand:VEC_REG_MODE 1 "register_operand")
|
||||
[(match_operand:VEC_ALLREG_MODE 0 "memory_operand")
|
||||
(match_operand:VEC_ALLREG_MODE 1 "register_operand")
|
||||
(match_operand 2 "")]
|
||||
""
|
||||
{
|
||||
@ -2698,7 +2712,7 @@
|
||||
})
|
||||
|
||||
(define_expand "mask_gather_load<mode>"
|
||||
[(match_operand:VEC_REG_MODE 0 "register_operand")
|
||||
[(match_operand:VEC_ALLREG_MODE 0 "register_operand")
|
||||
(match_operand:DI 1 "register_operand")
|
||||
(match_operand 2 "register_operand")
|
||||
(match_operand 3 "immediate_operand")
|
||||
@ -2728,7 +2742,7 @@
|
||||
(match_operand 1 "register_operand")
|
||||
(match_operand 2 "immediate_operand")
|
||||
(match_operand:SI 3 "gcn_alu_operand")
|
||||
(match_operand:VEC_REG_MODE 4 "register_operand")
|
||||
(match_operand:VEC_ALLREG_MODE 4 "register_operand")
|
||||
(match_operand:DI 5 "")]
|
||||
""
|
||||
{
|
||||
@ -2982,9 +2996,9 @@
|
||||
|
||||
; Instructions to move a scalar value from lane 63 of a vector register.
|
||||
(define_insn "mov_from_lane63_<mode>"
|
||||
[(set (match_operand:<SCALAR_MODE> 0 "register_operand" "=Sg,v")
|
||||
[(set (match_operand:<SCALAR_MODE> 0 "register_operand" "=Sg,v")
|
||||
(unspec:<SCALAR_MODE>
|
||||
[(match_operand:VEC_1REG_MODE 1 "register_operand" "v,v")]
|
||||
[(match_operand:VEC_ALL1REG_MODE 1 "register_operand" "v,v")]
|
||||
UNSPEC_MOV_FROM_LANE63))]
|
||||
""
|
||||
"@
|
||||
|
||||
@ -3997,12 +3997,8 @@ gcn_vectorize_vec_perm_const (machine_mode vmode, rtx dst,
|
||||
static bool
|
||||
gcn_vector_mode_supported_p (machine_mode mode)
|
||||
{
|
||||
/* FIXME: Enable V64QImode and V64HImode.
|
||||
We should support these modes, but vector operations are usually
|
||||
assumed to automatically truncate types, and GCN does not. We
|
||||
need to add explicit truncates and/or use SDWA for QI/HI insns. */
|
||||
return (/* mode == V64QImode || mode == V64HImode
|
||||
||*/ mode == V64SImode || mode == V64DImode
|
||||
return (mode == V64QImode || mode == V64HImode
|
||||
|| mode == V64SImode || mode == V64DImode
|
||||
|| mode == V64SFmode || mode == V64DFmode);
|
||||
}
|
||||
|
||||
@ -4032,6 +4028,25 @@ gcn_vectorize_preferred_simd_mode (scalar_mode mode)
|
||||
}
|
||||
}
|
||||
|
||||
/* Implement TARGET_VECTORIZE_RELATED_MODE.
|
||||
|
||||
All GCN vectors are 64-lane, so this is simpler than other architectures.
|
||||
In particular, we do *not* want to match vector bit-size. */
|
||||
|
||||
static opt_machine_mode
|
||||
gcn_related_vector_mode (machine_mode vector_mode, scalar_mode element_mode,
|
||||
poly_uint64 nunits)
|
||||
{
|
||||
if (known_ne (nunits, 0U) && known_ne (nunits, 64U))
|
||||
return VOIDmode;
|
||||
|
||||
machine_mode pref_mode = gcn_vectorize_preferred_simd_mode (element_mode);
|
||||
if (!VECTOR_MODE_P (pref_mode))
|
||||
return VOIDmode;
|
||||
|
||||
return pref_mode;
|
||||
}
|
||||
|
||||
/* Implement TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT.
|
||||
|
||||
Returns the preferred alignment in bits for accesses to vectors of type type
|
||||
@ -6162,6 +6177,8 @@ print_operand (FILE *file, rtx x, int code)
|
||||
#undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
|
||||
#define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
|
||||
gcn_preferred_vector_alignment
|
||||
#undef TARGET_VECTORIZE_RELATED_MODE
|
||||
#define TARGET_VECTORIZE_RELATED_MODE gcn_related_vector_mode
|
||||
#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
|
||||
#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
|
||||
gcn_vectorize_support_vector_misalignment
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user