diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3a322921d1bd..eef35b4b1945 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2014-02-14  Vladimir Makarov  <vmakarov@redhat.com>
+	    Richard Earnshaw  <rearnsha@arm.com>
+
+	PR rtl-optimization/59535
+	* lra-constraints.c (process_alt_operands): Encourage alternative
+	when unassigned pseudo class is superset of the alternative class.
+	(inherit_reload_reg): Don't inherit when optimizing for code size.
+	* config/arm/arm.h (MODE_BASE_REG_CLASS): Add version for LRA
+	returning CORE_REGS for anything but Thumb1 and BASE_REGS for
+	modes not less than 4 for Thumb1.
+
 2014-02-14  Kyle McMartin  <kyle@redhat.com>
 
 	PR pch/60010
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index bed056e5c2bf..d9d3547458e9 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1272,8 +1272,13 @@ enum reg_class
    when addressing quantities in QI or HI mode; if we don't know the
    mode, then we must be conservative.  */
 #define MODE_BASE_REG_CLASS(MODE)					\
-    (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS :      \
-     (((MODE) == SImode) ? BASE_REGS : LO_REGS))
+  (arm_lra_flag								\
+   ? (TARGET_32BIT ? CORE_REGS						\
+      : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS				\
+      : LO_REGS)							\
+   : ((TARGET_ARM || (TARGET_THUMB2 && !optimize_size)) ? CORE_REGS	\
+      : ((MODE) == SImode) ? BASE_REGS					\
+      : LO_REGS))
 
 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
    instead of BASE_REGS.  */
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index 5302321deb71..d3831380feed 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -2112,6 +2112,21 @@ process_alt_operands (int only_alternative)
 		  goto fail;
 		}
 
+	      /* If not assigned pseudo has a class which a subset of
+		 required reg class, it is a less costly alternative
+		 as the pseudo still can get a hard reg of necessary
+		 class.  */
+	      if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
+		  && (cl = get_reg_class (REGNO (op))) != NO_REGS
+		  && ira_class_subset_p[this_alternative][cl])
+		{
+		  if (lra_dump_file != NULL)
+		    fprintf
+		      (lra_dump_file,
+		       "            %d Super set class reg: reject-=3\n", nop);
+		  reject -= 3;
+		}
+
 	      this_alternative_offmemok = offmemok;
 	      if (this_costly_alternative != NO_REGS)
 		{
@@ -4391,6 +4406,9 @@ static bool
 inherit_reload_reg (bool def_p, int original_regno,
 		    enum reg_class cl, rtx insn, rtx next_usage_insns)
 {
+  if (optimize_function_for_size_p (cfun))
+    return false;
+
   enum reg_class rclass = lra_get_allocno_class (original_regno);
   rtx original_reg = regno_reg_rtx[original_regno];
   rtx new_reg, new_insns, usage_insn;