diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7f3ce22cf06e..070fa17a654d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2010-11-16  Nick Clifton  <nickc@redhat.com>
+
+	* config/v850/v850.md (maddsf4): Rename to fmasf4 and use fma
+	rtx_code.
+	(msubsf4): Rename to fmssf4, and use fma.
+	(nmaddsf4): Rename to fnmasf4 and use fma.
+	(nmsubsf4): Rename to fnmssf4 and use fma.
+
 2010-11-16  Joern Rennecke  <amylaar@spamcop.net>
 
 	PR target/44762
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 3a9485522dea..d488b8b9f803 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -2024,24 +2024,23 @@
    (set_attr "type" "fpu")])
 
 ;;; multiply-add
-(define_insn "maddsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-			  (match_operand:SF 2 "register_operand" "r"))
-		 (match_operand:SF 3 "register_operand" "r")))]
+(define_insn "fmasf4"
+  [(set (match_operand:SF         0 "register_operand" "=r")
+	(fma:SF (match_operand:SF 1 "register_operand" "r")
+		(match_operand:SF 2 "register_operand" "r")
+		(match_operand:SF 3 "register_operand" "r")))]
   "TARGET_V850E2V3"
   "maddf.s %2,%1,%3,%0"
   [(set_attr "length" "4")
    (set_attr "cc" "none_0hit")
    (set_attr "type" "fpu")])
 
-
 ;;; multiply-subtract
-(define_insn "msubsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-			   (match_operand:SF 2 "register_operand" "r"))
-		  (match_operand:SF 3 "register_operand" "r")))]
+(define_insn "fmssf4"
+  [(set (match_operand:SF                 0 "register_operand" "=r")
+	(fma:SF (match_operand:SF         1 "register_operand" "r")
+		(match_operand:SF         2 "register_operand" "r")
+		(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
   "TARGET_V850E2V3"
   "msubf.s %2,%1,%3,%0"
   [(set_attr "length" "4")
@@ -2049,11 +2048,11 @@
    (set_attr "type" "fpu")])
 
 ;;; negative-multiply-add
-(define_insn "nmaddsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-				  (match_operand:SF 2 "register_operand" "r"))
-			 (match_operand:SF 3 "register_operand" "r"))))]
+(define_insn "fnmasf4"
+  [(set (match_operand:SF                 0 "register_operand" "=r")
+	(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+		(match_operand:SF         2 "register_operand" "r")
+		(match_operand:SF         3 "register_operand" "r")))]
   "TARGET_V850E2V3"
   "nmaddf.s %2,%1,%3,%0"
   [(set_attr "length" "4")
@@ -2061,11 +2060,11 @@
    (set_attr "type" "fpu")])
 
 ;; negative-multiply-subtract
-(define_insn "nmsubsf4"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "r")
-				   (match_operand:SF 2 "register_operand" "r"))
-			  (match_operand:SF 3 "register_operand" "r"))))]
+(define_insn "fnmssf4"
+  [(set (match_operand:SF                 0 "register_operand" "=r")
+	(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+		(match_operand:SF         2 "register_operand" "r")
+		(neg:SF (match_operand:SF 3 "register_operand" "r"))))]
   "TARGET_V850E2V3"
   "nmsubf.s %2,%1,%3,%0"
   [(set_attr "length" "4")