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altivec.h (vec_adde): New define.
[gcc] 2015-08-18 Bill Schmidt <wschmidt@vnet.linux.ibm.com> * config/rs6000/altivec.h (vec_adde): New define. (vec_addec): Likewise. (vec_double): Likewise. (vec_bperm): Likewise. (vec_gb): Likewise. * config/rs6000/rs6000-builtin.def (ADDE): New BU_ALTIVEC_OVERLOAD_3. (ADDEC): Likewise. (DOUBLE): New BU_VSX_OVERLOAD_1. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add new entries for ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VEC_ADDE, ALTIVEC_BUILTIN_VEC_ADDEC, ALTIVEC_BUILTIN_VEC_ANDC, VSX_BUILTIN_VEC_DOUBLE, ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VEC_SEL, P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_VEC_ORC, and P8V_BUILTIN_VEC_VBPERMQ. [gcc/testsuite] 2015-08-18 Bill Schmidt <wschmidt@vnet.linux.ibm.com> * gcc.target/powerpc/altivec-35.c: New test. * gcc.target/powerpc/p8vector-builtin-8.c: New test. * gcc.target/powerpc/vsx-vector-7.c: New test. From-SVN: r226995
This commit is contained in:
Bill Schmidt
William Schmidt
parent
7940cae431
commit
29ec406adc
@ -1,3 +1,24 @@
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2015-08-18 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
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* config/rs6000/altivec.h (vec_adde): New define.
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(vec_addec): Likewise.
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(vec_double): Likewise.
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(vec_bperm): Likewise.
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(vec_gb): Likewise.
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* config/rs6000/rs6000-builtin.def (ADDE): New
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BU_ALTIVEC_OVERLOAD_3.
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(ADDEC): Likewise.
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(DOUBLE): New BU_VSX_OVERLOAD_1.
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* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add new
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entries for ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VEC_ADDE,
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ALTIVEC_BUILTIN_VEC_ADDEC, ALTIVEC_BUILTIN_VEC_ANDC,
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VSX_BUILTIN_VEC_DOUBLE, ALTIVEC_BUILTIN_VEC_MERGEH,
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ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VEC_NOR,
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ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VEC_XOR,
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ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VEC_SEL,
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P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_VEC_ORC,
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and P8V_BUILTIN_VEC_VBPERMQ.
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2015-08-18 Jason Merrill <jason@redhat.com>
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* print-tree.c (print_node): Handle TREE_BINFO.
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@ -100,6 +100,8 @@
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typed builtins. */
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#define vec_vaddfp __builtin_vec_vaddfp
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#define vec_addc __builtin_vec_addc
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#define vec_adde __builtin_vec_adde
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#define vec_addec __builtin_vec_addec
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#define vec_vaddsws __builtin_vec_vaddsws
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#define vec_vaddshs __builtin_vec_vaddshs
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#define vec_vaddsbs __builtin_vec_vaddsbs
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@ -125,6 +127,7 @@
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#define vec_cts __builtin_vec_cts
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#define vec_ctu __builtin_vec_ctu
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#define vec_cpsgn __builtin_vec_copysign
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#define vec_double __builtin_vec_double
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#define vec_expte __builtin_vec_expte
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#define vec_floor __builtin_vec_floor
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#define vec_loge __builtin_vec_loge
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@ -340,6 +343,7 @@
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#define vec_vaddudm __builtin_vec_vaddudm
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#define vec_vadduqm __builtin_vec_vadduqm
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#define vec_vbpermq __builtin_vec_vbpermq
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#define vec_bperm __builtin_vec_vbpermq
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#define vec_vclz __builtin_vec_vclz
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#define vec_cntlz __builtin_vec_vclz
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#define vec_vclzb __builtin_vec_vclzb
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@ -351,6 +355,7 @@
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#define vec_vsubecuq __builtin_vec_vsubecuq
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#define vec_vsubeuqm __builtin_vec_vsubeuqm
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#define vec_vgbbd __builtin_vec_vgbbd
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#define vec_gb __builtin_vec_vgbbd
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#define vec_vmaxsd __builtin_vec_vmaxsd
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#define vec_vmaxud __builtin_vec_vmaxud
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#define vec_vminsd __builtin_vec_vminsd
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@ -951,6 +951,8 @@ BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CONST)
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before we get to the point about classifying the builtin type. */
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/* 3 argument Altivec overloaded builtins. */
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BU_ALTIVEC_OVERLOAD_3 (ADDE, "adde")
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BU_ALTIVEC_OVERLOAD_3 (ADDEC, "addec")
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BU_ALTIVEC_OVERLOAD_3 (MADD, "madd")
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BU_ALTIVEC_OVERLOAD_3 (MADDS, "madds")
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BU_ALTIVEC_OVERLOAD_3 (MLADD, "mladd")
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@ -1447,6 +1449,9 @@ BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw")
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BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd")
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BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw")
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/* 1 argument VSX overloaded builtin functions. */
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BU_VSX_OVERLOAD_1 (DOUBLE, "double")
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/* VSX builtins that are handled as special cases. */
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BU_VSX_OVERLOAD_X (LD, "ld")
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BU_VSX_OVERLOAD_X (ST, "st")
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@ -810,7 +810,25 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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{ ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW,
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RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
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RS6000_BTI_unsigned_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
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RS6000_BTI_unsigned_V1TI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ,
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RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
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{ ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM,
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RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
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{ ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
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RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
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{ ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ,
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RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI },
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{ ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS,
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@ -979,6 +997,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
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RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC,
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@ -1237,6 +1257,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
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{ VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP,
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RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 },
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{ VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP,
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RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 },
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{ ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF,
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RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
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{ ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI,
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@ -1712,6 +1736,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
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@ -1770,6 +1796,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
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{ ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
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@ -1954,6 +1982,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR,
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@ -1996,6 +2026,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
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RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR,
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@ -2695,6 +2727,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
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{ ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
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RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
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{ ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR,
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@ -2957,6 +2991,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI },
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{ ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
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{ ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
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RS6000_BTI_unsigned_V16QI },
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{ ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI },
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{ ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI,
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@ -3003,6 +3040,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
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{ ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
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RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI },
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{ ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
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RS6000_BTI_bool_V2DI },
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{ ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI,
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RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI,
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RS6000_BTI_unsigned_V2DI },
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{ ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
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RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI },
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{ ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF,
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@ -3765,6 +3808,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
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RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
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RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI,
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RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI,
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RS6000_BTI_unsigned_V16QI, 0 },
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@ -3780,6 +3825,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
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RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
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RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI,
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RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI,
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RS6000_BTI_unsigned_V8HI, 0 },
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@ -3795,6 +3842,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
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RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
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{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
|
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RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
@ -3810,6 +3859,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
|
||||
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
@ -3839,6 +3890,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
|
||||
RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
|
||||
RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
|
||||
@ -3854,6 +3907,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
|
||||
RS6000_BTI_unsigned_V8HI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI,
|
||||
RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
|
||||
@ -3869,6 +3924,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
|
||||
RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
|
||||
@ -3884,6 +3941,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF,
|
||||
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
|
||||
{ P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF,
|
||||
@ -3904,6 +3963,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
|
||||
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
|
||||
RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI,
|
||||
RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
|
||||
RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
|
||||
@ -3919,6 +3980,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
|
||||
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
|
||||
RS6000_BTI_unsigned_V8HI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI,
|
||||
RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
|
||||
RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
|
||||
@ -3934,6 +3997,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
|
||||
RS6000_BTI_unsigned_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI,
|
||||
RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
|
||||
RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
|
||||
@ -3949,6 +4014,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
|
||||
RS6000_BTI_unsigned_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI,
|
||||
RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF,
|
||||
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
|
||||
{ P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF,
|
||||
@ -3984,6 +4051,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
|
||||
{ P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
|
||||
RS6000_BTI_unsigned_V16QI, 0 },
|
||||
{ P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ,
|
||||
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI,
|
||||
RS6000_BTI_unsigned_V16QI, 0 },
|
||||
|
||||
{ P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB,
|
||||
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2015-08-18 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
|
||||
|
||||
* gcc.target/powerpc/altivec-35.c: New test.
|
||||
* gcc.target/powerpc/p8vector-builtin-8.c: New test.
|
||||
* gcc.target/powerpc/vsx-vector-7.c: New test.
|
||||
|
||||
2015-08-18 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
|
||||
|
||||
PR middle-end/36757
|
||||
|
||||
16
gcc/testsuite/gcc.target/powerpc/altivec-35.c
Normal file
16
gcc/testsuite/gcc.target/powerpc/altivec-35.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_altivec_ok } */
|
||||
/* { dg-options "-maltivec -mno-vsx -mno-power8-vector -O0" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
/* Test Altivec built-ins added for version 1.1 of ELFv2 ABI. */
|
||||
|
||||
vector signed int vsia, vsib;
|
||||
|
||||
void foo (vector signed int *vsir)
|
||||
{
|
||||
*vsir++ = vec_addc (vsia, vsib);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "vaddcuw" 1 } } */
|
||||
62
gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
Normal file
62
gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
Normal file
@ -0,0 +1,62 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-options "-mpower8-vector -O2" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
/* Test POWER8 vector built-ins added for version 1.1 of ELFv2 ABI. */
|
||||
|
||||
vector unsigned char vuca, vucb, vucc;
|
||||
vector bool char vbca, vbcb;
|
||||
vector bool short vbsa, vbsb;
|
||||
vector bool int vbia, vbib;
|
||||
vector signed long long vsla, vslb;
|
||||
vector unsigned long long vula, vulb, vulc;
|
||||
vector bool long long vbla, vblb, vblc;
|
||||
vector signed __int128 vsxa, vsxb, vsxc;
|
||||
vector unsigned __int128 vuxa, vuxb, vuxc;
|
||||
vector double vda, vdb;
|
||||
|
||||
void foo (vector unsigned char *vucr,
|
||||
vector bool char *vbcr,
|
||||
vector bool short *vbsr,
|
||||
vector bool int *vbir,
|
||||
vector unsigned long long *vulr,
|
||||
vector bool long long *vblr,
|
||||
vector signed __int128 *vsxr,
|
||||
vector unsigned __int128 *vuxr,
|
||||
vector double *vdr)
|
||||
{
|
||||
*vsxr++ = vec_addc (vsxa, vsxb);
|
||||
*vuxr++ = vec_addc (vuxa, vuxb);
|
||||
*vsxr++ = vec_adde (vsxa, vsxb, vsxc);
|
||||
*vuxr++ = vec_adde (vuxa, vuxb, vuxc);
|
||||
*vsxr++ = vec_addec (vsxa, vsxb, vsxc);
|
||||
*vuxr++ = vec_addec (vuxa, vuxb, vuxc);
|
||||
*vulr++ = vec_bperm (vuxa, vucb);
|
||||
*vbcr++ = vec_eqv (vbca, vbcb);
|
||||
*vbir++ = vec_eqv (vbia, vbib);
|
||||
*vblr++ = vec_eqv (vbla, vblb);
|
||||
*vbsr++ = vec_eqv (vbsa, vbsb);
|
||||
*vucr++ = vec_gb (vuca);
|
||||
*vbcr++ = vec_nand (vbca, vbcb);
|
||||
*vbir++ = vec_nand (vbia, vbib);
|
||||
*vblr++ = vec_nand (vbla, vblb);
|
||||
*vbsr++ = vec_nand (vbsa, vbsb);
|
||||
*vbcr++ = vec_orc (vbca, vbcb);
|
||||
*vbir++ = vec_orc (vbia, vbib);
|
||||
*vblr++ = vec_orc (vbla, vblb);
|
||||
*vbsr++ = vec_orc (vbsa, vbsb);
|
||||
*vblr++ = vec_perm (vbla, vblb, vucc);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "vaddcuq" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vaddeuqm" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vaddecuq" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vbpermq" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxleqv" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "vgbbd" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxlnand" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "xxlorc" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "vperm" 1 } } */
|
||||
|
||||
36
gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c
Normal file
36
gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c
Normal file
@ -0,0 +1,36 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-options "-mvsx -mno-power8-vector -O2" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
/* Test VSX built-ins added for version 1.1 of ELFv2 ABI. */
|
||||
|
||||
vector bool long long vbla, vblb, vblc;
|
||||
vector signed long long vsla;
|
||||
vector unsigned long long vula, vulc;
|
||||
|
||||
void foo (vector bool long long *vblr,
|
||||
vector double *vdr)
|
||||
{
|
||||
*vblr++ = vec_andc (vbla, vblb);
|
||||
*vdr++ = vec_double (vsla);
|
||||
*vdr++ = vec_double (vula);
|
||||
*vblr++ = vec_mergeh (vbla, vblb);
|
||||
*vblr++ = vec_mergel (vbla, vblb);
|
||||
*vblr++ = vec_nor (vbla, vblb);
|
||||
*vblr++ = vec_or (vbla, vblb);
|
||||
*vblr++ = vec_sel (vbla, vblb, vblc);
|
||||
*vblr++ = vec_sel (vbla, vblb, vulc);
|
||||
*vblr++ = vec_xor (vbla, vblb);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "xxlandc" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xvcvsxddp" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xvcvuxddp" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,3" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,0" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxlnor" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxlor" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "xxsel" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "xxlxor" 1 } } */
|
||||
Loading…
x
Reference in New Issue
Block a user