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i386.md (ashlsi3): Revise comments.
* i386.md (ashlsi3): Revise comments. Provide new anonymous
pattern for Pentium and PPro/PII. Reverse constraints in
generic ashlsi3 anonymous pattern.
From-SVN: r25647
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Jeffrey A Law
Jeff Law
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959f3a0667
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24883a4a12
@ -12,6 +12,10 @@ Mon Mar 8 16:04:44 1999 Jim Wilson <wilson@cygnus.com>
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Mon Mar 8 15:27:42 1999 Jeffrey A Law (law@cygnus.com)
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* i386.md (ashlsi3): Revise comments. Provide new anonymous
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pattern for Pentium and PPro/PII. Reverse constraints in
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generic ashlsi3 anonymous pattern.
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* calls.c (initialize_argument_info): Accept a pointer to
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CUMULATIVE_ARGS.
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(expand_call): Pass the address of CUMULATIVE_ARGS.
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@ -4709,10 +4709,6 @@ byte_xor_operation:
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RET;
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}")
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;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg"
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;; On i486, movl/sall appears slightly faster than leal, but the leal
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;; is smaller - use leal for now unless the shift count is 1.
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(define_expand "ashlsi3"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
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@ -4720,19 +4716,20 @@ byte_xor_operation:
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""
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"")
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;; For register destinations:
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;; add == 2 bytes, move == 2 bytes, shift == 3 bytes, lea == 7 bytes
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;; Optimizing for code size:
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;; For regsiter destinations:
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;; add == 2 bytes, move == 2 bytes, shift == 3 bytes, lea == 7 bytes
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;;
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;; lea loses when optimizing for size
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;; lea loses when optimizing for size
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;;
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;; Do the math. If the count is 1, using add, else using sal will
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;; produce the smallest possible code, even when the source and
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;; dest do not match. For a memory destination, sal is the only
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;; choice.
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;; Do the math. If the count is 1, using add, else using sal will
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;; produce the smallest possible code, even when the source and
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;; dest do not match. For a memory destination, sal is the only
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;; choice.
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;;
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;; Do not try to handle case where src and dest do not match. Let regmove
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;; and reload handle them. A mov followed by this insn will generate the
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;; desired size optimized results.
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;; Do not try to handle case where src and dest do not match. Let regmove
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;; and reload handle them. A mov followed by this insn will generate the
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;; desired size optimized results.
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
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@ -4748,11 +4745,144 @@ byte_xor_operation:
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return AS2 (sal%L0,%2,%0);
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}")
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;; For Pentium/Pentium MMX:
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;;
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;; We want to optimize for pairability, but avoid generating AGI stalls.
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;;
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;; If this insn is expected to issue in the U pipe, then prefer sal,
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;; else prefer lea for small shifts when srcreg == dstreg.
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;;
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;; For PPro/PII
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;;
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;; There's more than one approach to optimizing for this family; it is
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;; unclear which approach is best. For now, we will try to minimize
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;; uops. Note that sal and lea have the same characteristics, so we
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;; prefer sal as it takes less space.
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;;
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;; We can actually share code for these two cases since the basic techniques
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;; for generating good code on these chips is the same, even if the final
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;; code sequences are different.
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;;
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;; I do not know what is most appropriate for the AMD or Cyrix chips.
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;;
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;; srcreg == dstreg, constant shift count:
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;;
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;; For a shift count of one, use "add".
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;; For a shift count of two or three, use "sal"/"lea" for Pentium and
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;; Pentium MMX depending on which pipe the insn will execute.
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;; All others use "sar".
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;;
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;; srcreg != dstreg, constant shift count:
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;;
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;; For shift counts of one to three, use "lea".
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;; All others use "lea" for the first shift into the destination reg,
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;; then fall back on the srcreg == dstreg for the residual shifts.
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;;
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;; memory destinations or nonconstant shift count:
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;;
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;; Use "sal".
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;;
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "r,0")
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(match_operand:SI 2 "nonmemory_operand" "M,cI")))]
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"! optimize_size"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
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(match_operand:SI 2 "nonmemory_operand" "cI,I")))]
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"! optimize_size
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&& ((int)ix86_cpu == (int)PROCESSOR_PENTIUM
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|| (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
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"*
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{
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/* This should be extremely rare (impossible?). We can not encode a shift
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of the stack pointer using an lea instruction. So copy the stack pointer
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into the destination register and fall into the srcreg == dstreg shifting
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support. */
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if (operands[1] == stack_pointer_rtx)
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{
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output_asm_insn (AS2 (mov%L0,%1,%0), operands);
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operands[1] = operands[0];
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}
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/* Handle case where srcreg != dstreg. */
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if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
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{
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/* For counts > 3, it is easiest to split into component insns. */
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if (INTVAL (operands[2]) > 3)
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return \"#\";
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/* For shifts up to and including 3 bits, use lea. */
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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/* Source and destination match. */
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/* Handle variable shift. */
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if (REG_P (operands[2]))
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return AS2 (sal%L0,%b2,%0);
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/* Always perform shift by 1 using an add instruction. */
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if (REG_P (operands[0]) && operands[2] == const1_rtx)
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return AS2 (add%L0,%0,%0);
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#if 0
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/* ??? Currently disabled. reg-stack currently stomps on the mode of
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each insn. Thus, we can not easily detect when we should use lea to
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improve issue characteristics. Until reg-stack is fixed, fall back to
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sal instruction for Pentiums to avoid AGI stall. */
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/* Shift reg by 2 or 3 use an lea instruction for Pentium if this is
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insn is expected to issue into the V pipe (the insn's mode will be
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TImode for a U pipe, and !TImode for a V pipe instruction). */
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if (REG_P (operands[0])
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&& GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) <= 3
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&& (int)ix86_cpu == (int)PROCESSOR_PENTIUM
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&& GET_MODE (insn) != TImode)
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{
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operands[1] = gen_rtx_MULT (SImode, operands[1],
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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#endif
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/* Otherwise use a shift instruction. */
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return AS2 (sal%L0,%2,%0);
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}")
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;; Pentium/PPro/PII Splitter used when srcreg != destreg and shift
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;; count is > 3. In each case we use lea to perform the first three
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;; shifts into the destination register, then we fall back to the
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;; normal shifting code for the residual shifts.
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(define_split
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ashift:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "immediate_operand" "I")))]
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"reload_completed
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&& ! optimize_size
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&& ((int)ix86_cpu == (int)PROCESSOR_PENTIUM
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|| (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)
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&& GET_CODE (operands[2]) == CONST_INT
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&& INTVAL (operands[2]) > 3
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&& true_regnum (operands[0]) != true_regnum (operands[1])"
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[(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
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"
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{
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operands[3] = GEN_INT (INTVAL (operands[2] - 3));
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operands[2] = GEN_INT (3);
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}")
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;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg"
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;; On i486, movl/sall appears slightly faster than leal, but the leal
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;; is smaller - use leal for now unless the shift count is 1.
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;;
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(define_insn ""
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[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
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(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
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(match_operand:SI 2 "nonmemory_operand" "cI,M")))]
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"! optimize_size
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&& ! ((int)ix86_cpu == (int)PROCESSOR_PENTIUM
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|| (int)ix86_cpu == (int)PROCESSOR_PENTIUMPRO)"
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"*
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{
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if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
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