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pa.c (move_operand): Relax "mode" test.
Wed Jul 24 10:53:38 1996 Jeffrey A Law (law@cygnus.com) * pa/pa.c (move_operand): Relax "mode" test. Allow scaled indexed addressing modes. (output_fp_move_double): Tweak output strings to work with updated 'F' and 'M' output modifiers. (print_operand): Collapse 'F' and 'M' into a single hunk of code. For auto-increment modes output "s,ma" and "s,mb". For scaled indexing modes output "x,s" For other addresses, output nothing for 'M' and "s" for 'F'. * pa.h (EXTRA_CONSTRAINT): Don't accept scaled indexed addresses for 'Q' and 'T'. Do accept scaled indexed addresses for 'R'. (GO_IF_LEGITIMATE_ADDRESS): Accept scaled indexed addresses for SFmode and DFmode. * pa.md: Remove all scaled indexed load patterns. (movsi patterns): Accept scaled indexed addresses in some cases. Update output strings for updated 'M' and 'F' output modifiers. (movhi, movqi, movsf, movdf, movdi patterns): Likewise. From-SVN: r12558
This commit is contained in:
Jeff Law
parent
2cf55b5554
commit
2414e0e283
@ -270,8 +270,6 @@ move_operand (op, mode)
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if (GET_CODE (op) == CONST_INT)
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return cint_ok_for_move (INTVAL (op));
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if (GET_MODE (op) != mode)
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return 0;
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if (GET_CODE (op) == SUBREG)
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op = SUBREG_REG (op);
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if (GET_CODE (op) != MEM)
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@ -281,6 +279,22 @@ move_operand (op, mode)
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if (GET_CODE (op) == LO_SUM)
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return (register_operand (XEXP (op, 0), Pmode)
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&& CONSTANT_P (XEXP (op, 1)));
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/* Since move_operand is only used for source operands, we can always
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allow scaled indexing! */
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if (GET_CODE (op) == PLUS
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&& ((GET_CODE (XEXP (op, 0)) == MULT
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&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
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&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
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&& INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
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&& GET_CODE (XEXP (op, 1)) == REG)
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|| (GET_CODE (XEXP (op, 1)) == MULT
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&&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
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&& GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
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&& INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
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&& GET_CODE (XEXP (op, 0)) == REG)))
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return 1;
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return memory_address_p (mode, op);
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}
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@ -1610,11 +1624,11 @@ output_fp_move_double (operands)
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|| operands[1] == CONST0_RTX (GET_MODE (operands[0])))
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output_asm_insn ("fcpy,dbl %r1,%0", operands);
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else
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output_asm_insn ("fldds%F1 %1,%0", operands);
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output_asm_insn ("fldd%F1 %1,%0", operands);
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}
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else if (FP_REG_P (operands[1]))
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{
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output_asm_insn ("fstds%F0 %1,%0", operands);
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output_asm_insn ("fstd%F0 %1,%0", operands);
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}
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else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
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{
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@ -3324,6 +3338,7 @@ print_operand (file, x, code)
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fputs ("i", file);
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return;
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case 'M':
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case 'F':
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switch (GET_CODE (XEXP (x, 0)))
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{
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case PRE_DEC:
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@ -3334,22 +3349,16 @@ print_operand (file, x, code)
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case POST_INC:
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fputs ("s,ma", file);
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break;
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default:
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break;
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}
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return;
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case 'F':
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switch (GET_CODE (XEXP (x, 0)))
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{
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case PRE_DEC:
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case PRE_INC:
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fputs (",mb", file);
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break;
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case POST_DEC:
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case POST_INC:
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fputs (",ma", file);
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case PLUS:
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if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
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|| GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
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fputs ("x,s", file);
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else if (code == 'F')
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fputs ("s", file);
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break;
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default:
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if (code == 'F')
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fputs ("s", file);
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break;
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}
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return;
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@ -3392,7 +3401,18 @@ print_operand (file, x, code)
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fprintf (file, "%d(0,%s)", size, reg_names [REGNO (base)]);
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break;
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default:
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output_address (XEXP (x, 0));
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if (GET_CODE (XEXP (x, 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
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fprintf (file, "%s(0,%s)",
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reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
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reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
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else if (GET_CODE (XEXP (x, 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
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fprintf (file, "%s(0,%s)",
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reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
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reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
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else
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output_address (XEXP (x, 0));
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break;
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}
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}
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@ -1362,12 +1362,25 @@ extern struct rtx_def *hppa_builtin_saveregs ();
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(IS_RELOADING_PSEUDO_P (OP) \
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|| (GET_CODE (OP) == MEM \
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&& memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
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&& ! symbolic_memory_operand (OP, VOIDmode))) \
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&& ! symbolic_memory_operand (OP, VOIDmode) \
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&& !(GET_CODE (XEXP (OP, 0)) == PLUS \
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&& (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
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|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))))\
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: ((C) == 'R' ? \
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(GET_CODE (OP) == MEM \
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&& GET_CODE (XEXP (OP, 0)) == PLUS \
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&& (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT \
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|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT) \
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&& (move_operand (OP, GET_MODE (OP)) \
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|| memory_address_p (GET_MODE (OP), XEXP (OP, 0))))\
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: ((C) == 'T' ? \
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(GET_CODE (OP) == MEM \
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/* Using DFmode forces only short displacements \
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to be recognized as valid in reg+d addresses. */\
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&& memory_address_p (DFmode, XEXP (OP, 0))) : 0))
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&& memory_address_p (DFmode, XEXP (OP, 0)) \
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&& !(GET_CODE (XEXP (OP, 0)) == PLUS \
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&& (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
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|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))) : 0)))
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
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and check its validity for a certain class.
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@ -1462,6 +1475,15 @@ extern struct rtx_def *hppa_builtin_saveregs ();
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|| ((MODE) != SFmode && (MODE) != DFmode))) \
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|| INT_5_BITS (index))) \
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goto ADDR; \
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if (base \
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&& (mode == SFmode || mode == DFmode) \
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&& GET_CODE (index) == MULT \
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&& GET_CODE (XEXP (index, 0)) == REG \
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&& REG_OK_FOR_BASE_P (XEXP (index, 0)) \
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&& GET_CODE (XEXP (index, 1)) == CONST_INT \
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&& INTVAL (XEXP (index, 1)) == (mode == SFmode ? 4 : 8)\
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&& shadd_operand (XEXP (index, 1), VOIDmode)) \
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goto ADDR; \
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} \
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else if (GET_CODE (X) == LO_SUM \
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&& GET_CODE (XEXP (X, 0)) == REG \
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@ -1449,7 +1449,7 @@
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[(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
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"=r,r,r,r,r,Q,*q,!f,f,*T")
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(match_operand:SI 1 "move_operand"
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"r,J,N,K,Q,rM,rM,!fM,*T,f"))]
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"r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
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"(register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode))
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&& ! TARGET_SOFT_FLOAT"
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@ -1462,8 +1462,8 @@
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stw%M0 %r1,%0
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mtsar %r1
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fcpy,sgl %r1,%0
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fldws%F1 %1,%0
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fstws%F0 %1,%0"
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fldw%F1 %1,%0
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fstw%F0 %1,%0"
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[(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
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@ -1471,7 +1471,7 @@
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[(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
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"=r,r,r,r,r,Q,*q")
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(match_operand:SI 1 "move_operand"
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"r,J,N,K,Q,rM,rM"))]
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"r,J,N,K,RQ,rM,rM"))]
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"(register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode))
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&& TARGET_SOFT_FLOAT"
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@ -1486,47 +1486,6 @@
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[(set_attr "type" "move,move,move,move,load,store,move")
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(set_attr "length" "4,4,4,4,4,4,4")])
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;; Load indexed. We don't use unscaled modes since they can't be used
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;; unless we can tell which of the registers is the base and which is
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;; the index, due to PA's idea of segment selection using the top bits
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;; of the base register.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"ldwx,s %1(0,%2),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; This variant of the above insn can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Note how operand 3 uses a predicate of "const_int_operand", but
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;; has constraints allowing a register. I don't know how this works,
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;; but it somehow makes sure that out-of-range constants are placed
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;; in a register which somehow magically is a "const_int_operand".
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;; (this was stolen from alpha.md, I'm not going to try and change it.)
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "&=r")
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(mem:SI (plus:SI (plus:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 4))
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rI"))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh2addl %1,%2,%0\;ldw %3(0,%0),%0\";
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else
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return \"sh2addl %1,%2,%0\;ldwx %3(0,%0),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
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@ -1845,7 +1804,7 @@
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(define_insn ""
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[(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!f")
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(match_operand:HI 1 "move_operand" "r,J,N,K,Q,rM,rM,!fM"))]
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(match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!fM"))]
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"register_operand (operands[0], HImode)
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|| reg_or_0_operand (operands[1], HImode)"
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"@
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@ -1860,74 +1819,6 @@
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[(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
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(set_attr "length" "4,4,4,4,4,4,4,4")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(mem:HI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING"
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"ldhx,s %2(0,%1),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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; Same thing with zero extension.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (mem:HI
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(plus:SI
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(mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r")))))]
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"! TARGET_DISABLE_INDEXING"
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"ldhx,s %2(0,%1),%0"
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[(set_attr "type" "load")
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(set_attr "length" "4")])
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;; These variants of the above insns can occur if the second operand
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;; is the frame pointer. This is a kludge, but there doesn't
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;; seem to be a way around it. Only recognize it while reloading.
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;; Note how operand 3 uses a predicate of "const_int_operand", but
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;; has constraints allowing a register. I don't know how this works,
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;; but it somehow makes sure that out-of-range constants are placed
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;; in a register which somehow magically is a "const_int_operand".
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;; (this was stolen from alpha.md, I'm not going to try and change it.
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=&r")
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(mem:HI (plus:SI (plus:SI
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(mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rI"))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh1addl %2,%1,%0\;ldh %3(0,%0),%0\";
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else
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return \"sh1addl %2,%1,%0\;ldhx %3(0,%0),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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; Now the zero extended variant.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=&r")
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(zero_extend:SI (mem:HI (plus:SI (plus:SI
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(mult:SI (match_operand:SI 2 "register_operand" "r")
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(const_int 2))
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(match_operand:SI 1 "register_operand" "r"))
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(match_operand:SI 3 "const_int_operand" "rI")))))]
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"! TARGET_DISABLE_INDEXING && reload_in_progress"
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"*
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{
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if (GET_CODE (operands[3]) == CONST_INT)
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return \"sh1addl %2,%1,%0\;ldh %3(0,%0),%0\";
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else
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return \"sh1addl %2,%1,%0\;ldhx %3(0,%0),%0\";
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}"
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[(set_attr "type" "load")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r")
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(mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
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@ -2074,7 +1965,7 @@
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(define_insn ""
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[(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!f")
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(match_operand:QI 1 "move_operand" "r,J,N,K,Q,rM,rM,!fM"))]
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(match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!fM"))]
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"register_operand (operands[0], QImode)
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|| reg_or_0_operand (operands[1], QImode)"
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"@
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@ -2360,7 +2251,7 @@
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&& operands[1] != CONST0_RTX (DFmode)
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&& ! TARGET_SOFT_FLOAT"
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"* return (which_alternative == 0 ? output_move_double (operands)
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: \"fldds%F1 %1,%0\");"
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: \"fldd%F1 %1,%0\");"
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[(set_attr "type" "move,fpload")
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(set_attr "length" "16,4")])
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@ -2409,9 +2300,9 @@
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(define_insn ""
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[(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
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"=f,*r,Q,?o,?Q,f,*r,*r")
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"=f,*r,RQ,?o,?Q,f,*r,*r")
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(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
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"fG,*rG,f,*r,*r,Q,o,Q"))]
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"fG,*rG,f,*r,*r,RQ,o,Q"))]
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"(register_operand (operands[0], DFmode)
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|| reg_or_0_operand (operands[1], DFmode))
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&& ! TARGET_SOFT_FLOAT"
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@ -2440,45 +2331,6 @@
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[(set_attr "type" "move,store,store,load,load")
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(set_attr "length" "8,8,16,8,16")])
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(const_int 8))
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(match_operand:SI 2 "register_operand" "r"))))]
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"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
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"flddx,s %1(0,%2),%0"
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[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; This variant of the above insn can occur if the second operand
|
||||
;; is the frame pointer. This is a kludge, but there doesn't
|
||||
;; seem to be a way around it. Only recognize it while reloading.
|
||||
;; Note how operand 3 uses a predicate of "const_int_operand", but
|
||||
;; has constraints allowing a register. I don't know how this works,
|
||||
;; but it somehow makes sure that out-of-range constants are placed
|
||||
;; in a register which somehow magically is a "const_int_operand".
|
||||
;; (this was stolen from alpha.md, I'm not going to try and change it.
|
||||
;; Ugh. Output is a FP register; so we need to earlyclobber something
|
||||
;; else as a temporary.
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(mem:DF (plus:SI
|
||||
(plus:SI
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "+&r")
|
||||
(const_int 8))
|
||||
(match_operand:SI 2 "register_operand" "r"))
|
||||
(match_operand:SI 3 "const_int_operand" "rL"))))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT && reload_in_progress"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[3]) == CONST_INT)
|
||||
return \"sh3addl %1,%2,%1\;fldds %3(0,%1),%0\";
|
||||
else
|
||||
return \"sh3addl %1,%2,%1\;flddx %3(0,%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "register_operand" "=fx")
|
||||
(mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
@ -2517,45 +2369,6 @@
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(const_int 8))
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
(match_operand:DF 0 "register_operand" "f"))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
|
||||
"fstdx,s %0,%1(0,%2)"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; This variant of the above insn can occur if the second operand
|
||||
;; is the frame pointer. This is a kludge, but there doesn't
|
||||
;; seem to be a way around it. Only recognize it while reloading.
|
||||
;; Note how operand 3 uses a predicate of "const_int_operand", but
|
||||
;; has constraints allowing a register. I don't know how this works,
|
||||
;; but it somehow makes sure that out-of-range constants are placed
|
||||
;; in a register which somehow magically is a "const_int_operand".
|
||||
;; (this was stolen from alpha.md, I'm not going to try and change it.
|
||||
;; Ugh. Output is a FP register; so we need to earlyclobber something
|
||||
;; else as a temporary.
|
||||
(define_insn ""
|
||||
[(set (mem:DF (plus:SI
|
||||
(plus:SI
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "+&r")
|
||||
(const_int 8))
|
||||
(match_operand:SI 2 "register_operand" "r"))
|
||||
(match_operand:SI 3 "const_int_operand" "rL")))
|
||||
(match_operand:DF 0 "register_operand" "f"))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT && reload_in_progress"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[3]) == CONST_INT)
|
||||
return \"sh3addl %1,%2,%1\;fstds %0,%3(0,%1)\";
|
||||
else
|
||||
return \"sh3addl %1,%2,%1\;fstdx %0,%3(0,%1)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
@ -2741,7 +2554,7 @@
|
||||
&& operands[1] != CONST0_RTX (SFmode)
|
||||
&& ! TARGET_SOFT_FLOAT"
|
||||
"* return (which_alternative == 0 ? singlemove_string (operands)
|
||||
: \" fldws%F1 %1,%0\");"
|
||||
: \" fldw%F1 %1,%0\");"
|
||||
[(set_attr "type" "move,fpload")
|
||||
(set_attr "length" "8,4")])
|
||||
|
||||
@ -2790,18 +2603,18 @@
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
|
||||
"=f,r,f,r,Q,Q")
|
||||
"=f,r,f,r,RQ,Q")
|
||||
(match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
|
||||
"fG,rG,Q,Q,f,rG"))]
|
||||
"fG,rG,RQ,Q,f,rG"))]
|
||||
"(register_operand (operands[0], SFmode)
|
||||
|| reg_or_0_operand (operands[1], SFmode))
|
||||
&& ! TARGET_SOFT_FLOAT"
|
||||
"@
|
||||
fcpy,sgl %r1,%0
|
||||
copy %r1,%0
|
||||
fldws%F1 %1,%0
|
||||
fldw%F1 %1,%0
|
||||
ldw%M1 %1,%0
|
||||
fstws%F0 %r1,%0
|
||||
fstw%F0 %r1,%0
|
||||
stw%M0 %r1,%0"
|
||||
[(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
|
||||
(set_attr "length" "4,4,4,4,4,4")])
|
||||
@ -2821,45 +2634,6 @@
|
||||
[(set_attr "type" "move,load,store")
|
||||
(set_attr "length" "4,4,4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(const_int 4))
|
||||
(match_operand:SI 2 "register_operand" "r"))))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
|
||||
"fldwx,s %1(0,%2),%0"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; This variant of the above insn can occur if the second operand
|
||||
;; is the frame pointer. This is a kludge, but there doesn't
|
||||
;; seem to be a way around it. Only recognize it while reloading.
|
||||
;; Note how operand 3 uses a predicate of "const_int_operand", but
|
||||
;; has constraints allowing a register. I don't know how this works,
|
||||
;; but it somehow makes sure that out-of-range constants are placed
|
||||
;; in a register which somehow magically is a "const_int_operand".
|
||||
;; (this was stolen from alpha.md, I'm not going to try and change it.
|
||||
;; Ugh. Output is a FP register; so we need to earlyclobber something
|
||||
;; else as a temporary.
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(mem:SF (plus:SI
|
||||
(plus:SI
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "+&r")
|
||||
(const_int 4))
|
||||
(match_operand:SI 2 "register_operand" "r"))
|
||||
(match_operand:SI 3 "const_int_operand" "rL"))))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT && reload_in_progress"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[3]) == CONST_INT)
|
||||
return \"sh2addl %1,%2,%1\;fldws %3(0,%1),%0\";
|
||||
else
|
||||
return \"sh2addl %1,%2,%1\;fldwx %3(0,%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=fx")
|
||||
(mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
@ -2898,45 +2672,6 @@
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
|
||||
(const_int 4))
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
(match_operand:SF 0 "register_operand" "f"))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
|
||||
"fstwx,s %0,%1(0,%2)"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; This variant of the above insn can occur if the second operand
|
||||
;; is the frame pointer. This is a kludge, but there doesn't
|
||||
;; seem to be a way around it. Only recognize it while reloading.
|
||||
;; Note how operand 3 uses a predicate of "const_int_operand", but
|
||||
;; has constraints allowing a register. I don't know how this works,
|
||||
;; but it somehow makes sure that out-of-range constants are placed
|
||||
;; in a register which somehow magically is a "const_int_operand".
|
||||
;; (this was stolen from alpha.md, I'm not going to try and change it.
|
||||
;; Ugh. Output is a FP register; so we need to earlyclobber something
|
||||
;; else as a temporary.
|
||||
(define_insn ""
|
||||
[(set (mem:SF (plus:SI
|
||||
(plus:SI
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "+&r")
|
||||
(const_int 4))
|
||||
(match_operand:SI 2 "register_operand" "r"))
|
||||
(match_operand:SI 3 "const_int_operand" "rL")))
|
||||
(match_operand:SF 0 "register_operand" "f"))]
|
||||
"! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT && reload_in_progress"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[3]) == CONST_INT)
|
||||
return \"sh2addl %1,%2,%1\;fstws %0,%3(0,%1)\";
|
||||
else
|
||||
return \"sh2addl %1,%2,%1\;fstwx %0,%3(0,%1)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
|
||||
(match_operand:SI 2 "register_operand" "r")))
|
||||
@ -3072,7 +2807,7 @@
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(float:SF (match_operand:SI 1 "const_int_operand" "m")))]
|
||||
"! TARGET_SOFT_FLOAT"
|
||||
"fldws %1,%0\;fcnvxf,sgl,sgl %0,%0"
|
||||
"fldw%F1 %1,%0\;fcnvxf,sgl,sgl %0,%0"
|
||||
[(set_attr "type" "fpalu")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
@ -3091,7 +2826,7 @@
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(float:DF (match_operand:SI 1 "const_int_operand" "m")))]
|
||||
"! TARGET_SOFT_FLOAT"
|
||||
"fldws %1,%0\;fcnvxf,sgl,dbl %0,%0"
|
||||
"fldw%F1 %1,%0\;fcnvxf,sgl,dbl %0,%0"
|
||||
[(set_attr "type" "fpalu")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user