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RISC-V: allow bseti on SImode without sign-extension

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As long as the SImode operand is not a partial subreg, we can use a
bseti without postprocessing to or in a bit, as the middle end is
smart enough to stay away from the signbit.

gcc/ChangeLog:

	* config/riscv/bitmanip.md (*bsetidisi): New pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbs-bseti-02.c: New test.
This commit is contained in:
Philipp Tomsich 2022-10-10 22:24:02 +02:00
parent 11543b27fe
commit 23d9f62c50
2 changed files with 37 additions and 0 deletions
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12
gcc/config/riscv/bitmanip.md
View File

@ -350,6 +350,18 @@
"bseti\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
;; As long as the SImode operand is not a partial subreg, we can use a
;; bseti without postprocessing, as the middle end is smart enough to
;; stay away from the signbit.
(define_insn "*bsetidisi"
[(set (match_operand:DI 0 "register_operand" "=r")
(ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
(match_operand 2 "single_bit_mask_operand" "i")))]
"TARGET_ZBS && TARGET_64BIT
&& !partial_subreg_p (operands[2])"
"bseti\t%0,%1,%S2"
[(set_attr "type" "bitmanip")])
(define_insn "*bclr<mode>"
[(set (match_operand:X 0 "register_operand" "=r")
(and:X (rotate:X (const_int -2)

25
gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c Normal file
View File

@ -0,0 +1,25 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
/* bexti */
int f(int* a, int b)
{
return ((*a << b) | (1 << 14));
}
int g(int a, int b)
{
return ((a + b)| (1 << 30));
}
int h(int a, int b)
{
return ((a + b)| (1ULL << 33));
}
/* { dg-final { scan-assembler-times "addw\t" 2 } } */
/* { dg-final { scan-assembler-times "sllw\t" 1 } } */
/* { dg-final { scan-assembler-times "bseti\t" 2 } } */
/* { dg-final { scan-assembler-not "sext.w\t" } } */