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re PR middle-end/60102 (powerpc fp-bit ices at dwf_regno)
PR target/60102 [libgcc] 2014-07-31 Rohit <rohitarulraj@freescale.com> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update based on change in SPE high register numbers and 3 HTM registers. [gcc] 2014-07-31 Rohit <rohitarulraj@freescale.com> * config/rs6000/rs6000.c (rs6000_reg_names) : Add SPE high register names. (alt_reg_names) : Likewise. (rs6000_dwarf_register_span) : For SPE high registers, replace dwarf register numbers with GCC hard register numbers. (rs6000_init_dwarf_reg_sizes_extra) : Likewise. (rs6000_dbx_register_number): For SPE high registers, return dwarf register number for the corresponding GCC hard register number. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard register numbers for SPE high registers. (DWARF_FRAME_REGISTERS) : Likewise. (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. (DWARF_FRAME_REGNUM) : Likewise. (FIXED_REGISTERS) : Likewise. (CALL_USED_REGISTERS) : Likewise. (CALL_REALLY_USED_REGISTERS) : Likewise. (REG_ALLOC_ORDER) : Likewise. (enum reg_class) : Likewise. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : Likewise. (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. * gcc.target/powerpc/pr60102.c: New testcase. From-SVN: r213596
This commit is contained in:
Rohit Arul Raj
Edmar Wienskoski
parent
62c986afde
commit
23742a9e1b
@ -1,3 +1,30 @@
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2014-08-04 Rohit <rohitarulraj@freescale.com>
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PR target/60102
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* config/rs6000/rs6000.c
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(rs6000_reg_names) : Add SPE high register names.
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(alt_reg_names) : Likewise.
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(rs6000_dwarf_register_span) : For SPE high registers, replace
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dwarf register numbers with GCC hard register numbers.
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(rs6000_init_dwarf_reg_sizes_extra) : Likewise.
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(rs6000_dbx_register_number): For SPE high registers, return dwarf
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register number for the corresponding GCC hard register number.
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* config/rs6000/rs6000.h
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(FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard
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register numbers for SPE high registers.
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(DWARF_FRAME_REGISTERS) : Likewise.
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(DWARF_REG_TO_UNWIND_COLUMN) : Likewise.
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(DWARF_FRAME_REGNUM) : Likewise.
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(FIXED_REGISTERS) : Likewise.
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(CALL_USED_REGISTERS) : Likewise.
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(CALL_REALLY_USED_REGISTERS) : Likewise.
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(REG_ALLOC_ORDER) : Likewise.
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(enum reg_class) : Likewise.
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(REG_CLASS_NAMES) : Likewise.
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(REG_CLASS_CONTENTS) : Likewise.
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(SPE_HIGH_REGNO_P) : New macro to identify SPE high registers.
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* gcc.target/powerpc/pr60102.c: New testcase.
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2014-08-04 Richard Biener <rguenther@suse.de>
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* gimple-fold.h (gimple_fold_builtin): Remove.
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@ -1221,7 +1221,12 @@ char rs6000_reg_names[][8] =
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/* Soft frame pointer. */
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"sfp",
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/* HTM SPR registers. */
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"tfhar", "tfiar", "texasr"
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"tfhar", "tfiar", "texasr",
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/* SPE High registers. */
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"0", "1", "2", "3", "4", "5", "6", "7",
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"8", "9", "10", "11", "12", "13", "14", "15",
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"16", "17", "18", "19", "20", "21", "22", "23",
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"24", "25", "26", "27", "28", "29", "30", "31"
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};
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#ifdef TARGET_REGNAMES
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@ -1249,7 +1254,12 @@ static const char alt_reg_names[][8] =
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/* Soft frame pointer. */
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"sfp",
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/* HTM SPR registers. */
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"tfhar", "tfiar", "texasr"
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"tfhar", "tfiar", "texasr",
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/* SPE High registers. */
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"%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
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"%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
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"%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
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"%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
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};
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#endif
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@ -31411,13 +31421,13 @@ rs6000_dwarf_register_span (rtx reg)
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{
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if (BYTES_BIG_ENDIAN)
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{
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parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
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parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
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parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
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}
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else
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{
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parts[2 * i] = gen_rtx_REG (SImode, regno);
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parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
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parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
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}
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}
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@ -31437,11 +31447,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
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rtx mem = gen_rtx_MEM (BLKmode, addr);
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rtx value = gen_int_mode (4, mode);
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for (i = 1201; i < 1232; i++)
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for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
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{
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int column = DWARF_REG_TO_UNWIND_COLUMN (i);
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HOST_WIDE_INT offset
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= DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
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int column = DWARF_REG_TO_UNWIND_COLUMN
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(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
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HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
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emit_move_insn (adjust_address (mem, mode, offset), value);
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}
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@ -31460,9 +31470,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
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for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
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{
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int column = DWARF_REG_TO_UNWIND_COLUMN (i);
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HOST_WIDE_INT offset
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= DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
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int column = DWARF_REG_TO_UNWIND_COLUMN
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(DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
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HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
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emit_move_insn (adjust_address (mem, mode, offset), value);
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}
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@ -31494,9 +31504,8 @@ rs6000_dbx_register_number (unsigned int regno)
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return 99;
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if (regno == SPEFSCR_REGNO)
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return 612;
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/* SPE high reg number. We get these values of regno from
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rs6000_dwarf_register_span. */
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gcc_assert (regno >= 1200 && regno < 1232);
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if (SPE_HIGH_REGNO_P (regno))
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return regno - FIRST_SPE_HIGH_REGNO + 1200;
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return regno;
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}
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@ -930,35 +930,36 @@ enum data_align { align_abi, align_opt, align_both };
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The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
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#define FIRST_PSEUDO_REGISTER 117
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#define FIRST_PSEUDO_REGISTER 149
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/* This must be included for pre gcc 3.0 glibc compatibility. */
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#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
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/* Add 32 dwarf columns for synthetic SPE registers. */
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#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)
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/* True if register is an SPE High register. */
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#define SPE_HIGH_REGNO_P(N) \
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((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
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/* SPE high registers added as hard regs.
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The sfp register and 3 HTM registers
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aren't included in DWARF_FRAME_REGISTERS. */
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#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
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/* The SPE has an additional 32 synthetic registers, with DWARF debug
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info numbering for these registers starting at 1200. While eh_frame
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register numbering need not be the same as the debug info numbering,
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we choose to number these regs for eh_frame at 1200 too. This allows
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future versions of the rs6000 backend to add hard registers and
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continue to use the gcc hard register numbering for eh_frame. If the
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extra SPE registers in eh_frame were numbered starting from the
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current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
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changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
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avoid invalidating older SPE eh_frame info.
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we choose to number these regs for eh_frame at 1200 too.
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We must map them here to avoid huge unwinder tables mostly consisting
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of unused space. */
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#define DWARF_REG_TO_UNWIND_COLUMN(r) \
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((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
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((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
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/* Use standard DWARF numbering for DWARF debugging information. */
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#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
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/* Use gcc hard register numbering for eh_frame. */
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#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
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#define DWARF_FRAME_REGNUM(REGNO) \
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(SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO))
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/* Map register numbers held in the call frame info that gcc has
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collected using DWARF_FRAME_REGNUM to those that should be output in
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@ -990,7 +991,10 @@ enum data_align { align_abi, align_opt, align_both };
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 1 \
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, 1, 1, 1, 1, 1, 1 \
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, 1, 1, 1, 1, 1, 1, \
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/* SPE High registers. */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
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}
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/* 1 for registers not available across function calls.
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@ -1010,7 +1014,10 @@ enum data_align { align_abi, align_opt, align_both };
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 1 \
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, 1, 1, 1, 1, 1, 1 \
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, 1, 1, 1, 1, 1, 1, \
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/* SPE High registers. */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
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}
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/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
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@ -1029,7 +1036,10 @@ enum data_align { align_abi, align_opt, align_both };
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0 \
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, 0, 0, 0, 0, 0, 0 \
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, 0, 0, 0, 0, 0, 0, \
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/* SPE High registers. */ \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
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}
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#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
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@ -1113,7 +1123,10 @@ enum data_align { align_abi, align_opt, align_both };
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96, 95, 94, 93, 92, 91, \
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108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
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109, 110, \
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111, 112, 113, 114, 115, 116 \
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111, 112, 113, 114, 115, 116, \
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117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
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129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
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141, 142, 143, 144, 145, 146, 147, 148 \
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}
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/* True if register is floating-point. */
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@ -1348,6 +1361,7 @@ enum reg_class
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CR_REGS,
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NON_FLOAT_REGS,
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CA_REGS,
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SPE_HIGH_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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};
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@ -1379,6 +1393,7 @@ enum reg_class
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"CR_REGS", \
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"NON_FLOAT_REGS", \
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"CA_REGS", \
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"SPE_HIGH_REGS", \
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"ALL_REGS" \
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}
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@ -1386,30 +1401,54 @@ enum reg_class
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This is an initializer for a vector of HARD_REG_SET
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of length N_REG_CLASSES. */
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#define REG_CLASS_CONTENTS \
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{ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
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{ 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
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{ 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
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{ 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \
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{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \
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{ 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
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{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
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{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \
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{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
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{ 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \
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#define REG_CLASS_CONTENTS \
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{ \
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/* NO_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
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/* BASE_REGS. */ \
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{ 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
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/* GENERAL_REGS. */ \
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{ 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
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/* FLOAT_REGS. */ \
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
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/* ALTIVEC_REGS. */ \
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{ 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
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/* VSX_REGS. */ \
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{ 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
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/* VRSAVE_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
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/* VSCR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
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/* SPE_ACC_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
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/* SPEFSCR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
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/* SPR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
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/* NON_SPECIAL_REGS. */ \
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{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
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/* LINK_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
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/* CTR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
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/* LINK_OR_CTR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
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/* SPECIAL_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
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/* SPEC_OR_GEN_REGS. */ \
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{ 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
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/* CR0_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
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/* CR_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
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/* NON_FLOAT_REGS. */ \
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{ 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
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/* CA_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
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/* SPE_HIGH_REGS. */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
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/* ALL_REGS. */ \
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{ 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
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}
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/* The same information, inverted:
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@ -2348,6 +2387,39 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
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&rs6000_reg_names[114][0], /* tfhar */ \
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&rs6000_reg_names[115][0], /* tfiar */ \
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&rs6000_reg_names[116][0], /* texasr */ \
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\
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&rs6000_reg_names[117][0], /* SPE rh0. */ \
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&rs6000_reg_names[118][0], /* SPE rh1. */ \
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&rs6000_reg_names[119][0], /* SPE rh2. */ \
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&rs6000_reg_names[120][0], /* SPE rh3. */ \
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&rs6000_reg_names[121][0], /* SPE rh4. */ \
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&rs6000_reg_names[122][0], /* SPE rh5. */ \
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&rs6000_reg_names[123][0], /* SPE rh6. */ \
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&rs6000_reg_names[124][0], /* SPE rh7. */ \
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&rs6000_reg_names[125][0], /* SPE rh8. */ \
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&rs6000_reg_names[126][0], /* SPE rh9. */ \
|
||||
&rs6000_reg_names[127][0], /* SPE rh10. */ \
|
||||
&rs6000_reg_names[128][0], /* SPE rh11. */ \
|
||||
&rs6000_reg_names[129][0], /* SPE rh12. */ \
|
||||
&rs6000_reg_names[130][0], /* SPE rh13. */ \
|
||||
&rs6000_reg_names[131][0], /* SPE rh14. */ \
|
||||
&rs6000_reg_names[132][0], /* SPE rh15. */ \
|
||||
&rs6000_reg_names[133][0], /* SPE rh16. */ \
|
||||
&rs6000_reg_names[134][0], /* SPE rh17. */ \
|
||||
&rs6000_reg_names[135][0], /* SPE rh18. */ \
|
||||
&rs6000_reg_names[136][0], /* SPE rh19. */ \
|
||||
&rs6000_reg_names[137][0], /* SPE rh20. */ \
|
||||
&rs6000_reg_names[138][0], /* SPE rh21. */ \
|
||||
&rs6000_reg_names[139][0], /* SPE rh22. */ \
|
||||
&rs6000_reg_names[140][0], /* SPE rh22. */ \
|
||||
&rs6000_reg_names[141][0], /* SPE rh24. */ \
|
||||
&rs6000_reg_names[142][0], /* SPE rh25. */ \
|
||||
&rs6000_reg_names[143][0], /* SPE rh26. */ \
|
||||
&rs6000_reg_names[144][0], /* SPE rh27. */ \
|
||||
&rs6000_reg_names[145][0], /* SPE rh28. */ \
|
||||
&rs6000_reg_names[146][0], /* SPE rh29. */ \
|
||||
&rs6000_reg_names[147][0], /* SPE rh30. */ \
|
||||
&rs6000_reg_names[148][0], /* SPE rh31. */ \
|
||||
}
|
||||
|
||||
/* Table of additional register names to use in user input. */
|
||||
@ -2403,7 +2475,17 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
|
||||
{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
|
||||
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
|
||||
/* Transactional Memory Facility (HTM) Registers. */ \
|
||||
{"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} }
|
||||
{"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
|
||||
/* SPE high registers. */ \
|
||||
{"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
|
||||
{"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
|
||||
{"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
|
||||
{"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
|
||||
{"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
|
||||
{"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
|
||||
{"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
|
||||
{"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
|
||||
}
|
||||
|
||||
/* This is how to output an element of a case-vector that is relative. */
|
||||
|
||||
|
||||
@ -56,6 +56,8 @@
|
||||
(TFHAR_REGNO 114)
|
||||
(TFIAR_REGNO 115)
|
||||
(TEXASR_REGNO 116)
|
||||
(FIRST_SPE_HIGH_REGNO 117)
|
||||
(LAST_SPE_HIGH_REGNO 148)
|
||||
])
|
||||
|
||||
;;
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2014-08-04 Rohit <rohitarulraj@freescale.com>
|
||||
|
||||
PR target/60102
|
||||
* config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update
|
||||
based on change in SPE high register numbers and 3 HTM registers.
|
||||
|
||||
2014-08-01 Nathan Sidwell <nathan@acm.org>
|
||||
|
||||
* Makefile.in (LIBGCOV_MERGE, LIBGCOV_PROFILER,
|
||||
|
||||
@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind_Context *context,
|
||||
#ifdef __SPE__
|
||||
for (i = 14; i < 32; i++)
|
||||
{
|
||||
fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET;
|
||||
fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset
|
||||
fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET;
|
||||
fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset
|
||||
= (long) ®s->vregs - new_cfa + 4 * i;
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user