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extend.texi: Document new builtin functions for Intel Prescott New Intrunctions.
2003-06-25 H.J. Lu <hongjiu.lu@intel.com> * doc/extend.texi: Document new builtin functions for Intel Prescott New Intrunctions. * doc/invoke.texi: Document new command-line options, -mpni and -mno-pni, for Intel Prescott New Intrunctions. * config.gcc (extra_headers): Add pmmintrin.h for i[34567]86-*-*. * config/i386/i386.c (override_options): Turn on MASK_SSE2 for -mpni. Turn on MASK_SSE for -msse2. (bdesc_2arg): Add PNI builtins with 2 args. (bdesc_1arg): Add PNI builtins with 1 arg. (ix86_init_mmx_sse_builtins): Handle PNI builtins. (ix86_expand_builtin): Likewise. * config/i386/i386.h (MASK_3DNOW, MASK_3DNOW_A, MASK_128BIT_LONG_DOUBLE, MASK_64BIT, MASK_MS_BITFIELD_LAYOUT, MASK_TLS_DIRECT_SEG_REFS): Renumbered. (TARGET_PNI): New. (TARGET_SWITCHES): Don't enable MASK_SSE for -msse2 here. Add -mpni and -mno-pni. (TARGET_CPU_CPP_BUILTINS): Defined __PNI__ for PNI. (ix86_builtins): Add PNI builtins. (config/i386/i386.md): Add PNI patterns. * config/i386/pmmintrin.h: New file. From-SVN: r68502
This commit is contained in:
H.J. Lu
H.J. Lu
parent
7f8b3eb0cc
commit
22c7c85ebc
@ -1,3 +1,32 @@
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2003-06-25 H.J. Lu <hongjiu.lu@intel.com>
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* doc/extend.texi: Document new builtin functions for Intel
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Prescott New Intrunctions.
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* doc/invoke.texi: Document new command-line options, -mpni and
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-mno-pni, for Intel Prescott New Intrunctions.
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* config.gcc (extra_headers): Add pmmintrin.h for i[34567]86-*-*.
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* config/i386/i386.c (override_options): Turn on MASK_SSE2
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for -mpni. Turn on MASK_SSE for -msse2.
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(bdesc_2arg): Add PNI builtins with 2 args.
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(bdesc_1arg): Add PNI builtins with 1 arg.
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(ix86_init_mmx_sse_builtins): Handle PNI builtins.
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(ix86_expand_builtin): Likewise.
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* config/i386/i386.h (MASK_3DNOW, MASK_3DNOW_A,
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MASK_128BIT_LONG_DOUBLE, MASK_64BIT, MASK_MS_BITFIELD_LAYOUT,
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MASK_TLS_DIRECT_SEG_REFS): Renumbered.
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(TARGET_PNI): New.
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(TARGET_SWITCHES): Don't enable MASK_SSE for -msse2 here. Add
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-mpni and -mno-pni.
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(TARGET_CPU_CPP_BUILTINS): Defined __PNI__ for PNI.
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(ix86_builtins): Add PNI builtins.
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(config/i386/i386.md): Add PNI patterns.
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* config/i386/pmmintrin.h: New file.
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2003-06-25 Kazu Hirata <kazu@cs.umass.edu>
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* config/h8300/h8300.md (call): Fix the insn lengths.
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@ -1373,6 +1373,14 @@ override_options ()
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if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
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target_flags &= ~MASK_NO_FANCY_MATH_387;
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/* Turn on SSE2 builtins for -mpni. */
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if (TARGET_PNI)
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target_flags |= MASK_SSE2;
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/* Turn on SSE builtins for -msse2. */
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if (TARGET_SSE2)
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target_flags |= MASK_SSE;
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if (TARGET_64BIT)
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{
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if (TARGET_ALIGN_DOUBLE)
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@ -13058,7 +13066,15 @@ static const struct builtin_description bdesc_2arg[] =
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{ MASK_SSE2, CODE_FOR_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
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{ MASK_SSE2 | MASK_64BIT, CODE_FOR_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
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{ MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
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{ MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 }
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{ MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
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/* PNI MMX */
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{ MASK_PNI, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
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{ MASK_PNI, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
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{ MASK_PNI, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
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{ MASK_PNI, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
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{ MASK_PNI, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
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{ MASK_PNI, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
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};
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static const struct builtin_description bdesc_1arg[] =
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@ -13104,7 +13120,12 @@ static const struct builtin_description bdesc_1arg[] =
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{ MASK_SSE2, CODE_FOR_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
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{ MASK_SSE2, CODE_FOR_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
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{ MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 }
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{ MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 },
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/* PNI */
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{ MASK_PNI, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
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{ MASK_PNI, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
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{ MASK_PNI, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 }
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};
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void
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@ -13195,6 +13216,13 @@ ix86_init_mmx_sse_builtins ()
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= build_function_type (void_type_node, void_list_node);
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tree void_ftype_unsigned
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= build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
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tree void_ftype_unsigned_unsigned
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= build_function_type_list (void_type_node, unsigned_type_node,
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unsigned_type_node, NULL_TREE);
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tree void_ftype_pcvoid_unsigned_unsigned
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= build_function_type_list (void_type_node, const_ptr_type_node,
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unsigned_type_node, unsigned_type_node,
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NULL_TREE);
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tree unsigned_ftype_void
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= build_function_type (unsigned_type_node, void_list_node);
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tree di_ftype_void
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@ -13700,6 +13728,26 @@ ix86_init_mmx_sse_builtins ()
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def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
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def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
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/* Prescott New Instructions. */
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def_builtin (MASK_PNI, "__builtin_ia32_monitor",
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void_ftype_pcvoid_unsigned_unsigned,
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IX86_BUILTIN_MONITOR);
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def_builtin (MASK_PNI, "__builtin_ia32_mwait",
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void_ftype_unsigned_unsigned,
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IX86_BUILTIN_MWAIT);
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def_builtin (MASK_PNI, "__builtin_ia32_movshdup",
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v4sf_ftype_v4sf,
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IX86_BUILTIN_MOVSHDUP);
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def_builtin (MASK_PNI, "__builtin_ia32_movsldup",
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v4sf_ftype_v4sf,
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IX86_BUILTIN_MOVSLDUP);
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def_builtin (MASK_PNI, "__builtin_ia32_lddqu",
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v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
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def_builtin (MASK_PNI, "__builtin_ia32_loadddup",
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v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP);
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def_builtin (MASK_PNI, "__builtin_ia32_movddup",
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v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP);
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}
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/* Errors in the source file can cause expand_expr to return const0_rtx
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@ -14509,6 +14557,41 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
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case IX86_BUILTIN_STORED:
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return ix86_expand_store_builtin (CODE_FOR_sse2_stored, arglist);
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case IX86_BUILTIN_MONITOR:
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arg0 = TREE_VALUE (arglist);
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arg1 = TREE_VALUE (TREE_CHAIN (arglist));
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arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
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op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
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if (!REG_P (op0))
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op0 = copy_to_mode_reg (SImode, op0);
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if (!REG_P (op1))
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op1 = copy_to_mode_reg (SImode, op1);
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if (!REG_P (op2))
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op2 = copy_to_mode_reg (SImode, op2);
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emit_insn (gen_monitor (op0, op1, op2));
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return 0;
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case IX86_BUILTIN_MWAIT:
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arg0 = TREE_VALUE (arglist);
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arg1 = TREE_VALUE (TREE_CHAIN (arglist));
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op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
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if (!REG_P (op0))
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op0 = copy_to_mode_reg (SImode, op0);
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if (!REG_P (op1))
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op1 = copy_to_mode_reg (SImode, op1);
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emit_insn (gen_mwait (op0, op1));
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return 0;
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case IX86_BUILTIN_LOADDDUP:
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return ix86_expand_unop_builtin (CODE_FOR_loadddup, arglist, target, 1);
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case IX86_BUILTIN_LDDQU:
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return ix86_expand_unop_builtin (CODE_FOR_lddqu, arglist, target,
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1);
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default:
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break;
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}
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@ -121,12 +121,13 @@ extern int target_flags;
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#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
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#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
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#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
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#define MASK_3DNOW 0x00010000 /* Support 3Dnow builtins */
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#define MASK_3DNOW_A 0x00020000 /* Support Athlon 3Dnow builtins */
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#define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */
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#define MASK_64BIT 0x00080000 /* Produce 64bit code */
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#define MASK_MS_BITFIELD_LAYOUT 0x00100000 /* Use native (MS) bitfield layout */
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#define MASK_TLS_DIRECT_SEG_REFS 0x00200000 /* Avoid adding %gs:0 */
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#define MASK_PNI 0x00010000 /* Support PNI regs/builtins */
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#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
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#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
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#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
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#define MASK_64BIT 0x00100000 /* Produce 64bit code */
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#define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */
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#define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */
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/* Unused: 0x03e0000 */
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@ -302,6 +303,7 @@ extern int x86_prefetch_sse;
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#define TARGET_SSE ((target_flags & MASK_SSE) != 0)
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#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
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#define TARGET_PNI ((target_flags & MASK_PNI) != 0)
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#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
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#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
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&& (ix86_fpmath & FPMATH_387))
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@ -393,10 +395,14 @@ extern int x86_prefetch_sse;
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N_("Support MMX and SSE built-in functions and code generation") }, \
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{ "no-sse", -MASK_SSE, \
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N_("Do not support MMX and SSE built-in functions and code generation") },\
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{ "sse2", (MASK_SSE2|MASK_SSE), \
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{ "sse2", MASK_SSE2, \
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N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
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{ "no-sse2", -MASK_SSE2, \
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N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
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{ "pni", MASK_PNI, \
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N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
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{ "no-pni", -MASK_PNI, \
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N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
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{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
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N_("sizeof(long double) is 16") }, \
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{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
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@ -611,6 +617,8 @@ extern int x86_prefetch_sse;
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builtin_define ("__SSE__"); \
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if (TARGET_SSE2) \
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builtin_define ("__SSE2__"); \
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if (TARGET_PNI) \
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builtin_define ("__PNI__"); \
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if (TARGET_SSE_MATH && TARGET_SSE) \
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builtin_define ("__SSE_MATH__"); \
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if (TARGET_SSE_MATH && TARGET_SSE2) \
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@ -2516,6 +2524,22 @@ enum ix86_builtins
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IX86_BUILTIN_MFENCE,
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IX86_BUILTIN_LFENCE,
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/* Prescott New Instructions. */
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IX86_BUILTIN_ADDSUBPS,
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IX86_BUILTIN_HADDPS,
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IX86_BUILTIN_HSUBPS,
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IX86_BUILTIN_MOVSHDUP,
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IX86_BUILTIN_MOVSLDUP,
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IX86_BUILTIN_ADDSUBPD,
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IX86_BUILTIN_HADDPD,
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IX86_BUILTIN_HSUBPD,
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IX86_BUILTIN_LOADDDUP,
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IX86_BUILTIN_MOVDDUP,
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IX86_BUILTIN_LDDQU,
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IX86_BUILTIN_MONITOR,
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IX86_BUILTIN_MWAIT,
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IX86_BUILTIN_MAX
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};
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@ -109,6 +109,13 @@
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(UNSPEC_MFENCE 59)
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(UNSPEC_LFENCE 60)
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(UNSPEC_PSADBW 61)
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(UNSPEC_ADDSUB 71)
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(UNSPEC_HADD 72)
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(UNSPEC_HSUB 73)
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(UNSPEC_MOVSHDUP 74)
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(UNSPEC_MOVSLDUP 75)
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(UNSPEC_LDQQU 76)
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(UNSPEC_MOVDDUP 77)
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; x87 Floating point
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(UNSPEC_FPATAN 65)
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@ -130,6 +137,8 @@
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(UNSPECV_FEMMS 46)
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(UNSPECV_CLFLUSH 57)
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(UNSPECV_ALIGN 68)
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(UNSPECV_MONITOR 69)
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(UNSPECV_MWAIT 70)
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])
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;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
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@ -23512,3 +23521,129 @@
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"lfence"
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[(set_attr "type" "sse")
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(set_attr "memory" "unknown")])
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;; PNI
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(define_insn "mwait"
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[(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
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(match_operand:SI 1 "register_operand" "c")]
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UNSPECV_MWAIT)]
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"TARGET_PNI"
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"mwait\t%0, %1"
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[(set_attr "length" "3")])
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(define_insn "monitor"
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[(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
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(match_operand:SI 1 "register_operand" "c")
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(match_operand:SI 2 "register_operand" "d")]
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UNSPECV_MONITOR)]
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"TARGET_PNI"
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"monitor\t%0, %1, %2"
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[(set_attr "length" "3")])
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;; PNI arithmetic
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(define_insn "addsubv4sf3"
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_ADDSUB))]
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"TARGET_PNI"
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"addsubps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V4SF")])
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(define_insn "addsubv2df3"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_ADDSUB))]
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"TARGET_PNI"
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"addsubpd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V2DF")])
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(define_insn "haddv4sf3"
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_HADD))]
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"TARGET_PNI"
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"haddps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V4SF")])
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(define_insn "haddv2df3"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_HADD))]
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"TARGET_PNI"
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"haddpd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V2DF")])
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(define_insn "hsubv4sf3"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x")
|
||||
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
|
||||
(match_operand:V4SF 2 "nonimmediate_operand" "xm")]
|
||||
UNSPEC_HSUB))]
|
||||
"TARGET_PNI"
|
||||
"hsubps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "hsubv2df3"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=x")
|
||||
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" "xm")]
|
||||
UNSPEC_HSUB))]
|
||||
"TARGET_PNI"
|
||||
"hsubpd\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
(set_attr "mode" "V2DF")])
|
||||
|
||||
(define_insn "movshdup"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x")
|
||||
(unspec:V4SF
|
||||
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
|
||||
"TARGET_PNI"
|
||||
"movshdup\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "movsldup"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x")
|
||||
(unspec:V4SF
|
||||
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
|
||||
"TARGET_PNI"
|
||||
"movsldup\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "lddqu"
|
||||
[(set (match_operand:V16QI 0 "register_operand" "=x")
|
||||
(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
|
||||
UNSPEC_LDQQU))]
|
||||
"TARGET_PNI"
|
||||
"lddqu\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "loadddup"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=x")
|
||||
(vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
|
||||
"TARGET_PNI"
|
||||
"movddup\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn "movddup"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=x")
|
||||
(vec_duplicate:V2DF
|
||||
(vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
|
||||
(parallel [(const_int 0)]))))]
|
||||
"TARGET_PNI"
|
||||
"movddup\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
132
gcc/config/i386/pmmintrin.h
Normal file
132
gcc/config/i386/pmmintrin.h
Normal file
@ -0,0 +1,132 @@
|
||||
/* Copyright (C) 2003 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
||||
GNU CC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GNU CC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GNU CC; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 59 Temple Place - Suite 330,
|
||||
Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* As a special exception, if you include this header file into source
|
||||
files compiled by GCC, this header file does not by itself cause
|
||||
the resulting executable to be covered by the GNU General Public
|
||||
License. This exception does not however invalidate any other
|
||||
reasons why the executable file might be covered by the GNU General
|
||||
Public License. */
|
||||
|
||||
/* Implemented from the specification included in the Intel C++ Compiler
|
||||
User Guide and Reference, version 8.0. */
|
||||
|
||||
#ifndef _PMMINTRIN_H_INCLUDED
|
||||
#define _PMMINTRIN_H_INCLUDED
|
||||
|
||||
#ifdef __PNI__
|
||||
#include <xmmintrin.h>
|
||||
#include <emmintrin.h>
|
||||
|
||||
/* Additional bits in the MXCSR. */
|
||||
#define _MM_DENORMALS_ZERO_MASK 0x0040
|
||||
#define _MM_DENORMALS_ZERO_ON 0x0040
|
||||
#define _MM_DENORMALS_ZERO_OFF 0x0000
|
||||
|
||||
#define _MM_SET_DENORMALS_ZERO_MODE(mode) \
|
||||
_mm_setcsr ((_mm_getcsr () & ~_MM_DENORMALS_ZERO_MASK) | (mode))
|
||||
#define _MM_GET_DENORMALS_ZERO_MODE() \
|
||||
(_mm_getcsr() & _MM_DENORMALS_ZERO_MASK)
|
||||
|
||||
static __inline __m128
|
||||
_mm_addsub_ps (__m128 __X, __m128 __Y)
|
||||
{
|
||||
return (__m128) __builtin_ia32_addsubps ((__v4sf)__X, (__v4sf)__Y);
|
||||
}
|
||||
|
||||
static __inline __m128
|
||||
_mm_hadd_ps (__m128 __X, __m128 __Y)
|
||||
{
|
||||
return (__m128) __builtin_ia32_haddps ((__v4sf)__X, (__v4sf)__Y);
|
||||
}
|
||||
|
||||
static __inline __m128
|
||||
_mm_hsub_ps (__m128 __X, __m128 __Y)
|
||||
{
|
||||
return (__m128) __builtin_ia32_hsubps ((__v4sf)__X, (__v4sf)__Y);
|
||||
}
|
||||
|
||||
static __inline __m128
|
||||
_mm_movehdup_ps (__m128 __X)
|
||||
{
|
||||
return (__m128) __builtin_ia32_movshdup ((__v4sf)__X);
|
||||
}
|
||||
|
||||
static __inline __m128
|
||||
_mm_moveldup_ps (__m128 __X)
|
||||
{
|
||||
return (__m128) __builtin_ia32_movsldup ((__v4sf)__X);
|
||||
}
|
||||
|
||||
static __inline __m128d
|
||||
_mm_addsub_pd (__m128d __X, __m128d __Y)
|
||||
{
|
||||
return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
|
||||
}
|
||||
|
||||
static __inline __m128d
|
||||
_mm_hadd_pd (__m128d __X, __m128d __Y)
|
||||
{
|
||||
return (__m128d) __builtin_ia32_haddpd ((__v2df)__X, (__v2df)__Y);
|
||||
}
|
||||
|
||||
static __inline __m128d
|
||||
_mm_hsub_pd (__m128d __X, __m128d __Y)
|
||||
{
|
||||
return (__m128d) __builtin_ia32_hsubpd ((__v2df)__X, (__v2df)__Y);
|
||||
}
|
||||
|
||||
static __inline __m128d
|
||||
_mm_loaddup_pd (double const *__P)
|
||||
{
|
||||
return (__m128d) __builtin_ia32_loadddup (__P);
|
||||
}
|
||||
|
||||
static __inline __m128d
|
||||
_mm_movedup_pd (__m128d __X)
|
||||
{
|
||||
return (__m128d) __builtin_ia32_movddup ((__v2df)__X);
|
||||
}
|
||||
|
||||
static __inline __m128i
|
||||
_mm_lddqu_si128 (__m128i const *__P)
|
||||
{
|
||||
return (__m128i) __builtin_ia32_lddqu ((char const *)__P);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static __inline void
|
||||
_mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
|
||||
{
|
||||
__builtin_ia32_monitor (__P, __E, __H);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
_mm_mwait (unsigned int __E, unsigned int __H)
|
||||
{
|
||||
__builtin_ia32_mwait (__E, __H);
|
||||
}
|
||||
#else
|
||||
#define _mm_monitor(P, E, H) __builtin_ia32_monitor ((P), (E), (H))
|
||||
#define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H))
|
||||
#endif
|
||||
|
||||
#endif /* __PNI__ */
|
||||
|
||||
#endif /* _PMMINTRIN_H_INCLUDED */
|
||||
@ -5592,6 +5592,31 @@ Generates the @code{movhps} machine instruction as a store to memory.
|
||||
Generates the @code{movlps} machine instruction as a store to memory.
|
||||
@end table
|
||||
|
||||
The following built-in functions are available when @option{-mpni} is used.
|
||||
All of them generate the machine instruction that is part of the name.
|
||||
|
||||
@example
|
||||
v2df __builtin_ia32_addsubpd (v2df, v2df)
|
||||
v2df __builtin_ia32_addsubps (v2df, v2df)
|
||||
v2df __builtin_ia32_haddpd (v2df, v2df)
|
||||
v2df __builtin_ia32_haddps (v2df, v2df)
|
||||
v2df __builtin_ia32_hsubpd (v2df, v2df)
|
||||
v2df __builtin_ia32_hsubps (v2df, v2df)
|
||||
v16qi __builtin_ia32_lddqu (char const *)
|
||||
void __builtin_ia32_monitor (void *, unsigned int, unsigned int)
|
||||
v2df __builtin_ia32_movddup (v2df)
|
||||
v4sf __builtin_ia32_movshdup (v4sf)
|
||||
v4sf __builtin_ia32_movsldup (v4sf)
|
||||
void __builtin_ia32_mwait (unsigned int, unsigned int)
|
||||
@end example
|
||||
|
||||
The following built-in functions are available when @option{-mpni} is used.
|
||||
|
||||
@table @code
|
||||
@item v2df __builtin_ia32_loadddup (double const *)
|
||||
Generates the @code{movddup} machine instruction as a load from memory.
|
||||
@end table
|
||||
|
||||
The following built-in functions are available when @option{-m3dnow} is used.
|
||||
All of them generate the machine instruction that is part of the name.
|
||||
|
||||
|
||||
@ -487,7 +487,7 @@ in the following sections.
|
||||
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
|
||||
-mno-wide-multiply -mrtd -malign-double @gol
|
||||
-mpreferred-stack-boundary=@var{num} @gol
|
||||
-mmmx -msse -msse2 -m3dnow @gol
|
||||
-mmmx -msse -msse2 -mpni -m3dnow @gol
|
||||
-mthreads -mno-align-stringops -minline-all-stringops @gol
|
||||
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
|
||||
-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
|
||||
@ -8217,6 +8217,13 @@ code that expects temporaries to be 80bit.
|
||||
|
||||
This is the default choice for x86-64 compiler.
|
||||
|
||||
@item pni
|
||||
Use all SSE extensions enabled by @option{-msse2} as well as the new
|
||||
SSE extensions in Prescott New Intrunctions. @option{-mpni} also
|
||||
enables 2 builtin functions, @code{__builtin_ia32_monitor} and
|
||||
@code{__builtin_ia32_mwait}, for new intrunctions @code{monitor} and
|
||||
@code{mwait}.
|
||||
|
||||
@item sse,387
|
||||
Attempt to utilize both instruction sets at once. This effectively double the
|
||||
amount of available registers and on chips with separate execution units for
|
||||
@ -8398,6 +8405,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@itemx -mno-sse
|
||||
@item -msse2
|
||||
@itemx -mno-sse2
|
||||
@item -mpni
|
||||
@itemx -mno-pni
|
||||
@item -m3dnow
|
||||
@itemx -mno-3dnow
|
||||
@opindex mmmx
|
||||
|
||||
Loading…
Reference in New Issue
Block a user