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re PR target/40457 (use stm and ldm to access consecutive memory words)
PR target/40457 * postreload.c (move2add_use_add2_insn): Use full_costs for comparison. (move2add_use_add3_insn): Likewise. (reload_cse_move2add): Likewise. * rtlanal.c (get_full_rtx_cost): New function. * rtl.h (struct full_rtx_costs): New. (init_costs_to_max, init_costs_to_zero, costs_lt_p, costs_add_n_insns): New inline functions. (get_full_rtx_cost): Declare. testsuite/ PR target/40457 * gcc.target/arm/pr40457-3.c: New test. From-SVN: r164732
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Bernd Schmidt
Bernd Schmidt
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0f23bc1660
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2293974419
@ -1,3 +1,16 @@
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2010-09-29 Bernd Schmidt <bernds@codesourcery.com>
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PR target/40457
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* postreload.c (move2add_use_add2_insn): Use full_costs for
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comparison.
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(move2add_use_add3_insn): Likewise.
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(reload_cse_move2add): Likewise.
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* rtlanal.c (get_full_rtx_cost): New function.
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* rtl.h (struct full_rtx_costs): New.
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(init_costs_to_max, init_costs_to_zero, costs_lt_p,
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costs_add_n_insns): New inline functions.
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(get_full_rtx_cost): Declare.
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2010-09-29 Kai Tietz <kai.tietz@onevision.com>
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* config/i386/mingw32.h (TARGET_64BIT): replaced by
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116
gcc/postreload.c
116
gcc/postreload.c
@ -1645,39 +1645,45 @@ move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
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if (INTVAL (off) == reg_offset [regno])
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changed = validate_change (insn, &SET_SRC (pat), reg, 0);
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}
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else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
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&& have_add2_insn (reg, new_src))
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else
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{
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struct full_rtx_costs oldcst, newcst;
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rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
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changed = validate_change (insn, &SET_SRC (pat), tem, 0);
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}
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else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
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{
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enum machine_mode narrow_mode;
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for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
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narrow_mode != VOIDmode
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&& narrow_mode != GET_MODE (reg);
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narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
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get_full_rtx_cost (pat, SET, &oldcst);
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SET_SRC (pat) = tem;
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get_full_rtx_cost (pat, SET, &newcst);
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SET_SRC (pat) = src;
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if (costs_lt_p (&newcst, &oldcst, speed)
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&& have_add2_insn (reg, new_src))
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changed = validate_change (insn, &SET_SRC (pat), tem, 0);
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else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
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{
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if (have_insn_for (STRICT_LOW_PART, narrow_mode)
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&& ((reg_offset[regno]
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& ~GET_MODE_MASK (narrow_mode))
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== (INTVAL (off)
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& ~GET_MODE_MASK (narrow_mode))))
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enum machine_mode narrow_mode;
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for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
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narrow_mode != VOIDmode
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&& narrow_mode != GET_MODE (reg);
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narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
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{
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rtx narrow_reg = gen_rtx_REG (narrow_mode,
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REGNO (reg));
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rtx narrow_src = gen_int_mode (INTVAL (off),
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narrow_mode);
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rtx new_set =
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gen_rtx_SET (VOIDmode,
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gen_rtx_STRICT_LOW_PART (VOIDmode,
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narrow_reg),
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narrow_src);
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changed = validate_change (insn, &PATTERN (insn),
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new_set, 0);
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if (changed)
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break;
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if (have_insn_for (STRICT_LOW_PART, narrow_mode)
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&& ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode))
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== (INTVAL (off) & ~GET_MODE_MASK (narrow_mode))))
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{
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rtx narrow_reg = gen_rtx_REG (narrow_mode,
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REGNO (reg));
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rtx narrow_src = gen_int_mode (INTVAL (off),
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narrow_mode);
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rtx new_set
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= gen_rtx_SET (VOIDmode,
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gen_rtx_STRICT_LOW_PART (VOIDmode,
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narrow_reg),
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narrow_src);
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changed = validate_change (insn, &PATTERN (insn),
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new_set, 0);
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if (changed)
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break;
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}
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}
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}
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}
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@ -1705,11 +1711,18 @@ move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
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rtx pat = PATTERN (insn);
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rtx src = SET_SRC (pat);
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int regno = REGNO (reg);
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int min_cost = INT_MAX;
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int min_regno = 0;
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bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
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int i;
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bool changed = false;
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struct full_rtx_costs oldcst, newcst, mincst;
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rtx plus_expr;
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init_costs_to_max (&mincst);
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get_full_rtx_cost (pat, SET, &oldcst);
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plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx);
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SET_SRC (pat) = plus_expr;
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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if (reg_set_luid[i] > move2add_last_label_luid
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@ -1728,22 +1741,25 @@ move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
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no-op moves. */
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if (new_src == const0_rtx)
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{
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min_cost = 0;
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init_costs_to_zero (&mincst);
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min_regno = i;
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break;
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}
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else
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{
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int cost = rtx_cost (new_src, PLUS, speed);
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if (cost < min_cost)
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XEXP (plus_expr, 1) = new_src;
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get_full_rtx_cost (pat, SET, &newcst);
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if (costs_lt_p (&newcst, &mincst, speed))
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{
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min_cost = cost;
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mincst = newcst;
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min_regno = i;
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}
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}
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}
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SET_SRC (pat) = src;
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if (min_cost < rtx_cost (src, SET, speed))
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if (costs_lt_p (&mincst, &oldcst, speed))
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{
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rtx tem;
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@ -1879,18 +1895,26 @@ reload_cse_move2add (rtx first)
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/* See above why we create (set (reg) (reg)) here. */
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success
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= validate_change (next, &SET_SRC (set), reg, 0);
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else if ((rtx_cost (new_src, PLUS, speed)
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< COSTS_N_INSNS (1) + rtx_cost (src3, SET, speed))
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&& have_add2_insn (reg, new_src))
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else
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{
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rtx newpat = gen_rtx_SET (VOIDmode,
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reg,
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gen_rtx_PLUS (GET_MODE (reg),
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reg,
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new_src));
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success
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= validate_change (next, &PATTERN (next),
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newpat, 0);
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rtx old_src = SET_SRC (set);
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struct full_rtx_costs oldcst, newcst;
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rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
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get_full_rtx_cost (set, SET, &oldcst);
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SET_SRC (set) = tem;
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get_full_rtx_cost (tem, SET, &newcst);
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SET_SRC (set) = old_src;
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costs_add_n_insns (&oldcst, 1);
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if (costs_lt_p (&newcst, &oldcst, speed)
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&& have_add2_insn (reg, new_src))
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{
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rtx newpat = gen_rtx_SET (VOIDmode, reg, tem);
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success
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= validate_change (next, &PATTERN (next),
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newpat, 0);
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}
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}
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if (success)
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delete_insn (insn);
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48
gcc/rtl.h
48
gcc/rtl.h
@ -1123,9 +1123,57 @@ rhs_regno (const_rtx x)
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not to use an rtx with this cost under any circumstances. */
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#define MAX_COST INT_MAX
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/* A structure to hold all available cost information about an rtl
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expression. */
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struct full_rtx_costs
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{
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int speed;
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int size;
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};
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/* Initialize a full_rtx_costs structure C to the maximum cost. */
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static inline void
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init_costs_to_max (struct full_rtx_costs *c)
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{
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c->speed = MAX_COST;
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c->size = MAX_COST;
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}
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/* Initialize a full_rtx_costs structure C to zero cost. */
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static inline void
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init_costs_to_zero (struct full_rtx_costs *c)
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{
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c->speed = 0;
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c->size = 0;
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}
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/* Compare two full_rtx_costs structures A and B, returning true
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if A < B when optimizing for speed. */
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static inline bool
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costs_lt_p (struct full_rtx_costs *a, struct full_rtx_costs *b,
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bool speed)
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{
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if (speed)
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return (a->speed < b->speed
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|| (a->speed == b->speed && a->size < b->size));
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else
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return (a->size < b->size
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|| (a->size == b->size && a->speed < b->speed));
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}
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/* Increase both members of the full_rtx_costs structure C by the
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cost of N insns. */
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static inline void
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costs_add_n_insns (struct full_rtx_costs *c, int n)
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{
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c->speed += COSTS_N_INSNS (n);
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c->size += COSTS_N_INSNS (n);
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}
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extern void init_rtlanal (void);
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extern int rtx_cost (rtx, enum rtx_code, bool);
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extern int address_cost (rtx, enum machine_mode, addr_space_t, bool);
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extern void get_full_rtx_cost (rtx, enum rtx_code, struct full_rtx_costs *);
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extern unsigned int subreg_lsb (const_rtx);
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extern unsigned int subreg_lsb_1 (enum machine_mode, enum machine_mode,
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unsigned int);
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@ -3589,6 +3589,17 @@ rtx_cost (rtx x, enum rtx_code outer_code ATTRIBUTE_UNUSED, bool speed)
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return total;
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}
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/* Fill in the structure C with information about both speed and size rtx
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costs for X, with outer code OUTER. */
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void
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get_full_rtx_cost (rtx x, enum rtx_code outer, struct full_rtx_costs *c)
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{
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c->speed = rtx_cost (x, outer, true);
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c->size = rtx_cost (x, outer, false);
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}
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/* Return cost of address expression X.
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Expect that X is properly formed address reference.
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@ -1,3 +1,8 @@
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2010-09-29 Bernd Schmidt <bernds@codesourcery.com>
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PR target/40457
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* gcc.target/arm/pr40457-3.c: New test.
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2010-09-29 Nathan Sidwell <nathan@codesourcery.com>
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* lib/target-supports-dg.exp (dg-require-ifunc): Remove extraneous
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10
gcc/testsuite/gcc.target/arm/pr40457-3.c
Normal file
10
gcc/testsuite/gcc.target/arm/pr40457-3.c
Normal file
@ -0,0 +1,10 @@
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/* { dg-options "-Os" } */
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/* { dg-do compile } */
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void foo(int* p)
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{
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p[0] = 1;
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p[1] = 0;
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}
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/* { dg-final { scan-assembler "stm" } } */
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