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s390.md ("udivsi3"): Ensure trap is generated for division by zero.
gcc/ChangeLog:
* config/s390/s390.md ("udivsi3"): Ensure trap is generated
for division by zero.
("umodsi3"): Likewise.
libjava/ChangeLog:
* configure.host (DIVIDESPEC) [s390*-*-*]: Set to
-fno-use-divide-subroutine.
* include/s390-signal.h: Include <ucontext.h> and <limits.h>.
(HANDLE_FPE): Define.
(SIGNAL_HANDLER): Change third argument to ucontext_t *.
(struct old_s390_kernel_sigaction): Likewise for k_sa_handler.
(HANDLE_DIVIDE_OVERFLOW): Define.
From-SVN: r84683
This commit is contained in:
Ulrich Weigand
Ulrich Weigand
parent
bb732af863
commit
220a826e6d
@ -1,3 +1,9 @@
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2004-07-14 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390.md ("udivsi3"): Ensure trap is generated
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for division by zero.
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("umodsi3"): Likewise.
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2004-07-14 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (mips_output_move): When generating mips16 code,
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@ -4990,7 +4990,7 @@
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emit_move_insn (operands[0], const0_rtx);
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emit_insn (gen_cmpsi (operands[2], operands[1]));
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emit_jump_insn (gen_bgtu (label3));
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emit_insn (gen_cmpsi (operands[2], const1_rtx));
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emit_insn (gen_cmpsi (operands[2], const0_rtx));
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emit_jump_insn (gen_blt (label2));
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emit_insn (gen_cmpsi (operands[2], const1_rtx));
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emit_jump_insn (gen_beq (label1));
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@ -5082,7 +5082,7 @@
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emit_move_insn(operands[0], operands[1]);
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emit_insn (gen_cmpsi (operands[2], operands[1]));
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emit_jump_insn (gen_bgtu (label3));
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emit_insn (gen_cmpsi (operands[2], const1_rtx));
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emit_insn (gen_cmpsi (operands[2], const0_rtx));
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emit_jump_insn (gen_blt (label2));
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emit_insn (gen_cmpsi (operands[2], const1_rtx));
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emit_jump_insn (gen_beq (label1));
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@ -1,3 +1,13 @@
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2004-07-14 Ulrich Weigand <uweigand@de.ibm.com>
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* configure.host (DIVIDESPEC) [s390*-*-*]: Set to
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-fno-use-divide-subroutine.
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* include/s390-signal.h: Include <ucontext.h> and <limits.h>.
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(HANDLE_FPE): Define.
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(SIGNAL_HANDLER): Change third argument to ucontext_t *.
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(struct old_s390_kernel_sigaction): Likewise for k_sa_handler.
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(HANDLE_DIVIDE_OVERFLOW): Define.
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2004-07-14 Michael Koch <konqueror@gmx.de>
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Matthias Klose <doko@debian.org>
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@ -138,6 +138,7 @@ case "${host}" in
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s390*-*)
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sysdeps_dir=s390
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libgcj_interpreter=yes
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DIVIDESPEC=-fno-use-divide-subroutine
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enable_hash_synchronization_default=yes
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;;
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sparc*-*)
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@ -15,18 +15,170 @@ details. */
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#include <signal.h>
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#include <sys/syscall.h>
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#include <ucontext.h>
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#include <limits.h>
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#define HANDLE_SEGV 1
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#undef HANDLE_FPE
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#define HANDLE_FPE 1
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#define SIGNAL_HANDLER(_name) \
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static void _name (int, siginfo_t *, void *)
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static void _name (int, siginfo_t *_si __attribute__((unused)), \
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ucontext_t *_uc __attribute__((unused)))
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/* We no longer need to fiddle with the PSW address in the signal handler;
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this is now all handled correctly in MD_FALLBACK_FRAME_STATE_FOR. */
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#define MAKE_THROW_FRAME(_exception)
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/* According to the JVM spec, "if the dividend is the negative integer
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of the smallest magnitude and the divisor is -1, then overflow occurs
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and the result is equal to the dividend. Despite the overflow, no
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exception occurs".
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We handle this by inspecting the instruction which generated the signal,
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and if dividend and divisor are as above, we simply return from the signal
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handler. This causes execution to continue after the instruction.
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Before returning, we the set result registers as expected. */
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#define HANDLE_DIVIDE_OVERFLOW \
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do \
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{ \
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unsigned char *_eip = (unsigned char *) \
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__builtin_extract_return_addr (_si->si_addr); \
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unsigned long *_regs = _uc->uc_mcontext.gregs; \
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int _r1, _r2, _d2, _x2, _b2; \
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\
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/* First, a couple of helper routines to decode instructions. */ \
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struct _decode \
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{ \
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/* Decode RR instruction format. */ \
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static inline int _is_rr (unsigned char *_eip, \
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unsigned char _op, \
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int *_r1, int *_r2) \
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{ \
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if (_eip[0] == _op) \
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{ \
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*_r1 = _eip[1] >> 4; \
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*_r2 = _eip[1] & 0xf; \
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return 1; \
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} \
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return 0; \
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} \
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\
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/* Decode RX instruction format. */ \
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static inline int _is_rx (unsigned char *_eip, \
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unsigned char _op, \
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int *_r1, int *_d2, int *_x2, int *_b2) \
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{ \
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if (_eip[0] == _op) \
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{ \
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*_r1 = _eip[1] >> 4; \
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*_x2 = _eip[1] & 0xf; \
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*_b2 = _eip[2] >> 4; \
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*_d2 = ((_eip[2] & 0xf) << 8) + _eip[3]; \
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return 1; \
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} \
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return 0; \
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} \
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\
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/* Decode RRE instruction format. */ \
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static inline int _is_rre (unsigned char *_eip, \
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unsigned char _op1, unsigned char _op2,\
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int *_r1, int *_r2) \
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{ \
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if (_eip[0] == _op1 && _eip[1] == _op2) \
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{ \
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*_r1 = _eip[3] >> 4; \
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*_r2 = _eip[3] & 0xf; \
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return 1; \
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} \
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return 0; \
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} \
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\
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/* Decode RXY instruction format. */ \
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static inline int _is_rxy (unsigned char *_eip, \
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unsigned char _op1, unsigned char _op2,\
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int *_r1, int *_d2, int *_x2, int *_b2)\
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{ \
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if (_eip[0] == _op1 && _eip[5] == _op2) \
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{ \
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*_r1 = _eip[1] >> 4; \
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*_x2 = _eip[1] & 0xf; \
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*_b2 = _eip[2] >> 4; \
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*_d2 = ((_eip[2] & 0xf) << 8) + _eip[3] + (_eip[4] << 12); \
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/* We have a 20-bit signed displacement. */ \
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*_d2 = (*_d2 ^ 0x80000) - 0x80000; \
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return 1; \
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} \
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return 0; \
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} \
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\
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/* Compute effective address. */ \
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static inline unsigned long _eff (unsigned long *_regs, \
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long _d, int _x, int _b) \
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{ \
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return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0); \
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} \
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}; \
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\
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\
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/* DR r1,r2 */ \
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if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2) \
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&& (int) _regs[_r1] == -1 && (int) _regs[_r1+1] == INT_MIN \
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&& (int) _regs[_r2] == -1) \
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{ \
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_regs[_r1] &= ~0xffffffff; \
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return; \
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} \
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\
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/* D r1,d2(x2,b2) */ \
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if (_decode::_is_rx (_eip, 0x5d, &_r1, &_d2, &_x2, &_b2) \
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&& (int) _regs[_r1] == -1 && (int) _regs[_r1+1] == INT_MIN \
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&& *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1) \
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{ \
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_regs[_r1] &= ~0xffffffff; \
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return; \
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} \
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\
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/* DSGR r1,r2 */ \
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if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2) \
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&& (long) _regs[_r1+1] == LONG_MIN \
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&& (long) _regs[_r2] == -1L) \
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{ \
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_regs[_r1] = 0; \
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return; \
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} \
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\
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/* DSGFR r1,r2 */ \
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if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2) \
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&& (long) _regs[_r1+1] == LONG_MIN \
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&& (int) _regs[_r2] == -1) \
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{ \
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_regs[_r1] = 0; \
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return; \
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} \
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\
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/* DSG r1,d2(x2,b2) */ \
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if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2) \
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&& (long) _regs[_r1+1] == LONG_MIN \
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&& *(long *) _decode::_eff (_regs, _d2, _x2, _b2) == -1L) \
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{ \
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_regs[_r1] = 0; \
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return; \
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} \
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\
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/* DSGF r1,d2(x2,b2) */ \
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if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2) \
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&& (long) _regs[_r1+1] == LONG_MIN \
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&& *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1) \
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{ \
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_regs[_r1] = 0; \
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return; \
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} \
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\
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} \
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while (0)
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/* For an explanation why we cannot simply use sigaction to
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install the handlers, see i386-signal.h. */
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@ -36,7 +188,7 @@ static void _name (int, siginfo_t *, void *)
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visible to us in a header file so we define it here. */
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struct old_s390_kernel_sigaction {
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void (*k_sa_handler) (int, siginfo_t *, void *);
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void (*k_sa_handler) (int, siginfo_t *, ucontext_t *);
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unsigned long k_sa_mask;
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unsigned long k_sa_flags;
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void (*sa_restorer) (void);
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