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i386.h (enum reg_class): Remove FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS.

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* config/i386/i386.h (enum reg_class): Remove FP_TOP_SSE_REGS
	and FP_SECOND_SSE_REGS.
	(REG_CLASS_NAMES): Ditto.
	(REG_CLASS_CONTENTS): Ditto.
	* config/i386/i386.c (ix86_preferred_reload_class) Do not handle
	FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS classes.
	(ix86_preferred_output_reload_class): Ditto.
	* config/i386/i386.md (fix_trunc<mode>_i387_fisttp): Change "=&1f"
	clobber constraint to "=&f".
	(fix_truncdi_i387): Ditto.
	(lrintxfdi2): Ditto.
	(fistdi2_<rounding>): Ditto.
	(fpremxf4_i387): Change "=u" constraint to "=f".
	(fprem1xf4_i387): Ditto.
	(sincosxf3): Ditto.
	(fptanxf4_i387): Ditto.
	(fxtractxf3_i387): Ditto.
	(fscalexf4_i387): Ditto.
	(atan2xf3): Change "u" constraint to "f".
	(fyl2xxf3_i387): Ditto.
	(fyl2xp1xf3_i387): Ditto.

From-SVN: r264648
This commit is contained in:
Uros Bizjak 2018-09-26 17:17:32 +02:00 committed by Uros Bizjak
parent dd554b787d
commit 2202b162bb
4 changed files with 38 additions and 31 deletions
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24
gcc/ChangeLog
View File

@ -1,3 +1,27 @@
2018-09-26 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (enum reg_class): Remove FP_TOP_SSE_REGS
and FP_SECOND_SSE_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Ditto.
* config/i386/i386.c (ix86_preferred_reload_class) Do not handle
FP_TOP_SSE_REGS and FP_SECOND_SSE_REGS classes.
(ix86_preferred_output_reload_class): Ditto.
* config/i386/i386.md (fix_trunc<mode>_i387_fisttp): Change "=&1f"
clobber constraint to "=&f".
(fix_truncdi_i387): Ditto.
(lrintxfdi2): Ditto.
(fistdi2_<rounding>): Ditto.
(fpremxf4_i387): Change "=u" constraint to "=f".
(fprem1xf4_i387): Ditto.
(sincosxf3): Ditto.
(fptanxf4_i387): Ditto.
(fxtractxf3_i387): Ditto.
(fscalexf4_i387): Ditto.
(atan2xf3): Change "u" constraint to "f".
(fyl2xxf3_i387): Ditto.
(fyl2xp1xf3_i387): Ditto.
2018-09-26 Uros Bizjak <ubizjak@gmail.com>
PR target/87439

13
gcc/config/i386/i386.c
View File

@ -39043,10 +39043,6 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
/* Limit class to FP regs. */
if (FLOAT_CLASS_P (regclass))
return FLOAT_REGS;
else if (regclass == FP_TOP_SSE_REGS)
return FP_TOP_REG;
else if (regclass == FP_SECOND_SSE_REGS)
return FP_SECOND_REG;
}
return NO_REGS;
@ -39092,14 +39088,7 @@ ix86_preferred_output_reload_class (rtx x, reg_class_t regclass)
return MAYBE_SSE_CLASS_P (regclass) ? ALL_SSE_REGS : NO_REGS;
if (IS_STACK_MODE (mode))
{
if (regclass == FP_TOP_SSE_REGS)
return FP_TOP_REG;
else if (regclass == FP_SECOND_SSE_REGS)
return FP_SECOND_REG;
else
return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
}
return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
return regclass;
}

6
gcc/config/i386/i386.h
View File

@ -1337,8 +1337,6 @@ enum reg_class
SSE_REGS,
ALL_SSE_REGS,
MMX_REGS,
FP_TOP_SSE_REGS,
FP_SECOND_SSE_REGS,
FLOAT_SSE_REGS,
FLOAT_INT_REGS,
INT_SSE_REGS,
@ -1398,8 +1396,6 @@ enum reg_class
"SSE_REGS", \
"ALL_SSE_REGS", \
"MMX_REGS", \
"FP_TOP_SSE_REGS", \
"FP_SECOND_SSE_REGS", \
"FLOAT_SSE_REGS", \
"FLOAT_INT_REGS", \
"INT_SSE_REGS", \
@ -1438,8 +1434,6 @@ enum reg_class
{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
{ 0x1fe00000, 0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
{ 0x1fe00100, 0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
{ 0x1fe00200, 0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
{ 0x1fe0ff00, 0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
{ 0x1ff100ff, 0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \

26
gcc/config/i386/i386.md
View File

@ -4973,7 +4973,7 @@
(define_insn "fix_trunc<mode>_i387_fisttp"
[(set (match_operand:SWI248x 0 "nonimmediate_operand" "=m")
(fix:SWI248x (match_operand 1 "register_operand" "f")))
(clobber (match_scratch:XF 2 "=&1f"))]
(clobber (match_scratch:XF 2 "=&f"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_FISTTP
&& !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
@ -5019,7 +5019,7 @@
(fix:DI (match_operand 1 "register_operand" "f")))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))
(clobber (match_scratch:XF 4 "=&1f"))]
(clobber (match_scratch:XF 4 "=&f"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& !TARGET_FISTTP
&& !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
@ -15178,7 +15178,7 @@
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 3 "register_operand" "1")]
UNSPEC_FPREM_F))
(set (match_operand:XF 1 "register_operand" "=u")
(set (match_operand:XF 1 "register_operand" "=f")
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FPREM_U))
(set (reg:CCFP FPSR_REG)
@ -15253,7 +15253,7 @@
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 3 "register_operand" "1")]
UNSPEC_FPREM1_F))
(set (match_operand:XF 1 "register_operand" "=u")
(set (match_operand:XF 1 "register_operand" "=f")
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FPREM1_U))
(set (reg:CCFP FPSR_REG)
@ -15365,7 +15365,7 @@
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand" "=u")
(set (match_operand:XF 1 "register_operand" "=f")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
@ -15397,7 +15397,7 @@
(define_insn "fptanxf4_i387"
[(set (match_operand:SF 0 "register_operand" "=f")
(match_operand:SF 3 "const1_operand"))
(set (match_operand:XF 1 "register_operand" "=u")
(set (match_operand:XF 1 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
UNSPEC_TAN))]
"TARGET_USE_FANCY_MATH_387
@ -15439,7 +15439,7 @@
(define_insn "atan2xf3"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")
(match_operand:XF 2 "register_operand" "u")]
(match_operand:XF 2 "register_operand" "f")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=2"))]
"TARGET_USE_FANCY_MATH_387
@ -15576,7 +15576,7 @@
(define_insn "fyl2xxf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")
(match_operand:XF 2 "register_operand" "u")]
(match_operand:XF 2 "register_operand" "f")]
UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 "=2"))]
"TARGET_USE_FANCY_MATH_387
@ -15673,7 +15673,7 @@
(define_insn "fyl2xp1xf3_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")
(match_operand:XF 2 "register_operand" "u")]
(match_operand:XF 2 "register_operand" "f")]
UNSPEC_FYL2XP1))
(clobber (match_scratch:XF 3 "=2"))]
"TARGET_USE_FANCY_MATH_387
@ -15714,7 +15714,7 @@
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")]
UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 1 "register_operand" "=u")
(set (match_operand:XF 1 "register_operand" "=f")
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
@ -15808,7 +15808,7 @@
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 3 "register_operand" "1")]
UNSPEC_FSCALE_FRACT))
(set (match_operand:XF 1 "register_operand" "=u")
(set (match_operand:XF 1 "register_operand" "=f")
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FSCALE_EXP))]
"TARGET_USE_FANCY_MATH_387
@ -16193,7 +16193,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=m")
(unspec:DI [(match_operand:XF 1 "register_operand" "f")]
UNSPEC_FIST))
(clobber (match_scratch:XF 2 "=&1f"))]
(clobber (match_scratch:XF 2 "=&f"))]
"TARGET_USE_FANCY_MATH_387"
"* return output_fix_trunc (insn, operands, false);"
[(set_attr "type" "fpspc")
@ -16404,7 +16404,7 @@
FIST_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))
(clobber (match_scratch:XF 4 "=&1f"))]
(clobber (match_scratch:XF 4 "=&f"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"* return output_fix_trunc (insn, operands, false);"