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[AArch64] Pattern-match SVE extending loads
This patch pattern-matches a partial SVE load followed by a sign or zero extension into an extending load. (The partial load is already an extending load; we just don't rely on the upper bits of the elements.) Nothing yet uses the extra LDFF1 and LDNF1 combinations, but it seemed more consistent to provide them, since I needed to update the pattern to use a predicated extension anyway. 2019-11-16 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve.md (@aarch64_load_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>): (@aarch64_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>) (@aarch64_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>): Combine into... (@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>): ...this new pattern, handling extension to partial modes as well as full modes. Describe the extension as a predicated rather than unpredicated extension. (@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>) (@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>) (@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>): Combine into... (@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>): ...this new pattern, handling extension to partial modes as well as full modes. Describe the extension as a predicated rather than unpredicated extension. * config/aarch64/aarch64-sve-builtins.cc (function_expander::use_contiguous_load_insn): Add an extra predicate for extending loads. * config/aarch64/aarch64.c (aarch64_extending_load_p): New function. (aarch64_sve_adjust_stmt_cost): Likewise. (aarch64_add_stmt_cost): Use aarch64_sve_adjust_stmt_cost to adjust the cost of SVE vector stmts. gcc/testsuite/ * gcc.target/aarch64/sve/load_extend_1.c: New test. * gcc.target/aarch64/sve/load_extend_2.c: Likewise. * gcc.target/aarch64/sve/load_extend_3.c: Likewise. * gcc.target/aarch64/sve/load_extend_4.c: Likewise. * gcc.target/aarch64/sve/load_extend_5.c: Likewise. * gcc.target/aarch64/sve/load_extend_6.c: Likewise. * gcc.target/aarch64/sve/load_extend_7.c: Likewise. * gcc.target/aarch64/sve/load_extend_8.c: Likewise. * gcc.target/aarch64/sve/load_extend_9.c: Likewise. * gcc.target/aarch64/sve/load_extend_10.c: Likewise. * gcc.target/aarch64/sve/reduc_4.c: Add --param aarch64-sve-compare-costs=0. From-SVN: r278343
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
e58703e2c1
commit
217ccab8f4
@ -1,3 +1,30 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve.md
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(@aarch64_load_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>):
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(@aarch64_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
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(@aarch64_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>):
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Combine into...
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(@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
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...this new pattern, handling extension to partial modes as well
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as full modes. Describe the extension as a predicated rather than
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unpredicated extension.
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(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>)
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(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>)
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(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>):
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Combine into...
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(@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
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...this new pattern, handling extension to partial modes as well
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as full modes. Describe the extension as a predicated rather than
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unpredicated extension.
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* config/aarch64/aarch64-sve-builtins.cc
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(function_expander::use_contiguous_load_insn): Add an extra
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predicate for extending loads.
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* config/aarch64/aarch64.c (aarch64_extending_load_p): New function.
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(aarch64_sve_adjust_stmt_cost): Likewise.
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(aarch64_add_stmt_cost): Use aarch64_sve_adjust_stmt_cost to adjust
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the cost of SVE vector stmts.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_HSDI): New mode iterator.
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@ -2790,7 +2790,9 @@ function_expander::use_vcond_mask_insn (insn_code icode,
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}
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/* Implement the call using instruction ICODE, which loads memory operand 1
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into register operand 0 under the control of predicate operand 2. */
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into register operand 0 under the control of predicate operand 2.
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Extending loads have a further predicate (operand 3) that nominally
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controls the extension. */
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rtx
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function_expander::use_contiguous_load_insn (insn_code icode)
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{
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@ -2799,6 +2801,8 @@ function_expander::use_contiguous_load_insn (insn_code icode)
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add_output_operand (icode);
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add_mem_operand (mem_mode, get_contiguous_base (mem_mode));
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add_input_operand (icode, args[0]);
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if (GET_MODE_UNIT_BITSIZE (mem_mode) < type_suffix (0).element_bits)
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add_input_operand (icode, CONSTM1_RTX (VNx16BImode));
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return generate_insn (icode);
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}
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@ -1189,39 +1189,22 @@
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;; -------------------------------------------------------------------------
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;; Predicated load and extend, with 8 elements per 128-bit block.
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(define_insn "@aarch64_load_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>"
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[(set (match_operand:VNx8_WIDE 0 "register_operand" "=w")
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(ANY_EXTEND:VNx8_WIDE
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(unspec:VNx8_NARROW
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[(match_operand:VNx8BI 2 "register_operand" "Upl")
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(match_operand:VNx8_NARROW 1 "memory_operand" "m")]
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UNSPEC_LD1_SVE)))]
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"TARGET_SVE"
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"ld1<ANY_EXTEND:s><VNx8_NARROW:Vesize>\t%0.<VNx8_WIDE:Vetype>, %2/z, %1"
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)
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;; Predicated load and extend, with 4 elements per 128-bit block.
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(define_insn "@aarch64_load_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>"
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[(set (match_operand:VNx4_WIDE 0 "register_operand" "=w")
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(ANY_EXTEND:VNx4_WIDE
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(unspec:VNx4_NARROW
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[(match_operand:VNx4BI 2 "register_operand" "Upl")
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(match_operand:VNx4_NARROW 1 "memory_operand" "m")]
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UNSPEC_LD1_SVE)))]
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"TARGET_SVE"
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"ld1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.<VNx4_WIDE:Vetype>, %2/z, %1"
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)
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;; Predicated load and extend, with 2 elements per 128-bit block.
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(define_insn "@aarch64_load_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>"
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[(set (match_operand:VNx2_WIDE 0 "register_operand" "=w")
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(ANY_EXTEND:VNx2_WIDE
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(unspec:VNx2_NARROW
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[(match_operand:VNx2BI 2 "register_operand" "Upl")
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(match_operand:VNx2_NARROW 1 "memory_operand" "m")]
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UNSPEC_LD1_SVE)))]
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"TARGET_SVE"
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"ld1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.<VNx2_WIDE:Vetype>, %2/z, %1"
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(define_insn_and_rewrite "@aarch64_load_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>"
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[(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
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(unspec:SVE_HSDI
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[(match_operand:<SVE_HSDI:VPRED> 3 "general_operand" "UplDnm")
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(ANY_EXTEND:SVE_HSDI
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(unspec:SVE_PARTIAL_I
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[(match_operand:<SVE_PARTIAL_I:VPRED> 2 "register_operand" "Upl")
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(match_operand:SVE_PARTIAL_I 1 "memory_operand" "m")]
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UNSPEC_LD1_SVE))]
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UNSPEC_PRED_X))]
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"TARGET_SVE && (~<SVE_HSDI:narrower_mask> & <SVE_PARTIAL_I:self_mask>) == 0"
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"ld1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_HSDI:Vctype>, %2/z, %1"
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"&& !CONSTANT_P (operands[3])"
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{
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operands[3] = CONSTM1_RTX (<SVE_HSDI:VPRED>mode);
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}
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)
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;; -------------------------------------------------------------------------
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@ -1268,46 +1251,24 @@
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;; - LDNF1W
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;; -------------------------------------------------------------------------
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;; Predicated first-faulting or non-faulting load and extend, with 8 elements
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;; per 128-bit block.
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(define_insn "@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx8_WIDE:mode><VNx8_NARROW:mode>"
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[(set (match_operand:VNx8_WIDE 0 "register_operand" "=w")
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(ANY_EXTEND:VNx8_WIDE
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(unspec:VNx8_NARROW
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[(match_operand:VNx8BI 2 "register_operand" "Upl")
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(match_operand:VNx8_NARROW 1 "aarch64_sve_ld<fn>f1_operand" "Ut<fn>")
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(reg:VNx16BI FFRT_REGNUM)]
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SVE_LDFF1_LDNF1)))]
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"TARGET_SVE"
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"ld<fn>f1<ANY_EXTEND:s><VNx8_NARROW:Vesize>\t%0.<VNx8_WIDE:Vetype>, %2/z, %1"
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)
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;; Predicated first-faulting or non-faulting load and extend, with 4 elements
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;; per 128-bit block.
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(define_insn "@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>"
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[(set (match_operand:VNx4_WIDE 0 "register_operand" "=w")
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(ANY_EXTEND:VNx4_WIDE
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(unspec:VNx4_NARROW
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[(match_operand:VNx4BI 2 "register_operand" "Upl")
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(match_operand:VNx4_NARROW 1 "aarch64_sve_ld<fn>f1_operand" "Ut<fn>")
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(reg:VNx16BI FFRT_REGNUM)]
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SVE_LDFF1_LDNF1)))]
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"TARGET_SVE"
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"ld<fn>f1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.<VNx4_WIDE:Vetype>, %2/z, %1"
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)
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;; Predicated first-faulting or non-faulting load and extend, with 2 elements
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;; per 128-bit block.
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(define_insn "@aarch64_ld<fn>f1_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>"
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[(set (match_operand:VNx2_WIDE 0 "register_operand" "=w")
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(ANY_EXTEND:VNx2_WIDE
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(unspec:VNx2_NARROW
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[(match_operand:VNx2BI 2 "register_operand" "Upl")
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(match_operand:VNx2_NARROW 1 "aarch64_sve_ld<fn>f1_operand" "Ut<fn>")
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(reg:VNx16BI FFRT_REGNUM)]
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SVE_LDFF1_LDNF1)))]
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"TARGET_SVE"
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"ld<fn>f1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.<VNx2_WIDE:Vetype>, %2/z, %1"
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;; Predicated first-faulting or non-faulting load and extend.
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(define_insn_and_rewrite "@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>"
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[(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
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(unspec:SVE_HSDI
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[(match_operand:<SVE_HSDI:VPRED> 3 "general_operand" "UplDnm")
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(ANY_EXTEND:SVE_HSDI
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(unspec:SVE_PARTIAL_I
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[(match_operand:<SVE_PARTIAL_I:VPRED> 2 "register_operand" "Upl")
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(match_operand:SVE_PARTIAL_I 1 "aarch64_sve_ld<fn>f1_operand" "Ut<fn>")
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(reg:VNx16BI FFRT_REGNUM)]
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SVE_LDFF1_LDNF1))]
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UNSPEC_PRED_X))]
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"TARGET_SVE && (~<SVE_HSDI:narrower_mask> & <SVE_PARTIAL_I:self_mask>) == 0"
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"ld<fn>f1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_HSDI:Vctype>, %2/z, %1"
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"&& !CONSTANT_P (operands[3])"
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{
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operands[3] = CONSTM1_RTX (<SVE_HSDI:VPRED>mode);
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}
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)
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;; -------------------------------------------------------------------------
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@ -12879,6 +12879,49 @@ aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
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}
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}
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/* Return true if STMT_INFO extends the result of a load. */
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static bool
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aarch64_extending_load_p (stmt_vec_info stmt_info)
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{
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gassign *assign = dyn_cast <gassign *> (stmt_info->stmt);
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if (!assign || !CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (assign)))
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return false;
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tree rhs = gimple_assign_rhs1 (stmt_info->stmt);
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tree lhs_type = TREE_TYPE (gimple_assign_lhs (assign));
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tree rhs_type = TREE_TYPE (rhs);
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if (!INTEGRAL_TYPE_P (lhs_type)
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|| !INTEGRAL_TYPE_P (rhs_type)
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|| TYPE_PRECISION (lhs_type) <= TYPE_PRECISION (rhs_type))
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return false;
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stmt_vec_info def_stmt_info = stmt_info->vinfo->lookup_def (rhs);
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return (def_stmt_info
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&& STMT_VINFO_DATA_REF (def_stmt_info)
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&& DR_IS_READ (STMT_VINFO_DATA_REF (def_stmt_info)));
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}
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/* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
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for STMT_INFO, which has cost kind KIND. Adjust the cost as necessary
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for SVE targets. */
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static unsigned int
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aarch64_sve_adjust_stmt_cost (vect_cost_for_stmt kind, stmt_vec_info stmt_info,
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unsigned int stmt_cost)
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{
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/* Unlike vec_promote_demote, vector_stmt conversions do not change the
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vector register size or number of units. Integer promotions of this
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type therefore map to SXT[BHW] or UXT[BHW].
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Most loads have extending forms that can do the sign or zero extension
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on the fly. Optimistically assume that a load followed by an extension
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will fold to this form during combine, and that the extension therefore
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comes for free. */
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if (kind == vector_stmt && aarch64_extending_load_p (stmt_info))
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stmt_cost = 0;
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return stmt_cost;
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}
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/* Implement targetm.vectorize.add_stmt_cost. */
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static unsigned
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aarch64_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
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@ -12894,6 +12937,9 @@ aarch64_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
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int stmt_cost =
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aarch64_builtin_vectorization_cost (kind, vectype, misalign);
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if (stmt_info && vectype && aarch64_sve_mode_p (TYPE_MODE (vectype)))
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stmt_cost = aarch64_sve_adjust_stmt_cost (kind, stmt_info, stmt_cost);
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/* Statements in an inner loop relative to the loop being
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vectorized are weighted more heavily. The value here is
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arbitrary and could potentially be improved with analysis. */
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@ -1,3 +1,18 @@
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/load_extend_1.c: New test.
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* gcc.target/aarch64/sve/load_extend_2.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_3.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_4.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_5.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_6.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_7.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_8.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_9.c: Likewise.
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* gcc.target/aarch64/sve/load_extend_10.c: Likewise.
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* gcc.target/aarch64/sve/reduc_4.c: Add
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--param aarch64-sve-compare-costs=0.
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2019-11-16 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/cost_model_1.c: Expect the loop to be
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31
gcc/testsuite/gcc.target/aarch64/sve/load_extend_1.c
Normal file
31
gcc/testsuite/gcc.target/aarch64/sve/load_extend_1.c
Normal file
@ -0,0 +1,31 @@
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define TEST_LOOP(TYPE1, TYPE2) \
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void \
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f_##TYPE1##_##TYPE2 (TYPE1 *restrict dst, TYPE1 *restrict src1, \
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TYPE2 *restrict src2, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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dst[i] += src1[i] + src2[i]; \
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}
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#define TEST_ALL(T) \
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T (uint16_t, uint8_t) \
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T (uint32_t, uint8_t) \
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T (uint64_t, uint8_t) \
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T (uint32_t, uint16_t) \
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T (uint64_t, uint16_t) \
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T (uint64_t, uint32_t)
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TEST_ALL (TEST_LOOP)
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/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.h,} 1 } } */
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/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
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/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 1 } } */
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/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
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/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 1 } } */
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/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 1 } } */
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/* { dg-final { scan-assembler-not {\tuxt.\t} } } */
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||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_10.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_10.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint64_t *dst, uint32_t *src1, int16_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (int32_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1sh\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsxtw\tz[0-9]+\.d,} 1 } } */
|
||||
31
gcc/testsuite/gcc.target/aarch64/sve/load_extend_2.c
Normal file
31
gcc/testsuite/gcc.target/aarch64/sve/load_extend_2.c
Normal file
@ -0,0 +1,31 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define TEST_LOOP(TYPE1, TYPE2) \
|
||||
void \
|
||||
f_##TYPE1##_##TYPE2 (TYPE1 *restrict dst, TYPE1 *restrict src1, \
|
||||
TYPE2 *restrict src2, int n) \
|
||||
{ \
|
||||
for (int i = 0; i < n; ++i) \
|
||||
dst[i] += src1[i] + src2[i]; \
|
||||
}
|
||||
|
||||
#define TEST_ALL(T) \
|
||||
T (int16_t, int8_t) \
|
||||
T (int32_t, int8_t) \
|
||||
T (int64_t, int8_t) \
|
||||
T (int32_t, int16_t) \
|
||||
T (int64_t, int16_t) \
|
||||
T (int64_t, int32_t)
|
||||
|
||||
TEST_ALL (TEST_LOOP)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1sb\tz[0-9]+\.h,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1sb\tz[0-9]+\.s,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1sb\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1sh\tz[0-9]+\.s,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1sh\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1sw\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-not {\tsxt.\t} } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_3.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_3.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint32_t *dst, uint16_t *src1, uint8_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (uint16_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.s,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tuxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s,} 1 } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_4.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_4.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint64_t *dst, uint16_t *src1, uint8_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (uint16_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tuxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.d,} 1 } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_5.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_5.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint64_t *dst, uint32_t *src1, uint8_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (uint32_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tuxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 1 } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_6.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_6.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint64_t *dst, uint32_t *src1, uint16_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (uint32_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tuxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tuxtw\tz[0-9]+\.d,} 1 } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_7.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_7.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint32_t *dst, uint16_t *src1, int8_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (int16_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1sb\tz[0-9]+\.s,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsxth\tz[0-9]+\.s,} 1 } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_8.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_8.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint64_t *dst, uint16_t *src1, int8_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (int16_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1sb\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsxth\tz[0-9]+\.d,} 1 } } */
|
||||
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_9.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/load_extend_9.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=512" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void
|
||||
f1 (uint64_t *dst, uint32_t *src1, int8_t *src2)
|
||||
{
|
||||
for (int i = 0; i < 7; ++i)
|
||||
dst[i] += (int32_t) (src1[i] + src2[i]);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tld1sb\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d,} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tsxt.\t} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {\tsxtw\tz[0-9]+\.d,} 1 } } */
|
||||
@ -1,5 +1,5 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
|
||||
/* { dg-options "-O2 -ftree-vectorize -ffast-math --param aarch64-sve-compare-costs=0" } */
|
||||
|
||||
double
|
||||
f (double *restrict a, double *restrict b, int *lookup)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user