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re PR target/11965 (invalid assembler code for a shift << 32 operation)

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PR target/11965
	* config/sparc/sparc.c (sparc_v8plus_shift): Protect against
	constants greater than 63.
	* config/sparc/sparc.md (ashlsi3, ashrsi3, lshrsi3): Protect
	against constants greater than 31.
	(*ashldi3_sp64, *ashrdi3_sp64, *lshrdi3_sp64): Protect against
	constants greater than 63.

From-SVN: r71266
This commit is contained in:
Eric Botcazou 2003-09-10 12:59:36 +00:00
parent 80e46d778a
commit 1c8b4e29cc
5 changed files with 69 additions and 6 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2003-09-10 Martin Husemann <martin@duskware.de>
PR target/11965
* config/sparc/sparc.c (sparc_v8plus_shift): Protect against
constants greater than 63.
* config/sparc/sparc.md (ashlsi3, ashrsi3, lshrsi3): Protect
against constants greater than 31.
(*ashldi3_sp64, *ashrdi3_sp64, *lshrdi3_sp64): Protect against
constants greater than 63.
2003-09-09 Richard Henderson <rth@redhat.com>
* cgraphunit.c (cgraph_finalize_function): Remove unused argument.

4
gcc/config/sparc/sparc.c
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@ -8302,6 +8302,10 @@ sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
if (which_alternative != 2)
operands[3] = operands[0];
/* We can only shift by constants <= 63. */
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
if (GET_CODE (operands[1]) == CONST_INT)
{
output_asm_insn ("mov\t%1, %3", operands);

33
gcc/config/sparc/sparc.md
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@ -6908,6 +6908,8 @@
{
if (operands[2] == const1_rtx)
return "add\t%1, %1, %0";
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sll\t%1, %2, %0";
}
[(set (attr "type")
@ -6937,6 +6939,8 @@
{
if (operands[2] == const1_rtx)
return "add\t%1, %1, %0";
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "sllx\t%1, %2, %0";
}
[(set (attr "type")
@ -6996,7 +7000,11 @@
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
"sra\t%1, %2, %0"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sra\t%1, %2, %0";
}
[(set_attr "type" "shift")])
(define_insn "*ashrsi3_extend"
@ -7043,12 +7051,17 @@
}
})
(define_insn ""
(define_insn "*ashrdi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
"srax\t%1, %2, %0"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "srax\t%1, %2, %0";
}
[(set_attr "type" "shift")])
;; XXX
@ -7067,7 +7080,11 @@
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
"srl\t%1, %2, %0"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "srl\t%1, %2, %0";
}
[(set_attr "type" "shift")])
;; This handles the case where
@ -7124,12 +7141,16 @@
}
})
(define_insn ""
(define_insn "*lshrdi3_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
"srlx\t%1, %2, %0"
{
if (GET_CODE (operands[2]) == CONST_INT)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "srlx\t%1, %2, %0";
}
[(set_attr "type" "shift")])
;; XXX

3
gcc/testsuite/ChangeLog
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@ -1,3 +1,6 @@
2003-09-10 Eric Botcazou <ebotcazou@libertysurf.fr>
* gcc.dg/ultrasp10.c: New test.
2003-09-09 Devang Patel <dpatel@apple.com>

25
gcc/testsuite/gcc.dg/ultrasp10.c Normal file
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@ -0,0 +1,25 @@
/* PR target/11965 */
/* Originator: <jk@tools.de> */
/* { dg-do run { target sparc*-*-* } } */
/* { dg-options "-O -mcpu=ultrasparc" } */
/* This used to fail on 32-bit Ultrasparc because GCC emitted
an invalid shift instruction. */
static inline unsigned int shift(int n, unsigned int value)
{
return value << n;
}
unsigned int val = 1;
int main(void)
{
int i;
for (i = 0; i < 4; i++)
val = shift(32, val);
return 0;
}