mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2024-12-18 05:09:01 +08:00
Code Issues Packages Projects Releases Wiki Activity

- Really commit ctz patch.

Browse Source 
From-SVN: r62649
This commit is contained in:
David Edelsohn 2003-02-10 15:13:01 -05:00
parent 848f2ce8d5
commit 1b1edcfa61
1 changed files with 51 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
gcc/config/rs6000/rs6000.md
View File

@ -2364,15 +2364,21 @@
(const_int 0)))]
"")
(define_expand "ffssi2"
(define_insn "clzsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
""
"{cntlz|cntlzw} %0,%1")
(define_expand "ctzsi2"
[(set (match_dup 2)
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(parallel [(set (match_dup 3) (and:SI (match_dup 1)
(match_dup 2)))
(clobber (scratch:CC))])
(match_dup 2)))
(clobber (scratch:CC))])
(set (match_dup 4) (clz:SI (match_dup 3)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (const_int 32) (match_dup 4)))]
(minus:SI (const_int 31) (match_dup 4)))]
""
{
operands[2] = gen_reg_rtx (SImode);
@ -2380,12 +2386,22 @@
operands[4] = gen_reg_rtx (SImode);
})
(define_insn "clzsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
(define_expand "ffssi2"
[(set (match_dup 2)
(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(parallel [(set (match_dup 3) (and:SI (match_dup 1)
(match_dup 2)))
(clobber (scratch:CC))])
(set (match_dup 4) (clz:SI (match_dup 3)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (const_int 32) (match_dup 4)))]
""
"{cntlz|cntlzw} %0,%1")
{
operands[2] = gen_reg_rtx (SImode);
operands[3] = gen_reg_rtx (SImode);
operands[4] = gen_reg_rtx (SImode);
})
(define_expand "mulsi3"
[(use (match_operand:SI 0 "gpc_reg_operand" ""))
(use (match_operand:SI 1 "gpc_reg_operand" ""))
@ -6739,15 +6755,21 @@
(const_int 0)))]
"")
(define_expand "ffsdi2"
(define_insn "clzdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"cntlzd %0,%1")
(define_expand "ctzdi2"
[(set (match_dup 2)
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
(parallel [(set (match_dup 3) (and:DI (match_dup 1)
(match_dup 2)))
(clobber (scratch:CC))])
(match_dup 2)))
(clobber (scratch:CC))])
(set (match_dup 4) (clz:DI (match_dup 3)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(minus:DI (const_int 64) (match_dup 4)))]
(minus:DI (const_int 63) (match_dup 4)))]
"TARGET_POWERPC64"
{
operands[2] = gen_reg_rtx (DImode);
@ -6755,11 +6777,21 @@
operands[4] = gen_reg_rtx (DImode);
})
(define_insn "clzdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
(define_expand "ffsdi2"
[(set (match_dup 2)
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
(parallel [(set (match_dup 3) (and:DI (match_dup 1)
(match_dup 2)))
(clobber (scratch:CC))])
(set (match_dup 4) (clz:DI (match_dup 3)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(minus:DI (const_int 64) (match_dup 4)))]
"TARGET_POWERPC64"
"cntlzd %0,%1")
{
operands[2] = gen_reg_rtx (DImode);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
})
(define_insn "muldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")