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re PR target/23649 (gcc.dg/ppc-and-1.c failure due to not using rlwinm)
PR target/23649 * config/rs6000/predicates.md (mask_operand): Only handle rlwinm masks. (mask64_operand): Reinstate code prior to 2005-06-11 change. (mask64_2_operand): Reinstate code prior to 2004-11-11 change. (and64_2_operand): Tweak to use predicate. (and_operand): Adjust for mask_operand changes. * config/rs6000/rs6000.c (num_insns_constant): Revert 2005-06-11. (print_operand): Likewise. (rs6000_rtx_costs): Pass mode to mask_operand and use mask64_operand. (mask64_1or2_operand): Delete. * rs6000/rs6000-protos.h (mask64_1or2_operand): Delete. * config/rs6000/rs6000.h (EXTRA_CONSTRAINT <S>): Revert 2005-06-11. (EXTRA_CONSTRAINT <T>): Pass operand mode to predicate. (EXTRA_CONSTRAINT <t>): Disallow mask64_operand matches. * config/rs6000/rs6000.md (andsi3_internal3 split): Revert 2005-06-11. (rotldi3_internal4): Likewise. (rotldi3_internal5, rotldi3_internal5 split): Likewise. (rotldi3_internal6, rotldi3_internal6 split): Likewise. (ashldi3_internal7): Likewise. (ashldi3_internal8, ashldi3_internal8 split): Likewise. (ashldi3_internal, ashldi3_internal9 split): Likewise. (anddi3 split): Don't match mask64_operand. (anddi3_internal2): Add rlwinm. Modify 't' splitter predicate. (anddi3_internal3): Add rlwinm. Use and64_2_operand in non-cr0 splitter and match TARGET_64BIT not TARGET_POWERPC64. Modify 't' splitter predicate. (movdi_internal64 + 2): Revert 2005-06-11 change. From-SVN: r103716
This commit is contained in:
Alan Modra
Alan Modra
parent
e9555b1376
commit
1990cd7969
gcc
@ -1,3 +1,33 @@
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2005-09-01 Alan Modra <amodra@bigpond.net.au>
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PR target/23649
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* config/rs6000/predicates.md (mask_operand): Only handle rlwinm masks.
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(mask64_operand): Reinstate code prior to 2005-06-11 change.
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(mask64_2_operand): Reinstate code prior to 2004-11-11 change.
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(and64_2_operand): Tweak to use predicate.
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(and_operand): Adjust for mask_operand changes.
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* config/rs6000/rs6000.c (num_insns_constant): Revert 2005-06-11.
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(print_operand): Likewise.
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(rs6000_rtx_costs): Pass mode to mask_operand and use mask64_operand.
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(mask64_1or2_operand): Delete.
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* rs6000/rs6000-protos.h (mask64_1or2_operand): Delete.
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* config/rs6000/rs6000.h (EXTRA_CONSTRAINT <S>): Revert 2005-06-11.
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(EXTRA_CONSTRAINT <T>): Pass operand mode to predicate.
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(EXTRA_CONSTRAINT <t>): Disallow mask64_operand matches.
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* config/rs6000/rs6000.md (andsi3_internal3 split): Revert 2005-06-11.
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(rotldi3_internal4): Likewise.
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(rotldi3_internal5, rotldi3_internal5 split): Likewise.
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(rotldi3_internal6, rotldi3_internal6 split): Likewise.
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(ashldi3_internal7): Likewise.
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(ashldi3_internal8, ashldi3_internal8 split): Likewise.
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(ashldi3_internal, ashldi3_internal9 split): Likewise.
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(anddi3 split): Don't match mask64_operand.
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(anddi3_internal2): Add rlwinm. Modify 't' splitter predicate.
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(anddi3_internal3): Add rlwinm. Use and64_2_operand in non-cr0
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splitter and match TARGET_64BIT not TARGET_POWERPC64. Modify
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't' splitter predicate.
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(movdi_internal64 + 2): Revert 2005-06-11 change.
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2005-08-31 DJ Delorie <dj@redhat.com>
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* config/m32c/m32c.c (m32c_valid_pointer_mode): New.
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@ -452,14 +452,10 @@
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(and (not (match_operand 0 "logical_operand"))
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(match_operand 0 "reg_or_logical_cint_operand"))))
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;; For SImode, return 1 if op is a constant that can be encoded in a
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;; 32-bit mask (no more than two 1->0 or 0->1 transitions). Reject
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;; all ones and all zeros, since these should have been optimized away
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;; and confuse the making of MB and ME.
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;; For DImode, return 1 if the operand is a constant that is a
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;; PowerPC64 mask (no more than one 1->0 or 0->1 transitions). Reject
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;; all zeros, since zero should have been optimized away and confuses
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;; the making of MB and ME.
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;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
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;; suitable for use with rlwinm (no more than two 1->0 or 0->1
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;; transitions). Reject all ones and all zeros, since these should have
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;; been optimized away and confuse the making of MB and ME.
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(define_predicate "mask_operand"
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(match_code "const_int")
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{
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@ -467,34 +463,38 @@
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c = INTVAL (op);
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/* Fail in 64-bit mode if the mask wraps around because the upper
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32-bits of the mask will all be 1s, contrary to GCC's internal view. */
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if (mode == SImode && TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
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return 0;
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if (TARGET_POWERPC64)
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{
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/* Fail if the mask is not 32-bit. */
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if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
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return 0;
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/* Reject all zeros or all ones in 32-bit mode. */
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if (c == 0 || (mode == SImode && c == -1))
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return 0;
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/* Fail if the mask wraps around because the upper 32-bits of the
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mask will all be 1s, contrary to GCC's internal view. */
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if ((c & 0x80000001) == 0x80000001)
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return 0;
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}
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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if (c & 1)
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c = ~c;
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/* Reject all zeros or all ones. */
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if (c == 0)
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return 0;
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/* Find the first transition. */
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lsb = c & -c;
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if (mode == SImode)
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{
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/* Invert to look for a second transition. */
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c = ~c;
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/* Invert to look for a second transition. */
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c = ~c;
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/* Erase first transition. */
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c &= -lsb;
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/* Erase first transition. */
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c &= -lsb;
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/* Find the second transition (if any). */
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lsb = c & -c;
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}
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/* Find the second transition (if any). */
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lsb = c & -c;
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/* Match if all the bits above are 1's (or c is zero). */
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return c == -lsb;
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@ -522,20 +522,81 @@
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return c == -lsb;
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})
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;; Like mask_operand, but allow up to three transitions. This
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;; Return 1 if the operand is a constant that is a PowerPC64 mask
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;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
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;; transition). Reject all zeros, since zero should have been
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;; optimized away and confuses the making of MB and ME.
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(define_predicate "mask64_operand"
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(match_code "const_int")
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{
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HOST_WIDE_INT c, lsb;
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c = INTVAL (op);
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/* Reject all zeros. */
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if (c == 0)
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return 0;
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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if (c & 1)
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c = ~c;
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/* Find the first transition. */
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lsb = c & -c;
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/* Match if all the bits above are 1's (or c is zero). */
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return c == -lsb;
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})
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;; Like mask64_operand, but allow up to three transitions. This
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;; predicate is used by insn patterns that generate two rldicl or
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;; rldicr machine insns.
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(define_predicate "mask64_2_operand"
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(match_code "const_int")
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{
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return mask64_1or2_operand (op, mode, false);
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HOST_WIDE_INT c, lsb;
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c = INTVAL (op);
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/* Disallow all zeros. */
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if (c == 0)
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return 0;
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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if (c & 1)
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c = ~c;
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/* Find the first transition. */
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lsb = c & -c;
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/* Invert to look for a second transition. */
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c = ~c;
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/* Erase first transition. */
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c &= -lsb;
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/* Find the second transition. */
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lsb = c & -c;
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/* Invert to look for a third transition. */
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c = ~c;
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/* Erase second transition. */
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c &= -lsb;
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/* Find the third transition (if any). */
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lsb = c & -c;
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/* Match if all the bits above are 1's (or c is zero). */
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return c == -lsb;
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})
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;; Like and_operand, but also match constants that can be implemented
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;; with two rldicl or rldicr insns.
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(define_predicate "and64_2_operand"
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(ior (and (match_code "const_int")
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(match_test "mask64_1or2_operand (op, mode, true)"))
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(ior (match_operand 0 "mask64_2_operand")
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(if_then_else (match_test "fixed_regs[CR0_REGNO]")
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(match_operand 0 "gpc_reg_operand")
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(match_operand 0 "logical_operand"))))
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@ -544,9 +605,11 @@
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;; constant that can be used as the operand of a logical AND.
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(define_predicate "and_operand"
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(ior (match_operand 0 "mask_operand")
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(if_then_else (match_test "fixed_regs[CR0_REGNO]")
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(match_operand 0 "gpc_reg_operand")
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(match_operand 0 "logical_operand"))))
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(ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
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(match_operand 0 "mask64_operand"))
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(if_then_else (match_test "fixed_regs[CR0_REGNO]")
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(match_operand 0 "gpc_reg_operand")
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(match_operand 0 "logical_operand")))))
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;; Return 1 if the operand is either a logical operand or a short cint operand.
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(define_predicate "scc_eq_operand"
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@ -34,7 +34,6 @@ extern void rs6000_va_start (tree, rtx);
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extern int easy_vector_same (rtx, enum machine_mode);
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extern int easy_vector_splat_const (int, enum machine_mode);
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extern int mask64_1or2_operand (rtx, enum machine_mode, bool);
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extern bool macho_lo_sum_memory_operand (rtx, enum machine_mode);
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extern int num_insns_constant (rtx, enum machine_mode);
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extern int num_insns_constant_wide (HOST_WIDE_INT);
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@ -1980,7 +1980,7 @@ num_insns_constant (rtx op, enum machine_mode mode)
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case CONST_INT:
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#if HOST_BITS_PER_WIDE_INT == 64
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if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
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&& mask_operand (op, mode))
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&& mask64_operand (op, mode))
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return 2;
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else
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#endif
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@ -2022,7 +2022,7 @@ num_insns_constant (rtx op, enum machine_mode mode)
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|| (high == -1 && low < 0))
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return num_insns_constant_wide (low);
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else if (mask_operand (op, mode))
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else if (mask64_operand (op, mode))
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return 2;
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else if (low == 0)
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@ -2346,61 +2346,6 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
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emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
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}
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int
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mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
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bool allow_one)
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{
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if (GET_CODE (op) == CONST_INT)
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{
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HOST_WIDE_INT c, lsb;
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bool one_ok;
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c = INTVAL (op);
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/* Disallow all zeros. */
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if (c == 0)
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return 0;
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/* We can use a single rlwinm insn if no upper bits of C are set
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AND there are zero, one or two transitions in the _whole_ of
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C. */
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one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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if (c & 1)
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c = ~c;
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/* Find the first transition. */
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lsb = c & -c;
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/* Invert to look for a second transition. */
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c = ~c;
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/* Erase first transition. */
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c &= -lsb;
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/* Find the second transition. */
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lsb = c & -c;
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/* Invert to look for a third transition. */
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c = ~c;
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/* Erase second transition. */
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c &= -lsb;
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if (one_ok && !(allow_one || c))
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return 0;
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/* Find the third transition (if any). */
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lsb = c & -c;
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/* Match if all the bits above are 1's (or c is zero). */
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return c == -lsb;
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}
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return 0;
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}
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/* Generates shifts and masks for a pair of rldicl or rldicr insns to
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implement ANDing by the mask IN. */
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void
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@ -10379,7 +10324,7 @@ print_operand (FILE *file, rtx x, int code)
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/* PowerPC64 mask position. All 0's is excluded.
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CONST_INT 32-bit mask is considered sign-extended so any
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transition must occur within the CONST_INT, not on the boundary. */
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if (! mask_operand (x, DImode))
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if (! mask64_operand (x, DImode))
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output_operand_lossage ("invalid %%S value");
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uval = INT_LOWPART (x);
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@ -18235,7 +18180,9 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
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&& (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
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|| (CONST_OK_FOR_LETTER_P (INTVAL (x),
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mode == SImode ? 'L' : 'J'))
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|| mask_operand (x, VOIDmode)))
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|| mask_operand (x, mode)
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|| (mode == DImode
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&& mask64_operand (x, DImode))))
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|| ((outer_code == IOR || outer_code == XOR)
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&& (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
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|| (CONST_OK_FOR_LETTER_P (INTVAL (x),
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@ -18287,7 +18234,8 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
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&& ((outer_code == AND
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&& (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
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|| CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
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|| mask_operand (x, DImode)))
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|| mask_operand (x, DImode)
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|| mask64_operand (x, DImode)))
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|| ((outer_code == IOR || outer_code == XOR)
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&& CONST_DOUBLE_HIGH (x) == 0
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&& (CONST_DOUBLE_LOW (x)
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@ -1105,26 +1105,28 @@ enum reg_class
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'Q' means that is a memory operand that is just an offset from a reg.
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'R' is for AIX TOC entries.
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'S' is a constant that can be placed into a 64-bit mask operand
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'T' is a constant that can be placed into a 32-bit mask operand
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'S' is a constant that can be placed into a 64-bit mask operand.
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'T' is a constant that can be placed into a 32-bit mask operand.
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'U' is for V.4 small data references.
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'W' is a vector constant that can be easily generated (no mem refs).
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'Y' is an indexed or word-aligned displacement memory operand.
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'Z' is an indexed or indirect memory operand.
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'a' is an indexed or indirect address operand.
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't' is for AND masks that can be performed by two rldic{l,r} insns. */
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't' is for AND masks that can be performed by two rldic{l,r} insns
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(but excluding those that could match other constraints of anddi3.) */
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#define EXTRA_CONSTRAINT(OP, C) \
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((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
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: (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
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: (C) == 'S' ? mask_operand (OP, DImode) \
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: (C) == 'T' ? mask_operand (OP, SImode) \
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: (C) == 'S' ? mask64_operand (OP, DImode) \
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: (C) == 'T' ? mask_operand (OP, GET_MODE (OP)) \
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: (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
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&& small_data_operand (OP, GET_MODE (OP))) \
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: (C) == 't' ? (mask64_2_operand (OP, DImode) \
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&& (fixed_regs[CR0_REGNO] \
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|| !logical_operand (OP, DImode)) \
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&& !mask_operand (OP, DImode)) \
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&& !mask_operand (OP, DImode) \
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&& !mask64_operand (OP, DImode)) \
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: (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
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: (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
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: (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \
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@ -5979,7 +5979,7 @@
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
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(match_operand:DI 2 "reg_or_cint_operand" "ri"))
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(match_operand:DI 3 "mask_operand" "n")))]
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(match_operand:DI 3 "mask64_operand" "n")))]
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"TARGET_POWERPC64"
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"rld%I2c%B3 %0,%1,%H2,%S3")
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@ -5988,7 +5988,7 @@
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(compare:CC (and:DI
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(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
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(match_operand:DI 3 "mask_operand" "n,n"))
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||||
(match_operand:DI 3 "mask64_operand" "n,n"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 "=r,r"))]
|
||||
"TARGET_64BIT"
|
||||
@ -6003,7 +6003,7 @@
|
||||
(compare:CC (and:DI
|
||||
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_cint_operand" ""))
|
||||
(match_operand:DI 3 "mask_operand" ""))
|
||||
(match_operand:DI 3 "mask64_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
@ -6021,7 +6021,7 @@
|
||||
(compare:CC (and:DI
|
||||
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
|
||||
(match_operand:DI 3 "mask_operand" "n,n"))
|
||||
(match_operand:DI 3 "mask64_operand" "n,n"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
@ -6037,7 +6037,7 @@
|
||||
(compare:CC (and:DI
|
||||
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "reg_or_cint_operand" ""))
|
||||
(match_operand:DI 3 "mask_operand" ""))
|
||||
(match_operand:DI 3 "mask64_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
@ -6435,7 +6435,7 @@
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "i"))
|
||||
(match_operand:DI 3 "mask_operand" "n")))]
|
||||
(match_operand:DI 3 "mask64_operand" "n")))]
|
||||
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
"rldicr %0,%1,%H2,%S3")
|
||||
|
||||
@ -6444,7 +6444,7 @@
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "const_int_operand" "i,i"))
|
||||
(match_operand:DI 3 "mask_operand" "n,n"))
|
||||
(match_operand:DI 3 "mask64_operand" "n,n"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 "=r,r"))]
|
||||
"TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
@ -6459,7 +6459,7 @@
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" ""))
|
||||
(match_operand:DI 3 "mask_operand" ""))
|
||||
(match_operand:DI 3 "mask64_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
@ -6477,7 +6477,7 @@
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "const_int_operand" "i,i"))
|
||||
(match_operand:DI 3 "mask_operand" "n,n"))
|
||||
(match_operand:DI 3 "mask64_operand" "n,n"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
@ -6493,7 +6493,7 @@
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" ""))
|
||||
(match_operand:DI 3 "mask_operand" ""))
|
||||
(match_operand:DI 3 "mask64_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
@ -6698,7 +6698,8 @@
|
||||
(clobber (match_scratch:CC 3 ""))]
|
||||
"TARGET_POWERPC64
|
||||
&& (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
|
||||
&& !mask_operand (operands[2], DImode)"
|
||||
&& !mask_operand (operands[2], DImode)
|
||||
&& !mask64_operand (operands[2], DImode)"
|
||||
[(set (match_dup 0)
|
||||
(and:DI (rotate:DI (match_dup 1)
|
||||
(match_dup 4))
|
||||
@ -6712,16 +6713,17 @@
|
||||
})
|
||||
|
||||
(define_insn "*anddi3_internal2"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
|
||||
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
|
||||
(match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
|
||||
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
|
||||
(match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
|
||||
(clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
|
||||
(clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
|
||||
(clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
and. %3,%1,%2
|
||||
rldic%B2. %3,%1,0,%S2
|
||||
rlwinm. %3,%1,0,%m2,%M2
|
||||
andi. %3,%1,%b2
|
||||
andis. %3,%1,%u2
|
||||
#
|
||||
@ -6729,9 +6731,10 @@
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
|
||||
(set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
|
||||
[(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
|
||||
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "")
|
||||
@ -6740,9 +6743,10 @@
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 ""))
|
||||
(clobber (match_scratch:CC 4 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
"TARGET_64BIT && reload_completed
|
||||
&& (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
|
||||
&& !mask_operand (operands[2], DImode)"
|
||||
&& !mask_operand (operands[2], DImode)
|
||||
&& !mask64_operand (operands[2], DImode)"
|
||||
[(set (match_dup 3)
|
||||
(and:DI (rotate:DI (match_dup 1)
|
||||
(match_dup 5))
|
||||
@ -6759,17 +6763,18 @@
|
||||
}")
|
||||
|
||||
(define_insn "*anddi3_internal3"
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
|
||||
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
|
||||
(match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
|
||||
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
|
||||
(match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
|
||||
(and:DI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
|
||||
(clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
and. %0,%1,%2
|
||||
rldic%B2. %0,%1,0,%S2
|
||||
rlwinm. %0,%1,0,%m2,%M2
|
||||
andi. %0,%1,%b2
|
||||
andis. %0,%1,%u2
|
||||
#
|
||||
@ -6777,19 +6782,20 @@
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
|
||||
(set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
|
||||
[(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
|
||||
(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "and_operand" ""))
|
||||
(match_operand:DI 2 "and64_2_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(and:DI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_scratch:CC 4 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
"TARGET_64BIT && reload_completed"
|
||||
[(parallel [(set (match_dup 0)
|
||||
(and:DI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_dup 4))])
|
||||
@ -6806,9 +6812,10 @@
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(and:DI (match_dup 1) (match_dup 2)))
|
||||
(clobber (match_scratch:CC 4 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
"TARGET_64BIT && reload_completed
|
||||
&& (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
|
||||
&& !mask_operand (operands[2], DImode)"
|
||||
&& !mask_operand (operands[2], DImode)
|
||||
&& !mask64_operand (operands[2], DImode)"
|
||||
[(set (match_dup 0)
|
||||
(and:DI (rotate:DI (match_dup 1)
|
||||
(match_dup 5))
|
||||
@ -8024,7 +8031,7 @@
|
||||
;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(match_operand:DI 1 "mask_operand" ""))]
|
||||
(match_operand:DI 1 "mask64_operand" ""))]
|
||||
"TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
|
||||
[(set (match_dup 0) (const_int -1))
|
||||
(set (match_dup 0)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user