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2004-11-22 James A. Morrison <phython@gcc.gnu.org
* config/sparc/sparc.c: Include insn-codes.h and langhooks.h.
(sparc_init_builtins): New function.
(sparc_init_vis_builtins): Create builtin functions for VIS
instructions.
(sparc_expand_builtin): Expand builtin functions for VIS instructions.
(TARGET_INIT_BUILTINS): Define to sparc_init_builtins.
(TARGET_EXPAND_BUILTIN): Define to sparc_expand_builtin.
(def_builtin): New macro for creating builtin functions.
(P): New mode macro for pointer types.
(UNSPEC_FPACK16, UNSPEC_FPACK32, UNSPEC_FPACKFIX, UNSPEC_FEXPAND,
UNSPEC_FPMERGE, UNSPEC_MUL16AL, UNSPEC_MUL8UL, UNSPEC_MULDUL,
UNSPEC_ALIGNDATA, UNSPEC_ALIGNADDR, UNSPEC_PDIST): New constants.
(fpack16_vis, fpackfix_vis, fpack32_vis, fexpand_vis, fpmerge_vis,
fmul8x16_vis, fmul8x16au_vis, fmul8x16al_vis, fmul8sux16_vis,
fmul8ulx16_vis, fmuld8sux16_vis, fmuld8ulx16_vis, pdist_vis,
faligndata<V64:mode>_vis, alignaddr<P:mode>_vis): New patterns.
testsuite:
* gcc.target/sparc/align.c, gcc.target/sparc/combined-2.c,
gcc.target/sparc/fpack16.c, gcc.target/sparc/fpack32.c,
gcc.target/sparc/fpackfix.c, gcc.target/fexpand.c,
gcc.target/sparc/fpmerge.c, gcc.target/sparc/fpmul.c,
gcc.target/sparc/pdist.c: New tests.
From-SVN: r91057
This commit is contained in:
James A. Morrison
parent
3174451e16
commit
16f592418f
@ -1,3 +1,22 @@
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2004-11-22 James A. Morrison <phython@gcc.gnu.org
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* config/sparc/sparc.c: Include insn-codes.h and langhooks.h.
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(sparc_init_builtins): New function.
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(sparc_init_vis_builtins): Create builtin functions for VIS
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instructions.
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(sparc_expand_builtin): Expand builtin functions for VIS instructions.
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(TARGET_INIT_BUILTINS): Define to sparc_init_builtins.
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(TARGET_EXPAND_BUILTIN): Define to sparc_expand_builtin.
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(def_builtin): New macro for creating builtin functions.
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(P): New mode macro for pointer types.
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(UNSPEC_FPACK16, UNSPEC_FPACK32, UNSPEC_FPACKFIX, UNSPEC_FEXPAND,
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UNSPEC_FPMERGE, UNSPEC_MUL16AL, UNSPEC_MUL8UL, UNSPEC_MULDUL,
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UNSPEC_ALIGNDATA, UNSPEC_ALIGNADDR, UNSPEC_PDIST): New constants.
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(fpack16_vis, fpackfix_vis, fpack32_vis, fexpand_vis, fpmerge_vis,
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fmul8x16_vis, fmul8x16au_vis, fmul8x16al_vis, fmul8sux16_vis,
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fmul8ulx16_vis, fmuld8sux16_vis, fmuld8ulx16_vis, pdist_vis,
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faligndata<V64:mode>_vis, alignaddr<P:mode>_vis): New patterns.
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2004-11-22 Devang Patel <dpatel@apple.com>
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* tree-if-conv.c (clean_predicate_lists): Clean all basic blocks.
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@ -32,6 +32,7 @@ Boston, MA 02111-1307, USA. */
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "insn-codes.h"
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#include "conditions.h"
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#include "output.h"
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#include "insn-attr.h"
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@ -48,6 +49,7 @@ Boston, MA 02111-1307, USA. */
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#include "target-def.h"
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#include "cfglayout.h"
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#include "tree-gimple.h"
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#include "langhooks.h"
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/* Processor costs */
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static const
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@ -332,6 +334,9 @@ static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
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static bool sparc_function_ok_for_sibcall (tree, tree);
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static void sparc_init_libfuncs (void);
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static void sparc_init_builtins (void);
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static void sparc_vis_init_builtins (void);
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static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
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static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
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HOST_WIDE_INT, tree);
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static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT,
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@ -417,6 +422,11 @@ enum processor_type sparc_cpu;
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#undef TARGET_INIT_LIBFUNCS
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#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
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#undef TARGET_INIT_BUILTINS
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#define TARGET_INIT_BUILTINS sparc_init_builtins
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#undef TARGET_EXPAND_BUILTIN
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#define TARGET_EXPAND_BUILTIN sparc_expand_builtin
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#ifdef HAVE_AS_TLS
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#undef TARGET_HAVE_TLS
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@ -8446,6 +8456,163 @@ sparc_init_libfuncs (void)
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gofast_maybe_init_libfuncs ();
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}
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#define def_builtin(NAME, CODE, TYPE) \
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lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \
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NULL_TREE)
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/* Implement the TARGET_INIT_BUILTINS target hook.
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Create builtin functions for special SPARC instructions. */
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static void
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sparc_init_builtins (void)
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{
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if (TARGET_VIS)
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sparc_vis_init_builtins ();
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}
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/* Create builtin functions for VIS 1.0 instructions. */
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static void
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sparc_vis_init_builtins (void)
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{
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tree v4qi = build_vector_type (unsigned_intQI_type_node, 4);
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tree v8qi = build_vector_type (unsigned_intQI_type_node, 8);
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tree v4hi = build_vector_type (intHI_type_node, 4);
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tree v2hi = build_vector_type (intHI_type_node, 2);
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tree v2si = build_vector_type (intSI_type_node, 2);
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tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0);
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tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0);
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tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0);
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tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0);
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tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0);
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tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0);
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tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0);
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tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0);
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tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0);
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tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0);
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tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0);
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tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0);
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tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node,
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v8qi, v8qi,
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intDI_type_node, 0);
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tree di_ftype_di_di = build_function_type_list (intDI_type_node,
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intDI_type_node,
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intDI_type_node, 0);
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tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node,
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ptr_type_node,
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intSI_type_node, 0);
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tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node,
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ptr_type_node,
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intDI_type_node, 0);
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/* Packing and expanding vectors. */
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def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi);
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def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
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v8qi_ftype_v2si_v8qi);
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def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
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v2hi_ftype_v2si);
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def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi);
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def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
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v8qi_ftype_v4qi_v4qi);
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/* Multiplications. */
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def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis,
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v4hi_ftype_v4qi_v4hi);
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def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis,
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v4hi_ftype_v4qi_v2hi);
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def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis,
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v4hi_ftype_v4qi_v2hi);
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def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis,
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v4hi_ftype_v8qi_v4hi);
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def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis,
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v4hi_ftype_v8qi_v4hi);
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def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis,
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v2si_ftype_v4qi_v2hi);
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def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis,
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v2si_ftype_v4qi_v2hi);
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/* Data aligning. */
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def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
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v4hi_ftype_v4hi_v4hi);
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def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
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v8qi_ftype_v8qi_v8qi);
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def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
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v2si_ftype_v2si_v2si);
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def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
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di_ftype_di_di);
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if (TARGET_ARCH64)
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def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
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ptr_ftype_ptr_di);
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else
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def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
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ptr_ftype_ptr_si);
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/* Pixel distance. */
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def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis,
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di_ftype_v8qi_v8qi_di);
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}
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/* Handle TARGET_EXPAND_BUILTIN target hook.
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Expand builtin functions for sparc instrinsics. */
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static rtx
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sparc_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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enum machine_mode tmode, int ignore ATTRIBUTE_UNUSED)
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{
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tree arglist;
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tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
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unsigned int icode = DECL_FUNCTION_CODE (fndecl);
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rtx pat, op[4];
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enum machine_mode mode[4];
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int arg_count = 0;
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mode[arg_count] = tmode;
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if (target == 0
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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op[arg_count] = gen_reg_rtx (tmode);
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else
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op[arg_count] = target;
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for (arglist = TREE_OPERAND (exp, 1); arglist;
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arglist = TREE_CHAIN (arglist))
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{
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tree arg = TREE_VALUE (arglist);
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arg_count++;
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mode[arg_count] = insn_data[icode].operand[arg_count].mode;
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op[arg_count] = expand_expr (arg, NULL_RTX, VOIDmode, 0);
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if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
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mode[arg_count]))
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op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
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}
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switch (arg_count)
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{
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case 1:
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pat = GEN_FCN (icode) (op[0], op[1]);
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break;
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case 2:
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pat = GEN_FCN (icode) (op[0], op[1], op[2]);
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break;
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case 3:
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pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
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break;
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default:
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gcc_unreachable ();
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}
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if (!pat)
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return NULL_RTX;
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emit_insn (pat);
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return op[0];
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}
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int
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sparc_extra_constraint_check (rtx op, int c, int strict)
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{
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@ -45,6 +45,18 @@
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(UNSPEC_TLSIE 33)
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(UNSPEC_TLSLE 34)
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(UNSPEC_TLSLD_BASE 35)
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(UNSPEC_FPACK16 40)
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(UNSPEC_FPACK32 41)
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(UNSPEC_FPACKFIX 42)
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(UNSPEC_FEXPAND 43)
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(UNSPEC_FPMERGE 44)
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(UNSPEC_MUL16AL 45)
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(UNSPEC_MUL8UL 46)
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(UNSPEC_MULDUL 47)
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(UNSPEC_ALIGNDATA 48)
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(UNSPEC_ALIGNADDR 49)
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(UNSPEC_PDIST 50)
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])
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(define_constants
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@ -8961,3 +8973,161 @@
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"fnands\t%1, %2, %0"
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[(set_attr "type" "fga")
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(set_attr "fptype" "single")])
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;; Hard to generate VIS instructions. We have builtins for these.
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(define_insn "fpack16_vis"
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[(set (match_operand:V4QI 0 "register_operand" "=f")
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(unspec:V4QI [(match_operand:V4HI 1 "register_operand" "e")]
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UNSPEC_FPACK16))]
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"TARGET_VIS"
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"fpack16\t%1, %0"
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[(set_attr "type" "fga")
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(set_attr "fptype" "double")])
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(define_insn "fpackfix_vis"
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[(set (match_operand:V2HI 0 "register_operand" "=f")
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(unspec:V2HI [(match_operand:V2SI 1 "register_operand" "e")]
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UNSPEC_FPACKFIX))]
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"TARGET_VIS"
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"fpackfix\t%1, %0"
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[(set_attr "type" "fga")
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(set_attr "fptype" "double")])
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(define_insn "fpack32_vis"
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[(set (match_operand:V8QI 0 "register_operand" "=e")
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(unspec:V8QI [(match_operand:V2SI 1 "register_operand" "e")
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(match_operand:V8QI 2 "register_operand" "e")]
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UNSPEC_FPACK32))]
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"TARGET_VIS"
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"fpack32\t%1, %2, %0"
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[(set_attr "type" "fga")
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(set_attr "fptype" "double")])
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(define_insn "fexpand_vis"
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[(set (match_operand:V4HI 0 "register_operand" "=e")
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(unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")]
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UNSPEC_FEXPAND))]
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"TARGET_VIS"
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"fexpand\t%1, %0"
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[(set_attr "type" "fga")
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(set_attr "fptype" "double")])
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;; It may be possible to describe this operation as (1 indexed):
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;; (vec_select (vec_duplicate (vec_duplicate (vec_concat 1 2)))
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;; 1,5,10,14,19,23,28,32)
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;; Note that (vec_merge:V8QI [(V4QI) (V4QI)] (10101010 = 170) doesn't work
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;; because vec_merge expects all the operands to be of the same type.
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(define_insn "fpmerge_vis"
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[(set (match_operand:V8QI 0 "register_operand" "=e")
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(unspec:V8QI [(match_operand:V4QI 1 "register_operand" "f")
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(match_operand:V4QI 2 "register_operand" "f")]
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UNSPEC_FPMERGE))]
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"TARGET_VIS"
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"fpmerge\t%1, %2, %0"
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[(set_attr "type" "fga")
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(set_attr "fptype" "double")])
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;; Partitioned multiply instructions
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(define_insn "fmul8x16_vis"
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[(set (match_operand:V4HI 0 "register_operand" "=e")
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(mult:V4HI (match_operand:V4QI 1 "register_operand" "f")
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(match_operand:V4HI 2 "register_operand" "e")))]
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"TARGET_VIS"
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"fmul8x16\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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;; Only one of the following two insns can be a multiply.
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(define_insn "fmul8x16au_vis"
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[(set (match_operand:V4HI 0 "register_operand" "=e")
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(mult:V4HI (match_operand:V4QI 1 "register_operand" "f")
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(match_operand:V2HI 2 "register_operand" "f")))]
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"TARGET_VIS"
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"fmul8x16au\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fmul8x16al_vis"
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[(set (match_operand:V4HI 0 "register_operand" "=e")
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(unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")
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(match_operand:V2HI 2 "register_operand" "f")]
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UNSPEC_MUL16AL))]
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"TARGET_VIS"
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"fmul8x16al\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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;; Only one of the following two insns can be a multiply.
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(define_insn "fmul8sux16_vis"
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[(set (match_operand:V4HI 0 "register_operand" "=e")
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(mult:V4HI (match_operand:V8QI 1 "register_operand" "e")
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(match_operand:V4HI 2 "register_operand" "e")))]
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"TARGET_VIS"
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"fmul8sux16\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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(define_insn "fmul8ulx16_vis"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=e")
|
||||
(unspec:V4HI [(match_operand:V8QI 1 "register_operand" "e")
|
||||
(match_operand:V4HI 2 "register_operand" "e")]
|
||||
UNSPEC_MUL8UL))]
|
||||
"TARGET_VIS"
|
||||
"fmul8ulx16\t%1, %2, %0"
|
||||
[(set_attr "type" "fpmul")
|
||||
(set_attr "fptype" "double")])
|
||||
|
||||
;; Only one of the following two insns can be a multiply.
|
||||
(define_insn "fmuld8sux16_vis"
|
||||
[(set (match_operand:V2SI 0 "register_operand" "=e")
|
||||
(mult:V2SI (match_operand:V4QI 1 "register_operand" "f")
|
||||
(match_operand:V2HI 2 "register_operand" "f")))]
|
||||
"TARGET_VIS"
|
||||
"fmuld8sux16\t%1, %2, %0"
|
||||
[(set_attr "type" "fpmul")
|
||||
(set_attr "fptype" "double")])
|
||||
|
||||
(define_insn "fmuld8ulx16_vis"
|
||||
[(set (match_operand:V2SI 0 "register_operand" "=e")
|
||||
(unspec:V2SI [(match_operand:V4QI 1 "register_operand" "f")
|
||||
(match_operand:V2HI 2 "register_operand" "f")]
|
||||
UNSPEC_MULDUL))]
|
||||
"TARGET_VIS"
|
||||
"fmuld8ulx16\t%1, %2, %0"
|
||||
[(set_attr "type" "fpmul")
|
||||
(set_attr "fptype" "double")])
|
||||
|
||||
;; Using faligndata only makes sense after an alignaddr since the choice of
|
||||
;; bytes to take out of each operand is dependant on the results of the last
|
||||
;; alignaddr.
|
||||
(define_insn "faligndata<V64I:mode>_vis"
|
||||
[(set (match_operand:V64I 0 "register_operand" "=e")
|
||||
(unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
|
||||
(match_operand:V64I 2 "register_operand" "e")]
|
||||
UNSPEC_ALIGNDATA))]
|
||||
"TARGET_VIS"
|
||||
"faligndata\t%1, %2, %0"
|
||||
[(set_attr "type" "fga")
|
||||
(set_attr "fptype" "double")])
|
||||
|
||||
(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
|
||||
|
||||
(define_insn "alignaddr<P:mode>_vis"
|
||||
[(set (match_operand:P 0 "register_operand" "=r")
|
||||
(unspec:P [(match_operand:P 1 "reg_or_0_operand" "rJ")
|
||||
(match_operand:P 2 "reg_or_0_operand" "rJ")]
|
||||
UNSPEC_ALIGNADDR))]
|
||||
"TARGET_VIS"
|
||||
"alignaddr\t%r1, %r2, %0")
|
||||
|
||||
(define_insn "pdist_vis"
|
||||
[(set (match_operand:DI 0 "register_operand" "=e")
|
||||
(unspec:DI [(match_operand:V8QI 1 "register_operand" "e")
|
||||
(match_operand:V8QI 2 "register_operand" "e")
|
||||
(match_operand:DI 3 "register_operand" "0")]
|
||||
UNSPEC_PDIST))]
|
||||
"TARGET_VIS"
|
||||
"pdist\t%1, %2, %0"
|
||||
[(set_attr "type" "fga")
|
||||
(set_attr "fptype" "double")])
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
2004-11-22 James A. Morrison <phython@gcc.gnu.org>
|
||||
|
||||
* gcc.target/sparc/align.c, gcc.target/sparc/combined-2.c,
|
||||
gcc.target/sparc/fpack16.c, gcc.target/sparc/fpack32.c,
|
||||
gcc.target/sparc/fpackfix.c, gcc.target/fexpand.c,
|
||||
gcc.target/sparc/fpmerge.c, gcc.target/sparc/fpmul.c,
|
||||
gcc.target/sparc/pdist.c: New tests.
|
||||
|
||||
2004-11-22 Bob Wilson <bob.wilson@acm.org>
|
||||
|
||||
* gcc.dg/uninit-H.c: Define ASM for Xtensa targets.
|
||||
|
||||
29
gcc/testsuite/gcc.target/sparc/align.c
Normal file
29
gcc/testsuite/gcc.target/sparc/align.c
Normal file
@ -0,0 +1,29 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
#include <stdint.h>
|
||||
typedef int vec32 __attribute__((vector_size(8)));
|
||||
typedef short vec16 __attribute__((vector_size(8)));
|
||||
typedef char vec8 __attribute__((vector_size(8)));
|
||||
|
||||
vec16 foo1 (vec16 a, vec16 b) {
|
||||
return __builtin_vis_faligndatav4hi (a, b);
|
||||
}
|
||||
|
||||
vec32 foo2 (vec32 a, vec32 b) {
|
||||
return __builtin_vis_faligndatav2si (a, b);
|
||||
}
|
||||
|
||||
vec8 foo3 (vec8 a, vec8 b) {
|
||||
return __builtin_vis_faligndatav8qi (a, b);
|
||||
}
|
||||
|
||||
int64_t foo4 (int64_t a, int64_t b) {
|
||||
return __builtin_vis_faligndatadi (a, b);
|
||||
}
|
||||
|
||||
unsigned char * foo5 (unsigned char *data) {
|
||||
return __builtin_vis_alignaddr (data, 0);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "faligndata" 4 } } */
|
||||
/* { dg-final { scan-assembler "alignaddr.*%g0" } } */
|
||||
23
gcc/testsuite/gcc.target/sparc/combined-2.c
Normal file
23
gcc/testsuite/gcc.target/sparc/combined-2.c
Normal file
@ -0,0 +1,23 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
|
||||
typedef char pixel __attribute__((vector_size(4)));
|
||||
typedef char vec8 __attribute__((vector_size(8)));
|
||||
typedef short vec16 __attribute__((vector_size(8)));
|
||||
|
||||
vec16 foo (pixel a, pixel b) {
|
||||
vec8 c = __builtin_vis_fpmerge (a, b);
|
||||
vec16 d = { -1, -1, -1, -1 };
|
||||
vec16 e = __builtin_vis_fmul8x16 (a, d);
|
||||
|
||||
return e;
|
||||
}
|
||||
|
||||
vec16 bar (pixel a) {
|
||||
vec16 d = { 0, 0, 0, 0 };
|
||||
vec16 e = __builtin_vis_fmul8x16 (a, d); /* Mulitplication by 0 = 0. */
|
||||
|
||||
return e;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fmul8x16" } } */
|
||||
/* { dg-final { scan-assembler "fzero" } } */
|
||||
10
gcc/testsuite/gcc.target/sparc/fexpand.c
Normal file
10
gcc/testsuite/gcc.target/sparc/fexpand.c
Normal file
@ -0,0 +1,10 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
typedef short vec16 __attribute__((vector_size(8)));
|
||||
typedef char vec8 __attribute__((vector_size(4)));
|
||||
|
||||
vec16 foo (vec8 a) {
|
||||
return __builtin_vis_fexpand (a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fexpand\t%" } } */
|
||||
10
gcc/testsuite/gcc.target/sparc/fpack16.c
Normal file
10
gcc/testsuite/gcc.target/sparc/fpack16.c
Normal file
@ -0,0 +1,10 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
typedef short vec16 __attribute__((vector_size(8)));
|
||||
typedef char vec8 __attribute__((vector_size(4)));
|
||||
|
||||
vec8 foo (vec16 a) {
|
||||
return __builtin_vis_fpack16 (a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fpack16\t%" } } */
|
||||
10
gcc/testsuite/gcc.target/sparc/fpack32.c
Normal file
10
gcc/testsuite/gcc.target/sparc/fpack32.c
Normal file
@ -0,0 +1,10 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
typedef int vec32 __attribute__((vector_size(8)));
|
||||
typedef unsigned char vec8 __attribute__((vector_size(8)));
|
||||
|
||||
vec8 foo (vec32 a, vec8 b) {
|
||||
return __builtin_vis_fpack32 (a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fpack32\t%" } } */
|
||||
10
gcc/testsuite/gcc.target/sparc/fpackfix.c
Normal file
10
gcc/testsuite/gcc.target/sparc/fpackfix.c
Normal file
@ -0,0 +1,10 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
typedef int vec32 __attribute__((vector_size(8)));
|
||||
typedef short vec16 __attribute__((vector_size(4)));
|
||||
|
||||
vec16 foo (vec32 a) {
|
||||
return __builtin_vis_fpackfix (a);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fpackfix\t%" } } */
|
||||
10
gcc/testsuite/gcc.target/sparc/fpmerge.c
Normal file
10
gcc/testsuite/gcc.target/sparc/fpmerge.c
Normal file
@ -0,0 +1,10 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
typedef char pixel __attribute__((vector_size(8)));
|
||||
typedef char vec8 __attribute__((vector_size(4)));
|
||||
|
||||
pixel foo (vec8 a, vec8 b) {
|
||||
return __builtin_vis_fpmerge (a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fpmerge\t%" } } */
|
||||
43
gcc/testsuite/gcc.target/sparc/fpmul.c
Normal file
43
gcc/testsuite/gcc.target/sparc/fpmul.c
Normal file
@ -0,0 +1,43 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
typedef int vec32 __attribute__((vector_size(8)));
|
||||
typedef short vec16 __attribute__((vector_size(8)));
|
||||
typedef char pixel __attribute__((vector_size(4)));
|
||||
typedef short pixel16 __attribute__((vector_size(4)));
|
||||
typedef char vec8 __attribute__((vector_size(8)));
|
||||
|
||||
vec16 foo1 (pixel a, vec16 b) {
|
||||
return __builtin_vis_fmul8x16 (a, b);
|
||||
}
|
||||
|
||||
vec16 foo2 (pixel a, pixel16 b) {
|
||||
return __builtin_vis_fmul8x16au (a, b);
|
||||
}
|
||||
|
||||
vec16 foo3 (pixel a, pixel16 b) {
|
||||
return __builtin_vis_fmul8x16al (a, b);
|
||||
}
|
||||
|
||||
vec16 foo4 (vec8 a, vec16 b) {
|
||||
return __builtin_vis_fmul8sux16 (a, b);
|
||||
}
|
||||
|
||||
vec16 foo5 (vec8 a, vec16 b) {
|
||||
return __builtin_vis_fmul8ulx16 (a, b);
|
||||
}
|
||||
|
||||
vec32 foo6 (pixel a, pixel16 b) {
|
||||
return __builtin_vis_fmuld8sux16 (a, b);
|
||||
}
|
||||
|
||||
vec32 foo7 (pixel a, pixel16 b) {
|
||||
return __builtin_vis_fmuld8ulx16 (a, b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "fmul8x16\t%" } } */
|
||||
/* { dg-final { scan-assembler "fmul8x16au\t%" } } */
|
||||
/* { dg-final { scan-assembler "fmul8x16al\t%" } } */
|
||||
/* { dg-final { scan-assembler "fmul8sux16\t%" } } */
|
||||
/* { dg-final { scan-assembler "fmul8ulx16\t%" } } */
|
||||
/* { dg-final { scan-assembler "fmuld8sux16\t%" } } */
|
||||
/* { dg-final { scan-assembler "fmuld8ulx16\t%" } } */
|
||||
23
gcc/testsuite/gcc.target/sparc/pdist.c
Normal file
23
gcc/testsuite/gcc.target/sparc/pdist.c
Normal file
@ -0,0 +1,23 @@
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-mcpu=ultrasparc -mvis" } */
|
||||
#include <stdint.h>
|
||||
|
||||
typedef char vec8 __attribute__((vector_size(8)));
|
||||
|
||||
int64_t foo (vec8 a, vec8 b) {
|
||||
int64_t d = 0;
|
||||
d = __builtin_vis_pdist (a, b, d);
|
||||
return d;
|
||||
}
|
||||
|
||||
int64_t bar (vec8 a, vec8 b) {
|
||||
int64_t d = 0;
|
||||
return __builtin_vis_pdist (a, b, d);
|
||||
}
|
||||
|
||||
int64_t baz (vec8 a, vec8 b, int64_t d) {
|
||||
int64_t e = __builtin_vis_pdist (a, b, d);
|
||||
return e + d;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "pdist" 4 } } */
|
||||
Loading…
x
Reference in New Issue
Block a user