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Add ms2 support
Add ms2 support * config/ms1/ms1.md (UNSPEC_BLOCKAGE, UNSPEC_EI, UNSPEC_DI): New constants. (call,load,store): New insn types. (mem_access, branch_access): Adjust reservation conditions. (define_delay): Adjust condition. (decrement_and_branch_until_zero): Allow for ms2. Set branch type. (*decrement_and_rbanch_until_zero_no_clobber): Allow for ms2. (*movqi_internal,*movsi_internal,*movsf_internal): Use load,store insn type. (call_internal, call_value_internal, return_internal, return_interrupt_internal, eh_return_internal, indirect_jump, tablejump): Set call insn type. (blockage, ei, di): Use appropriate unspec const. * config/ms1/ms1.c (ms1_flag_delayed_branch): New. (ms1_get_attr_type): Adjust to give load & store types. (ms1_final_prescan_insn): Adjust for new insn types. Don't look backwards past a barrier. (ms1_override_options): Accept ms2 arch. Copy and reset delayed branch scheduling. (struct branch_info, struct label_info): New. (ms1_labels): New. (ms1_add_branches, ms1_check_delay_slot, ms1_reorg_hazard): New. (ms1_machine_reorg): New. (TARGET_MACHINE_DEPENDENT_REORG): Override. * config/ms1/crtn.asm: Add nop for ms2 JAL hazard. * config/ms1/ms1.h (processor_type): Add PROCESSOR_MS2. (ASM_SPEC, LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Add ms2. (TARGET_MS2): New. From-SVN: r106680
This commit is contained in:
Nathan Sidwell
Nathan Sidwell
parent
456b8ce5db
commit
1508cc4663
@ -1,3 +1,36 @@
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2005-11-09 Nathan Sidwell <nathan@codesourcery.com>
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Add ms2 support
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* config/ms1/ms1.md (UNSPEC_BLOCKAGE, UNSPEC_EI, UNSPEC_DI): New
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constants.
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(call,load,store): New insn types.
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(mem_access, branch_access): Adjust reservation conditions.
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(define_delay): Adjust condition.
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(decrement_and_branch_until_zero): Allow for ms2. Set branch
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type.
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(*decrement_and_rbanch_until_zero_no_clobber): Allow for ms2.
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(*movqi_internal,*movsi_internal,*movsf_internal): Use load,store
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insn type.
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(call_internal, call_value_internal, return_internal,
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return_interrupt_internal, eh_return_internal, indirect_jump,
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tablejump): Set call insn type.
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(blockage, ei, di): Use appropriate unspec const.
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* config/ms1/ms1.c (ms1_flag_delayed_branch): New.
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(ms1_get_attr_type): Adjust to give load & store types.
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(ms1_final_prescan_insn): Adjust for new insn types. Don't look
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backwards past a barrier.
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(ms1_override_options): Accept ms2 arch. Copy and reset delayed
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branch scheduling.
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(struct branch_info, struct label_info): New.
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(ms1_labels): New.
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(ms1_add_branches, ms1_check_delay_slot, ms1_reorg_hazard): New.
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(ms1_machine_reorg): New.
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(TARGET_MACHINE_DEPENDENT_REORG): Override.
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* config/ms1/crtn.asm: Add nop for ms2 JAL hazard.
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* config/ms1/ms1.h (processor_type): Add PROCESSOR_MS2.
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(ASM_SPEC, LIB_SPEC, STARTFILE_SPEC, ENDFILE_SPEC): Add ms2.
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(TARGET_MS2): New.
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2005-11-09 Per Bothner <per@bothner.com>
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Uros Bizjak <uros@kss-loka.si>
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@ -42,6 +42,7 @@
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.align 4
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ldw r14, sp, #0
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addi sp, sp, #4
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nop
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jal r0, r14
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or r0, r0, r0
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@ -50,5 +51,6 @@
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ldw r14, sp, #0
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addi sp, sp, #4
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nop
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jal r0, r14
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or r0, r0, r0
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@ -84,6 +84,8 @@ struct ms1_frame_info zero_frame_info;
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/* ms1 doesn't have unsigned compares need a library call for this. */
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struct rtx_def * ms1_ucmpsi3_libcall;
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static int ms1_flag_delayed_branch;
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static rtx
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ms1_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
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@ -125,13 +127,6 @@ ms1_asm_output_opcode (FILE *f ATTRIBUTE_UNUSED, const char *ptr)
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return ptr;
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}
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/* Return TRUE if INSN is a memory load. */
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static bool
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ms1_memory_load (rtx insn)
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{
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return ((GET_CODE (insn) == SET) && (GET_CODE (XEXP (insn,1)) == MEM));
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}
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/* Given an insn, return whether it's a memory operation or a branch
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operation, otherwise return TYPE_ARITH. */
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static enum attr_type
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@ -139,18 +134,24 @@ ms1_get_attr_type (rtx complete_insn)
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{
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rtx insn = PATTERN (complete_insn);
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if ((GET_CODE (insn) == SET)
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&& ((GET_CODE (XEXP (insn, 0)) == MEM)
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|| (GET_CODE (XEXP (insn, 1)) == MEM)))
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return TYPE_MEM;
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else if (((GET_CODE (insn) == SET) && (XEXP (insn, 0) == pc_rtx))
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|| (GET_CODE (complete_insn) == JUMP_INSN)
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|| (GET_CODE (complete_insn) == CALL_INSN))
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if (JUMP_P (complete_insn))
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return TYPE_BRANCH;
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if (CALL_P (complete_insn))
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return TYPE_BRANCH;
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else
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if (GET_CODE (insn) != SET)
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return TYPE_ARITH;
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if (SET_DEST (insn) == pc_rtx)
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return TYPE_BRANCH;
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if (GET_CODE (SET_DEST (insn)) == MEM)
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return TYPE_STORE;
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if (GET_CODE (SET_SRC (insn)) == MEM)
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return TYPE_LOAD;
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return TYPE_ARITH;
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}
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/* A helper routine for insn_dependent_p called through note_stores. */
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@ -212,35 +213,48 @@ ms1_final_prescan_insn (rtx insn,
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int noperands ATTRIBUTE_UNUSED)
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{
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rtx prev_i;
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enum attr_type prev_attr;
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ms1_nops_required = 0;
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ms1_nop_reasons = "";
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/* ms2 constraints are dealt with in reorg. */
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if (ms1_cpu == PROCESSOR_MS2)
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return;
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/* Only worry about real instructions. */
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if (! INSN_P (insn))
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return;
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/* Find the previous real instructions. */
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prev_i = PREV_INSN (insn);
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while (prev_i != NULL
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for (prev_i = PREV_INSN (insn);
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prev_i != NULL
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&& (! INSN_P (prev_i)
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|| GET_CODE (PATTERN (prev_i)) == USE
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|| GET_CODE (PATTERN (prev_i)) == CLOBBER))
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prev_i = PREV_INSN (prev_i);
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|| GET_CODE (PATTERN (prev_i)) == CLOBBER);
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prev_i = PREV_INSN (prev_i))
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{
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/* If we meet a barrier, there is no flow through here. */
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if (BARRIER_P (prev_i))
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return;
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}
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/* If there isn't one then there is nothing that we need do. */
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if (prev_i == NULL || ! INSN_P (prev_i))
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return;
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prev_attr = ms1_get_attr_type (prev_i);
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/* Delayed branch slots already taken care of by delay branch scheduling. */
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if (ms1_get_attr_type (prev_i) == TYPE_BRANCH)
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if (prev_attr == TYPE_BRANCH)
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return;
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switch (ms1_get_attr_type (insn))
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{
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case TYPE_MEM:
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case TYPE_LOAD:
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case TYPE_STORE:
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/* Avoid consecutive memory operation. */
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if (ms1_get_attr_type (prev_i) == TYPE_MEM
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if ((prev_attr == TYPE_LOAD || prev_attr == TYPE_STORE)
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&& ms1_cpu == PROCESSOR_MS1_64_001)
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{
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ms1_nops_required = 1;
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@ -252,7 +266,7 @@ ms1_final_prescan_insn (rtx insn,
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case TYPE_COMPLEX:
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/* One cycle of delay is required between load
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and the dependent arithmetic instruction. */
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if (ms1_memory_load (PATTERN (prev_i))
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if (prev_attr == TYPE_LOAD
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&& insn_true_dependent_p (prev_i, insn))
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{
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ms1_nops_required = 1;
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@ -263,7 +277,7 @@ ms1_final_prescan_insn (rtx insn,
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case TYPE_BRANCH:
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if (insn_dependent_p (prev_i, insn))
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{
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if (ms1_get_attr_type (prev_i) == TYPE_ARITH
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if (prev_attr == TYPE_ARITH
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&& ms1_cpu == PROCESSOR_MS1_64_001)
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{
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/* One cycle of delay between arith
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@ -271,7 +285,7 @@ ms1_final_prescan_insn (rtx insn,
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ms1_nops_required = 1;
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ms1_nop_reasons = "arith->branch dependency delay";
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}
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else if (ms1_memory_load (PATTERN (prev_i)))
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else if (prev_attr == TYPE_LOAD)
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{
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/* Two cycles of delay are required
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between load and dependent branch. */
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@ -790,10 +804,9 @@ ms1_override_options (void)
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else if (!strcasecmp (ms1_cpu_string, "MS1-16-002"))
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ms1_cpu = PROCESSOR_MS1_16_002;
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else if (!strcasecmp (ms1_cpu_string, "MS1-16-003"))
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{
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ms1_cpu = PROCESSOR_MS1_16_003;
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target_flags |= MASK_MUL;
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}
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ms1_cpu = PROCESSOR_MS1_16_003;
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else if (!strcasecmp (ms1_cpu_string, "MS2"))
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ms1_cpu = PROCESSOR_MS2;
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else
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error ("bad value (%s) for -march= switch", ms1_cpu_string);
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}
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@ -806,6 +819,10 @@ ms1_override_options (void)
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flag_gcse = 0;
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}
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/* We do delayed branch filling in machine dependent reorg */
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ms1_flag_delayed_branch = flag_delayed_branch;
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flag_delayed_branch = 0;
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init_machine_status = ms1_init_machine_status;
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}
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@ -1631,6 +1648,315 @@ ms1_pass_in_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type)
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|| TREE_ADDRESSABLE (type))));
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}
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/* Structures to hold branch information during reorg. */
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typedef struct branch_info
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{
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rtx insn; /* The branch insn. */
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struct branch_info *next;
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} branch_info;
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typedef struct label_info
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{
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rtx label; /* The label. */
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branch_info *branches; /* branches to this label. */
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struct label_info *next;
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} label_info;
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/* Chain of labels found in current function, used during reorg. */
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static label_info *ms1_labels;
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/* If *X is a label, add INSN to the list of branches for that
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label. */
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static int
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ms1_add_branches (rtx *x, void *insn)
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{
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if (GET_CODE (*x) == LABEL_REF)
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{
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branch_info *branch = xmalloc (sizeof (*branch));
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rtx label = XEXP (*x, 0);
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label_info *info;
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for (info = ms1_labels; info; info = info->next)
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if (info->label == label)
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break;
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if (!info)
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{
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info = xmalloc (sizeof (*info));
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info->next = ms1_labels;
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ms1_labels = info;
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info->label = label;
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info->branches = NULL;
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}
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branch->next = info->branches;
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info->branches = branch;
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branch->insn = insn;
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}
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return 0;
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}
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/* If BRANCH has a filled delay slot, check if INSN is dependent upon
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it. If so, undo the delay slot fill. Returns the next insn, if
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we patch out the branch. Returns the branch insn, if we cannot
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patch out the branch (due to anti-dependency in the delay slot).
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In that case, the caller must insert nops at the branch target. */
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static rtx
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ms1_check_delay_slot (rtx branch, rtx insn)
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{
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rtx slot;
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rtx tmp;
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rtx p;
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rtx jmp;
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gcc_assert (GET_CODE (PATTERN (branch)) == SEQUENCE);
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if (INSN_DELETED_P (branch))
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return NULL_RTX;
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slot = XVECEXP (PATTERN (branch), 0, 1);
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tmp = PATTERN (insn);
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note_stores (PATTERN (slot), insn_dependent_p_1, &tmp);
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if (tmp)
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/* Not dependent. */
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return NULL_RTX;
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/* Undo the delay slot. */
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jmp = XVECEXP (PATTERN (branch), 0, 0);
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tmp = PATTERN (jmp);
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note_stores (PATTERN (slot), insn_dependent_p_1, &tmp);
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if (!tmp)
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/* Anti dependent. */
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return branch;
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p = PREV_INSN (branch);
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NEXT_INSN (p) = slot;
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PREV_INSN (slot) = p;
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NEXT_INSN (slot) = jmp;
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PREV_INSN (jmp) = slot;
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NEXT_INSN (jmp) = branch;
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PREV_INSN (branch) = jmp;
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XVECEXP (PATTERN (branch), 0, 0) = NULL_RTX;
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XVECEXP (PATTERN (branch), 0, 1) = NULL_RTX;
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delete_insn (branch);
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return jmp;
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}
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/* Insert nops to satisfy pipeline constraints. We only deal with ms2
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constraints here. Earlier CPUs are dealt with by inserting nops with
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final_prescan (but that can lead to inferior code, and is
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impractical with ms2's JAL hazard).
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ms2 dynamic constraints
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1) a load and a following use must be separated by one insn
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2) an insn and a following dependent call must be separated by two insns
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only arith insns are placed in delay slots so #1 cannot happen with
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a load in a delay slot. #2 can happen with an arith insn in the
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delay slot. */
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static void
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ms1_reorg_hazard (void)
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{
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rtx insn, next;
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/* Find all the branches */
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for (insn = get_insns ();
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insn;
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insn = NEXT_INSN (insn))
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{
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rtx jmp;
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if (!INSN_P (insn))
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continue;
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jmp = PATTERN (insn);
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if (GET_CODE (jmp) != SEQUENCE)
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/* If it's not got a filled delay slot, then it can't
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conflict. */
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continue;
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jmp = XVECEXP (jmp, 0, 0);
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if (recog_memoized (jmp) == CODE_FOR_tablejump)
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for (jmp = XEXP (XEXP (XVECEXP (PATTERN (jmp), 0, 1), 0), 0);
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!JUMP_TABLE_DATA_P (jmp);
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jmp = NEXT_INSN (jmp))
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continue;
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for_each_rtx (&PATTERN (jmp), ms1_add_branches, insn);
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}
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/* Now scan for dependencies. */
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for (insn = get_insns ();
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insn && !INSN_P (insn);
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insn = NEXT_INSN (insn))
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continue;
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for (;
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insn;
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insn = next)
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{
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rtx jmp, tmp;
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enum attr_type attr;
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gcc_assert (INSN_P (insn) && !INSN_DELETED_P (insn));
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for (next = NEXT_INSN (insn);
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next && !INSN_P (next);
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next = NEXT_INSN (next))
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continue;
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jmp = insn;
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if (GET_CODE (PATTERN (insn)) == SEQUENCE)
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jmp = XVECEXP (PATTERN (insn), 0, 0);
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attr = recog_memoized (jmp) >= 0 ? get_attr_type (jmp) : TYPE_UNKNOWN;
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if (next && attr == TYPE_LOAD)
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{
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/* A load. See if NEXT is dependent, and if so insert a
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nop. */
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tmp = PATTERN (next);
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if (GET_CODE (tmp) == SEQUENCE)
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tmp = PATTERN (XVECEXP (tmp, 0, 0));
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note_stores (PATTERN (insn), insn_dependent_p_1, &tmp);
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if (!tmp)
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emit_insn_after (gen_nop (), insn);
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}
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if (attr == TYPE_CALL)
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{
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/* A call. Make sure we're not dependent on either of the
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previous two dynamic instructions. */
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int nops = 0;
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int count;
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rtx prev = insn;
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rtx rescan = NULL_RTX;
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for (count = 2; count && !nops;)
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{
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int type;
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prev = PREV_INSN (prev);
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if (!prev)
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{
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/* If we reach the start of the function, we must
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presume the caller set the address in the delay
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slot of the call instruction. */
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nops = count;
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break;
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}
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if (BARRIER_P (prev))
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break;
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if (LABEL_P (prev))
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{
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/* Look at branches to this label. */
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label_info *label;
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branch_info *branch;
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for (label = ms1_labels;
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label;
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label = label->next)
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if (label->label == prev)
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{
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for (branch = label->branches;
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branch;
|
||||
branch = branch->next)
|
||||
{
|
||||
tmp = ms1_check_delay_slot (branch->insn, jmp);
|
||||
|
||||
if (tmp == branch->insn)
|
||||
{
|
||||
nops = count;
|
||||
break;
|
||||
}
|
||||
|
||||
if (tmp && branch->insn == next)
|
||||
rescan = tmp;
|
||||
}
|
||||
break;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
if (!INSN_P (prev))
|
||||
continue;
|
||||
|
||||
if (GET_CODE (PATTERN (prev)) == SEQUENCE)
|
||||
{
|
||||
/* Look at the delay slot. */
|
||||
tmp = ms1_check_delay_slot (prev, jmp);
|
||||
if (tmp == prev)
|
||||
nops = count;
|
||||
break;
|
||||
}
|
||||
|
||||
type = (INSN_CODE (prev) >= 0 ? get_attr_type (prev)
|
||||
: TYPE_COMPLEX);
|
||||
if (type == TYPE_CALL || type == TYPE_BRANCH)
|
||||
break;
|
||||
|
||||
if (type == TYPE_LOAD
|
||||
|| type == TYPE_ARITH
|
||||
|| type == TYPE_COMPLEX)
|
||||
{
|
||||
tmp = PATTERN (jmp);
|
||||
note_stores (PATTERN (prev), insn_dependent_p_1, &tmp);
|
||||
if (!tmp)
|
||||
{
|
||||
nops = count;
|
||||
break;
|
||||
}
|
||||
}
|
||||
count -= INSN_CODE (prev) >= 0;
|
||||
}
|
||||
|
||||
if (rescan)
|
||||
for (next = NEXT_INSN (rescan);
|
||||
next && !INSN_P (next);
|
||||
next = NEXT_INSN (next))
|
||||
continue;
|
||||
while (nops--)
|
||||
emit_insn_before (gen_nop (), insn);
|
||||
}
|
||||
}
|
||||
|
||||
/* Free the data structures. */
|
||||
while (ms1_labels)
|
||||
{
|
||||
label_info *label = ms1_labels;
|
||||
branch_info *branch, *next;
|
||||
|
||||
ms1_labels = label->next;
|
||||
for (branch = label->branches; branch; branch = next)
|
||||
{
|
||||
next = branch->next;
|
||||
free (branch);
|
||||
}
|
||||
free (label);
|
||||
}
|
||||
}
|
||||
|
||||
/* Fixup the looping instructions, do delayed branch scheduling, fixup
|
||||
scheduling hazards. */
|
||||
|
||||
static void
|
||||
ms1_machine_reorg (void)
|
||||
{
|
||||
if (ms1_flag_delayed_branch)
|
||||
dbr_schedule (get_insns (), dump_file);
|
||||
|
||||
if (ms1_cpu == PROCESSOR_MS2)
|
||||
ms1_reorg_hazard ();
|
||||
}
|
||||
|
||||
/* Initialize the GCC target structure. */
|
||||
const struct attribute_spec ms1_attribute_table[];
|
||||
|
||||
@ -1646,6 +1972,8 @@ const struct attribute_spec ms1_attribute_table[];
|
||||
#define TARGET_MUST_PASS_IN_STACK ms1_pass_in_stack
|
||||
#undef TARGET_ARG_PARTIAL_BYTES
|
||||
#define TARGET_ARG_PARTIAL_BYTES ms1_arg_partial_bytes
|
||||
#undef TARGET_MACHINE_DEPENDENT_REORG
|
||||
#define TARGET_MACHINE_DEPENDENT_REORG ms1_machine_reorg
|
||||
|
||||
struct gcc_target targetm = TARGET_INITIALIZER;
|
||||
|
||||
|
||||
@ -25,7 +25,8 @@ enum processor_type
|
||||
{
|
||||
PROCESSOR_MS1_64_001,
|
||||
PROCESSOR_MS1_16_002,
|
||||
PROCESSOR_MS1_16_003
|
||||
PROCESSOR_MS1_16_003,
|
||||
PROCESSOR_MS2
|
||||
};
|
||||
|
||||
enum epilogue_type
|
||||
@ -40,7 +41,7 @@ extern enum processor_type ms1_cpu;
|
||||
/* A C string constant that tells the GCC driver program options to pass to
|
||||
the assembler. */
|
||||
#undef ASM_SPEC
|
||||
#define ASM_SPEC "%{march=ms1-16-002: -march=ms1-16-002} %{march=ms1-16-003: -march=ms1-16-003} %{!march=*: -march=ms1-16-002}"
|
||||
#define ASM_SPEC "%{march=ms1-16-002: -march=ms1-16-002} %{march=ms1-16-003: -march=ms1-16-003} %{march=ms2: -march=ms2} %{!march=*: -march=ms1-16-002}"
|
||||
|
||||
/* A string to pass to at the end of the command given to the linker. */
|
||||
#undef LIB_SPEC
|
||||
@ -51,7 +52,9 @@ march=MS1-64-001:-T 64-001.ld%s; \
|
||||
march=ms1-16-002:-T 16-002.ld%s; \
|
||||
march=MS1-16-002:-T 16-002.ld%s; \
|
||||
march=ms1-16-003:-T 16-003.ld%s; \
|
||||
march=MS1-16-003:-T 16-003.ld%s}"
|
||||
march=MS1-16-003:-T 16-003.ld%s; \
|
||||
march=ms2:-T ms2.ld%s; \
|
||||
march=MS2:-T ms2.ld%s}"
|
||||
|
||||
/* A string to pass at the very beginning of the command given to the
|
||||
linker. */
|
||||
@ -62,7 +65,9 @@ march=MS1-64-001:%{!mno-crt0:crt0-64-001.o%s} startup-64-001.o%s; \
|
||||
march=ms1-16-002:%{!mno-crt0:crt0-16-002.o%s} startup-16-002.o%s; \
|
||||
march=MS1-16-002:%{!mno-crt0:crt0-16-002.o%s} startup-16-002.o%s; \
|
||||
march=ms1-16-003:%{!mno-crt0:crt0-16-003.o%s} startup-16-003.o%s; \
|
||||
march=MS1-16-003:%{!mno-crt0:crt0-16-003.o%s} startup-16-003.o%s} \
|
||||
march=MS1-16-003:%{!mno-crt0:crt0-16-003.o%s} startup-16-003.o%s; \
|
||||
march=ms2:%{!mno-crt0:crt0-ms2.o%s} startup-ms2.o%s; \
|
||||
march=MS2:%{!mno-crt0:crt0-ms2.o%s} startup-ms2.o%s} \
|
||||
crti.o%s crtbegin.o%s"
|
||||
|
||||
/* A string to pass at the end of the command given to the linker. */
|
||||
@ -73,7 +78,9 @@ march=MS1-64-001:exit-64-001.o%s; \
|
||||
march=ms1-16-002:exit-16-002.o%s; \
|
||||
march=MS1-16-002:exit-16-002.o%s; \
|
||||
march=ms1-16-003:exit-16-003.o%s; \
|
||||
march=MS1-16-003:exit-16-003.o%s} \
|
||||
march=MS1-16-003:exit-16-003.o%s; \
|
||||
march=ms2:exit-ms2.o%s; \
|
||||
march=MS2:exit-ms2.o%s} \
|
||||
crtend.o%s crtn.o%s"
|
||||
|
||||
/* Run-time target specifications. */
|
||||
@ -89,6 +96,7 @@ march=MS1-16-003:exit-16-003.o%s} \
|
||||
#define TARGET_MS1_64_001 (ms1_cpu == PROCESSOR_MS1_64_001)
|
||||
#define TARGET_MS1_16_002 (ms1_cpu == PROCESSOR_MS1_16_002)
|
||||
#define TARGET_MS1_16_003 (ms1_cpu == PROCESSOR_MS1_16_003)
|
||||
#define TARGET_MS2 (ms1_cpu == PROCESSOR_MS2)
|
||||
|
||||
#define TARGET_VERSION fprintf (stderr, " (ms1)");
|
||||
|
||||
|
||||
@ -19,8 +19,16 @@
|
||||
;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
|
||||
;; 02110-1301, USA.
|
||||
|
||||
;; UNSPECs
|
||||
(define_constants
|
||||
[
|
||||
(UNSPEC_BLOCKAGE 0)
|
||||
(UNSPEC_EI 1)
|
||||
(UNSPEC_DI 2)
|
||||
])
|
||||
|
||||
;; Attributes
|
||||
(define_attr "type" "branch,mem,io,arith,complex,unknown"
|
||||
(define_attr "type" "branch,call,load,store,io,arith,complex,unknown"
|
||||
(const_string "unknown") )
|
||||
|
||||
;; If the attribute takes numeric values, no `enum' type will be defined and
|
||||
@ -36,7 +44,7 @@
|
||||
(define_cpu_unit "branch_unit" "other")
|
||||
|
||||
(define_insn_reservation "mem_access" 2
|
||||
(eq_attr "type" "mem")
|
||||
(ior (eq_attr "type" "load") (eq_attr "type" "store"))
|
||||
"decode_unit+memory_unit*2")
|
||||
|
||||
(define_insn_reservation "io_access" 2
|
||||
@ -44,7 +52,8 @@
|
||||
"decode_unit+memory_unit*2")
|
||||
|
||||
(define_insn_reservation "branch_access" 2
|
||||
(eq_attr "type" "branch")
|
||||
(ior (eq_attr "type" "branch")
|
||||
(eq_attr "type" "call"))
|
||||
"decode_unit+branch_unit*2")
|
||||
|
||||
(define_insn_reservation "arith_access" 1
|
||||
@ -64,7 +73,8 @@
|
||||
;; the destination of the branch. Thus, only type that will be acceptable
|
||||
;; (safe) is the arith type.
|
||||
|
||||
(define_delay (eq_attr "type" "branch")
|
||||
(define_delay (ior (eq_attr "type" "branch")
|
||||
(eq_attr "type" "call"))
|
||||
[(eq_attr "type" "arith") (nil) (nil)])
|
||||
|
||||
|
||||
@ -79,7 +89,7 @@
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))
|
||||
(clobber (match_scratch:SI 2 "=X,r"))]
|
||||
"TARGET_MS1_16_003"
|
||||
"TARGET_MS1_16_003 || TARGET_MS2"
|
||||
"@
|
||||
dbnz\t%0, %l1%#
|
||||
#"
|
||||
@ -98,9 +108,10 @@
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))]
|
||||
"TARGET_MS1_16_003"
|
||||
"TARGET_MS1_16_003 || TARGET_MS2"
|
||||
"dbnz\t%0, %l1%#"
|
||||
[(set_attr "length" "4")]
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")]
|
||||
)
|
||||
|
||||
;; Split the above to handle the case where operand 0 is in memory
|
||||
@ -116,7 +127,7 @@
|
||||
(plus:SI (match_dup 0)
|
||||
(const_int -1)))
|
||||
(clobber (match_scratch:SI 2 ""))]
|
||||
"TARGET_MS1_16_003"
|
||||
"TARGET_MS1_16_003 || TARGET_MS2"
|
||||
[(set (match_dup 2) (match_dup 0))
|
||||
(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
|
||||
(set (match_dup 0) (match_dup 2))
|
||||
@ -143,7 +154,7 @@
|
||||
(label_ref (match_operand 2 "" ""))
|
||||
(pc)))
|
||||
]
|
||||
"TARGET_MS1_16_003"
|
||||
"TARGET_MS1_16_003 || TARGET_MS2"
|
||||
[(parallel [(set (pc)
|
||||
(if_then_else
|
||||
(ne (match_dup 0) (const_int 0))
|
||||
@ -308,7 +319,7 @@
|
||||
stb %1, %0
|
||||
addi %0, r0, %1"
|
||||
[(set_attr "length" "4,4,4,4")
|
||||
(set_attr "type" "arith,mem,mem,arith")])
|
||||
(set_attr "type" "arith,load,store,arith")])
|
||||
|
||||
(define_insn "*movqi_internal_nobyte"
|
||||
[(set (match_operand:QI 0 "register_operand" "=r,r")
|
||||
@ -566,7 +577,7 @@
|
||||
nori %0, r0, %N1
|
||||
ldui %0, %H1\;addui %0, %0, %L1"
|
||||
[(set_attr "length" "4,4,4,4,4,4,4,8")
|
||||
(set_attr "type" "arith,mem,mem,arith,arith,arith,arith,complex")]
|
||||
(set_attr "type" "arith,load,store,arith,arith,arith,arith,complex")]
|
||||
)
|
||||
|
||||
;; Floating Point Moves
|
||||
@ -641,7 +652,7 @@
|
||||
ldw %0, %1
|
||||
stw %1, %0"
|
||||
[(set_attr "length" "4,4,4")
|
||||
(set_attr "type" "arith,mem,mem")]
|
||||
(set_attr "type" "arith,load,store")]
|
||||
)
|
||||
|
||||
(define_expand "movdf"
|
||||
@ -1269,7 +1280,7 @@
|
||||
""
|
||||
"jal r14, %0%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
(define_expand "call_value"
|
||||
[(parallel [(set (match_operand 0 "register_operand" "")
|
||||
@ -1292,7 +1303,7 @@
|
||||
""
|
||||
"jal r14, %1%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
;; Subroutine return
|
||||
(define_insn "return_internal"
|
||||
@ -1302,7 +1313,7 @@
|
||||
""
|
||||
"jal r0, r14%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
;; Interrupt return
|
||||
(define_insn "return_interrupt_internal"
|
||||
@ -1312,7 +1323,7 @@
|
||||
""
|
||||
"reti r15%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
;; Subroutine return
|
||||
(define_insn "eh_return_internal"
|
||||
@ -1324,7 +1335,7 @@
|
||||
""
|
||||
"jal r0, r11%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
|
||||
;; Normal unconditional jump
|
||||
@ -1341,7 +1352,7 @@
|
||||
""
|
||||
"jal r0,%0%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
(define_insn "tablejump"
|
||||
[(set (pc) (match_operand:SI 0 "register_operand" "r"))
|
||||
@ -1349,7 +1360,7 @@
|
||||
""
|
||||
"jal r0, %0%#"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "type" "branch")])
|
||||
(set_attr "type" "call")])
|
||||
|
||||
|
||||
(define_expand "prologue"
|
||||
@ -1412,7 +1423,7 @@
|
||||
;; Pseudo instruction that prevents the scheduler from moving code above this
|
||||
;; point.
|
||||
(define_insn "blockage"
|
||||
[(unspec_volatile [(const_int 0)] 0)]
|
||||
[(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
|
||||
""
|
||||
""
|
||||
[(set_attr "length" "0")])
|
||||
@ -1442,14 +1453,14 @@
|
||||
|
||||
;; Enable interrupts template
|
||||
(define_insn "ei"
|
||||
[(unspec_volatile [(const_int 0)] 1)]
|
||||
[(unspec_volatile [(const_int 0)] UNSPEC_EI)]
|
||||
""
|
||||
"ei"
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
;; Enable interrupts template
|
||||
(define_insn "di"
|
||||
[(unspec_volatile [(const_int 0)] 2)]
|
||||
[(unspec_volatile [(const_int 0)] UNSPEC_DI)]
|
||||
""
|
||||
"di"
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user