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invoke.texi (MIPS Options): Document -mfused-madd.
* doc/invoke.texi (MIPS Options): Document -mfused-madd. * config/mips/mips.h (MASK_NO_FUSED_MADD): New. (TARGET_FUSED_MADD): New. (TARGET_SWITCHES): Add -mfused-madd, -mno-fused-madd. * config/mips/mips.md: Add TARGET_FUSED_MADD as condition to the multiply-add instructions. From-SVN: r45041
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Geoffrey Keating
Geoffrey Keating
parent
915a17f667
commit
13fac94a68
@ -1,3 +1,12 @@
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2001-08-19 Geoffrey Keating <geoffk@redhat.com>
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* doc/invoke.texi (MIPS Options): Document -mfused-madd.
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* config/mips/mips.h (MASK_NO_FUSED_MADD): New.
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(TARGET_FUSED_MADD): New.
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(TARGET_SWITCHES): Add -mfused-madd, -mno-fused-madd.
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* config/mips/mips.md: Add TARGET_FUSED_MADD as condition to
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the multiply-add instructions.
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2001-08-19 Richard Henderson <rth@redhat.com>
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* dwarf2asm.c (dw2_output_indirect_constant_1): The symbol ref
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@ -223,6 +223,8 @@ extern void sbss_section PARAMS ((void));
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#define MASK_UNINIT_CONST_IN_RODATA \
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0x00800000 /* Store uninitialized
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consts in rodata */
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#define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
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multiply-add operations. */
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/* Debug switches, not documented */
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#define MASK_DEBUG 0 /* unused */
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@ -311,6 +313,8 @@ extern void sbss_section PARAMS ((void));
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#define TARGET_MAD (target_flags & MASK_MAD)
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#define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
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#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
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#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
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@ -439,6 +443,10 @@ extern void sbss_section PARAMS ((void));
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N_("Use multiply accumulate")}, \
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{"no-mad", -MASK_MAD, \
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N_("Don't use multiply accumulate")}, \
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{"no-fused-madd", MASK_NO_FUSED_MADD, \
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N_("Don't generate fused multiply/add instructions")}, \
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{"fused-madd", -MASK_NO_FUSED_MADD, \
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N_("Generate fused multiply/add instructions")}, \
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{"fix4300", MASK_4300_MUL_FIX, \
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N_("Work around early 4300 hardware bug")}, \
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{"no-fix4300", -MASK_4300_MUL_FIX, \
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@ -2138,7 +2138,7 @@
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(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
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"madd.d\\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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@ -2148,7 +2148,7 @@
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(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f"))
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(match_operand:SF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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"madd.s\\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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@ -2158,7 +2158,7 @@
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(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
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"msub.d\\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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@ -2169,7 +2169,7 @@
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(match_operand:SF 2 "register_operand" "f"))
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(match_operand:SF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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"msub.s\\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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@ -2179,7 +2179,7 @@
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(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f"))))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
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"nmadd.d\\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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@ -2189,7 +2189,7 @@
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(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f"))
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(match_operand:SF 3 "register_operand" "f"))))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT"
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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"nmadd.s\\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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@ -2199,7 +2199,7 @@
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(minus:DF (match_operand:DF 1 "register_operand" "f")
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(mult:DF (match_operand:DF 2 "register_operand" "f")
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(match_operand:DF 3 "register_operand" "f"))))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
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"nmsub.d\\t%0,%1,%2,%3"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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@ -2209,7 +2209,7 @@
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(minus:SF (match_operand:SF 1 "register_operand" "f")
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(mult:SF (match_operand:SF 2 "register_operand" "f")
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(match_operand:SF 3 "register_operand" "f"))))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT"
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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"nmsub.s\\t%0,%1,%2,%3"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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@ -450,7 +450,8 @@ in the following sections.
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@gccoptlist{
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-mabicalls -march=@var{cpu-type} -mtune=@var{cpu=type} @gol
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-mcpu=@var{cpu-type} -membedded-data -muninit-const-in-rodata @gol
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-membedded-pic -mfp32 -mfp64 -mgas -mgp32 -mgp64 @gol
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-membedded-pic -mfp32 -mfp64 -mfused-madd -mno-fused-madd @gol
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-mgas -mgp32 -mgp64 @gol
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-mgpopt -mhalf-pic -mhard-float -mint64 -mips1 @gol
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-mips2 -mips3 -mips4 -mlong64 -mlong32 -mlong-calls -mmemcpy @gol
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-mmips-as -mmips-tfile -mno-abicalls @gol
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@ -7080,6 +7081,18 @@ the default.
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Assume that 32 64-bit floating point registers are available. This is
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the default when the @option{-mips3} option is used.
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@item -mfused-madd
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@itemx -mno-fused-madd
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@opindex mfused-madd
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@opindex mno-fused-madd
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Generate code that uses (does not use) the floating point multiply and
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accumulate instructions, when they are available. These instructions
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are generated by default if they are available, but this may be
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undesirable if the extra precision causes problems or on certain chips
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in the mode where denormals are rounded to zero where denormals
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generated by multiply and accumulate instructions cause exceptions
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anyway.
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@item -mgp32
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@opindex mgp32
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Assume that 32 32-bit general purpose registers are available. This is
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