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RISC-V Port: gcc/testsuite

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gcc/testsuite/ChangeLog:

2017-02-06  Kito Cheng  <kito.cheng@gmail.com>

        * lib/target-supports.exp: Define the RISC-V target.
        * g++.dg/cpp0x/constexpr-rom.C: Skip on RISC-V
        * gcc.dg/builtin-apply2.c: Likewise.
        * gcc.dg/ifcvt-4.c: Likewise.
        * gcc.dg/loop-8.c: Likewise.
        * gcc.dg/sibcall-10.c: Likewise.
        * gcc.dg/sibcall-9.c: Likewise.
        * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
        * gcc.dg/tree-ssa/20040204-1.c: Likewise.
        * gcc.dg/tree-ssa/ssa-dom-cse-2.c: Likewise.
        * gcc.dg/tree-ssa/ssa-fre-3.c: Likewise.
        * gcc.c-torture/execute/20101011-1.c: Define DO_TEST on RISC-V.
        * gcc.dg/20020312-2.c: Don't define PIC_REG on RISC-V.
        * gcc.dg/stack-usage-1.c: Define SIZE on RISC-V.

From-SVN: r245228
This commit is contained in:
Kito Cheng 2017-02-06 21:39:03 +00:00 committed by Palmer Dabbelt
parent b906c007fe
commit 122e7b4f9d
15 changed files with 37 additions and 7 deletions
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17
gcc/testsuite/ChangeLog
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@ -1,3 +1,20 @@
2017-02-06 Kito Cheng <kito.cheng@gmail.com>
* lib/target-supports.exp: Define the RISC-V target.
* g++.dg/cpp0x/constexpr-rom.C: Skip on RISC-V
* gcc.dg/builtin-apply2.c: Likewise.
* gcc.dg/ifcvt-4.c: Likewise.
* gcc.dg/loop-8.c: Likewise.
* gcc.dg/sibcall-10.c: Likewise.
* gcc.dg/sibcall-9.c: Likewise.
* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
* gcc.dg/tree-ssa/20040204-1.c: Likewise.
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-3.c: Likewise.
* gcc.c-torture/execute/20101011-1.c: Define DO_TEST on RISC-V.
* gcc.dg/20020312-2.c: Don't define PIC_REG on RISC-V.
* gcc.dg/stack-usage-1.c: Define SIZE on RISC-V.
2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/66144

2
gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
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@ -2,7 +2,7 @@
// { dg-do compile { target c++11 } }
// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
// { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! mips*-*-* } } } } }
// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } }
struct Data
{

3
gcc/testsuite/gcc.c-torture/execute/20101011-1.c
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@ -6,6 +6,9 @@
#elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || defined (__POWERPC__) || defined (__ppc)
/* On PPC division by zero does not trap. */
# define DO_TEST 0
#elif defined (__riscv)
/* On RISC-V division by zero does not trap. */
# define DO_TEST 0
#elif defined (__SPU__)
/* On SPU division by zero does not trap. */
# define DO_TEST 0

2
gcc/testsuite/gcc.dg/20020312-2.c
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@ -67,6 +67,8 @@ extern void abort (void);
# else
# define PIC_REG "30"
# endif
#elif defined(__riscv)
/* No pic register. */
#elif defined(__RX__)
/* No pic register. */
#elif defined(__s390__)

1
gcc/testsuite/gcc.dg/builtin-apply2.c
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@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target untyped_assembly } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-*" } { "*" } { "" } } */
/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-*" } { "*" } { "" } } */
/* { dg-skip-if "Variadic funcs use Base AAPCS. Normal funcs use VFP variant." { arm*-*-* && arm_hf_eabi } { "*" } { "" } } */
/* PR target/12503 */

2
gcc/testsuite/gcc.dg/ifcvt-4.c
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@ -1,6 +1,6 @@
/* { dg-options "-fdump-rtl-ce1 -O2 --param max-rtl-if-conversion-insns=3 --param max-rtl-if-conversion-unpredictable-cost=100" } */
/* { dg-additional-options "-misel" { target { powerpc*-*-* } } } */
/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" { "arm*-*-* hppa*64*-*-* visium-*-*" } } */
/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" { "arm*-*-* hppa*64*-*-* visium-*-*" riscv*-*-* } } */
typedef int word __attribute__((mode(word)));

2
gcc/testsuite/gcc.dg/loop-8.c
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@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */
/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-*" } { "*" } { "" } } */
/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-*" } { "*" } { "" } } */
void
f (int *a, int *b)

2
gcc/testsuite/gcc.dg/sibcall-10.c
View File

@ -8,6 +8,8 @@
/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
/* -msave-restore disables sibcall patterns. */
/* { dg-skip-if "" { riscv*-*-* } { "-msave-restore" } { "" } } */
/* { dg-options "-O2 -foptimize-sibling-calls" } */
/* The option -foptimize-sibling-calls is the default, but serves as

2
gcc/testsuite/gcc.dg/sibcall-9.c
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@ -8,6 +8,8 @@
/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
/* -msave-restore disables sibcall patterns. */
/* { dg-skip-if "" { riscv*-*-* } { "-msave-restore" } { "" } } */
/* { dg-options "-O2 -foptimize-sibling-calls" } */
/* The option -foptimize-sibling-calls is the default, but serves as

2
gcc/testsuite/gcc.dg/stack-usage-1.c
View File

@ -63,6 +63,8 @@
# else
# define SIZE 240
# endif
#elif defined (__riscv)
# define SIZE 240
#elif defined (__AVR__)
#if defined (__AVR_3_BYTE_PC__ )
# define SIZE 251 /* 256 - 2 bytes for Y - 3 bytes for return address */

2
gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
View File

@ -9,7 +9,7 @@
/* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant.
avr: Variadic funcs don't pass arguments in registers, while normal funcs
do. */
/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* } } "*" "" } */
/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* } || { riscv*-*-* } } "*" "" } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } "*" "" } */
/* { dg-require-effective-target untyped_assembly } */

2
gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
View File

@ -33,4 +33,4 @@ void test55 (int x, int y)
that the && should be emitted (based on BRANCH_COST). Fix this
by teaching dom to look through && and register all components
as true. */
/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-* sparc*-*-* spu-*-* visium-*-* x86_64-*-*" } } } } */
/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-* i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-* sparc*-*-* spu-*-* visium-*-* x86_64-*-* riscv*-*-*" } } } } */

2
gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c
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@ -25,4 +25,4 @@ foo ()
but the loop reads only one element at a time, and DOM cannot resolve these.
The same happens on powerpc depending on the SIMD support available. */
/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* powerpc64*-*-* } || { sparc*-*-* && lp64 } } } } } */
/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-* hppa*64*-*-* powerpc64*-*-* } || { { sparc*-*-* && lp64 } || { riscv*-*-* && lp64 } } } } } } */

2
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
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@ -18,4 +18,4 @@ foo (int a, int b)
return aa + bb;
}
/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" "fre1" } } */
/* { dg-final { scan-tree-dump "Replaced \\\(int\\\) aa_.*with a_" "fre1" { xfail { riscv*-*-* && lp64 } } } } */

1
gcc/testsuite/lib/target-supports.exp
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@ -7971,6 +7971,7 @@ proc check_effective_target_logical_op_short_circuit {} {
|| [istarget s390*-*-*]
|| [istarget powerpc*-*-*]
|| [istarget nios2*-*-*]
|| [istarget riscv*-*-*]
|| [istarget visium-*-*]
|| [check_effective_target_arm_cortex_m] } {
return 1