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rs6000: Remove TARGET_FPRS

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Since rs6000 no longer supports SPE, TARGET_FPRS now always is true.

This makes TARGET_{SF,DF}_SPE always false.  Many patterns in spe.md
can now be deleted; which makes it possible to merge e.g. negdd2 with
*negdd2_fpr.

Finally, e500.h is deleted (it isn't used).


	* config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
	* config/rs6000/dfp.md: Ditto.
	(negdd2, *negdd2_fpr): Merge.
	(absdd2, *absdd2_fpr): Merge.
	(negtd2, *negtd2_fpr): Merge.
	(abstd2, *abstd2_fpr): Merge.
	* config/rs6000/e500.h: Delete file.
	* config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
	TARGET_FPRS by 1 and simplify.
	* config/rs6000/rs6000-c.c: Ditto.
	* config/rs6000/rs6000.c: Ditto.  Also replace TARGET_SF_SPE and
	TARGET_DF_SPE by 0.
	* config/rs6000/rs6000.h: Ditto.  Delete TARGET_SF_SPE and
	TARGET_DF_SPE.
	* config/rs6000/rs6000.md: Ditto.
	(floatdidf2, *floatdidf2_fpr): Merge.
	(move_from_CR_gt_bit): Delete.
	* config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
	(E500_CR_IOR_COMPARE): Delete.
	(All patterns that require !TARGET_FPRS): Delete.
	* config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.

From-SVN: r248974
This commit is contained in:
Segher Boessenkool 2017-06-07 16:55:54 +02:00 committed by Segher Boessenkool
parent a6d31e8499
commit 11d8d07e31
10 changed files with 195 additions and 686 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
gcc/ChangeLog
View File

@ -1,3 +1,27 @@
2017-06-07 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/darwin.md: Replace TARGET_FPRS by 1 and simplify.
* config/rs6000/dfp.md: Ditto.
(negdd2, *negdd2_fpr): Merge.
(absdd2, *absdd2_fpr): Merge.
(negtd2, *negtd2_fpr): Merge.
(abstd2, *abstd2_fpr): Merge.
* config/rs6000/e500.h: Delete file.
* config/rs6000/predicates.md (rs6000_cbranch_operator): Replace
TARGET_FPRS by 1 and simplify.
* config/rs6000/rs6000-c.c: Ditto.
* config/rs6000/rs6000.c: Ditto. Also replace TARGET_SF_SPE and
TARGET_DF_SPE by 0.
* config/rs6000/rs6000.h: Ditto. Delete TARGET_SF_SPE and
TARGET_DF_SPE.
* config/rs6000/rs6000.md: Ditto.
(floatdidf2, *floatdidf2_fpr): Merge.
(move_from_CR_gt_bit): Delete.
* config/rs6000/spe.md: Replace TARGET_FPRS by 1 and simplify.
(E500_CR_IOR_COMPARE): Delete.
(All patterns that require !TARGET_FPRS): Delete.
* config/rs6000/vsx.md: Replace TARGET_FPRS by 1 and simplify.
2017-06-07 Bin Cheng <bin.cheng@arm.com>
* passes.def (pass_iv_canon): Move before pass_loop_distribution.

16
gcc/config/rs6000/darwin.md
View File

@ -30,7 +30,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && !TARGET_64BIT"
"*
{
switch (which_alternative)
@ -61,7 +61,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
(mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"*
{
switch (which_alternative)
@ -81,7 +81,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@ -90,7 +90,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))
(match_operand:DF 0 "gpc_reg_operand" "f"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@ -99,7 +99,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
@ -110,7 +110,7 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
(mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
lwz %0,lo16(%2)(%1)"
@ -121,7 +121,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"
@ -132,7 +132,7 @@ You should have received a copy of the GNU General Public License
[(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
(match_operand 2 "" "")))
(match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
stw %0,lo16(%2)(%1)"

48
gcc/config/rs6000/dfp.md
View File

@ -35,7 +35,7 @@
UNSPEC_MOVSD_STORE))]
"(gpc_reg_operand (operands[0], DDmode)
|| gpc_reg_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_HARD_FLOAT"
"stfd%U0%X0 %1,%0"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
@ -46,7 +46,7 @@
UNSPEC_MOVSD_LOAD))]
"(gpc_reg_operand (operands[0], SDmode)
|| gpc_reg_operand (operands[1], DDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_HARD_FLOAT"
"lfd%U1%X1 %0,%1"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
@ -78,65 +78,41 @@
"drsp %0,%1"
[(set_attr "type" "dfp")])
(define_expand "negdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*negdd2_fpr"
(define_insn "negdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"fneg %0,%1"
[(set_attr "type" "fpsimple")])
(define_expand "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*absdd2_fpr"
(define_insn "absdd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"fabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*nabsdd2_fpr"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"fnabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_expand "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*negtd2_fpr"
(define_insn "negtd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"@
fneg %0,%1
fneg %0,%1\;fmr %L0,%L1"
[(set_attr "type" "fpsimple")
(set_attr "length" "4,8")])
(define_expand "abstd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"")
(define_insn "*abstd2_fpr"
(define_insn "abstd2"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"@
fabs %0,%1
fabs %0,%1\;fmr %L0,%L1"
@ -146,7 +122,7 @@
(define_insn "*nabstd2_fpr"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"@
fnabs %0,%1
fnabs %0,%1\;fmr %L0,%L1"

10
gcc/config/rs6000/predicates.md
View File

@ -1240,16 +1240,8 @@
1"))))
;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
;; If we're assuming that FP operations cannot generate user-visible traps,
;; then on e500 we can use the ordered-signaling instructions to implement
;; the unordered-quiet FP comparison predicates modulo a reversal.
(define_predicate "rs6000_cbranch_operator"
(if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
(if_then_else (match_test "flag_trapping_math")
(match_operand 0 "ordered_comparison_operator")
(ior (match_operand 0 "ordered_comparison_operator")
(match_code ("unlt,unle,ungt,unge"))))
(match_operand 0 "comparison_operator")))
(match_operand 0 "comparison_operator"))
;; Return 1 if OP is an unsigned comparison operator.
(define_predicate "unsigned_comparison_operator"

14
gcc/config/rs6000/rs6000-c.c
View File

@ -488,10 +488,10 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
the following conditions:
1. The operating system does not support saving of AltiVec
registers (OS_MISSING_ALTIVEC).
2. If any of the options TARGET_HARD_FLOAT, TARGET_FPRS,
TARGET_SINGLE_FLOAT, or TARGET_DOUBLE_FLOAT are turned off.
Hereafter, the OPTION_MASK_VSX flag is considered to have been
turned off explicitly.
2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
3. If TARGET_PAIRED_FLOAT was enabled. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
@ -674,8 +674,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
}
}
if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT))
if (!TARGET_HARD_FLOAT
|| (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
builtin_define ("_SOFT_DOUBLE");
/* Used by lwarx/stwcx. errata work-around. */
if (rs6000_cpu == PROCESSOR_PPC405)
@ -775,7 +775,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
/* Let the compiled code know if 'f' class registers will not be available. */
if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
if (TARGET_SOFT_FLOAT)
builtin_define ("__NO_FPRS__");
/* Whether aggregates passed by value are aligned to a 16 byte boundary

297
gcc/config/rs6000/rs6000.c
View File

@ -2853,9 +2853,6 @@ rs6000_debug_reg_global (void)
if (rs6000_float_gprs)
fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
fprintf (stderr, DEBUG_FMT_S, "fprs",
(TARGET_FPRS ? "true" : "false"));
fprintf (stderr, DEBUG_FMT_S, "single_float",
(TARGET_SINGLE_FLOAT ? "true" : "false"));
@ -3295,10 +3292,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wJ - VSX register if QImode/HImode are allowed in VSX registers.
wK - Altivec register if QImode/HImode are allowed in VSX registers. */
if (TARGET_HARD_FLOAT && TARGET_FPRS)
if (TARGET_HARD_FLOAT)
rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
if (TARGET_VSX)
@ -3663,8 +3660,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (addis_insns[i].pmode != cur_pmode)
continue;
if (rtype == RELOAD_REG_FPR
&& (!TARGET_HARD_FLOAT || !TARGET_FPRS))
if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
continue;
reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
@ -3689,7 +3685,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[HImode].fused_toc = true;
reg_addr[SImode].fused_toc = true;
reg_addr[DImode].fused_toc = true;
if (TARGET_HARD_FLOAT && TARGET_FPRS)
if (TARGET_HARD_FLOAT)
{
if (TARGET_SINGLE_FLOAT)
reg_addr[SFmode].fused_toc = true;
@ -4355,8 +4351,7 @@ rs6000_option_override_internal (bool global_init_p)
if (TARGET_VSX)
{
const char *msg = NULL;
if (!TARGET_HARD_FLOAT || !TARGET_FPRS
|| !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx requires hardware floating point");
@ -5550,8 +5545,7 @@ rs6000_option_override_internal (bool global_init_p)
/* Set up single/double float flags.
If TARGET_HARD_FLOAT is set, but neither single or double is set,
then set both flags. */
if (TARGET_HARD_FLOAT && TARGET_FPRS
&& rs6000_single_float == 0 && rs6000_double_float == 0)
if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
rs6000_single_float = rs6000_double_float = 1;
/* If not explicitly specified via option, decide whether to generate indexed
@ -9104,7 +9098,7 @@ legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
return false;
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
&& !(/* ??? Assume floating point reg based on mode? */
TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (mode == DFmode || mode == DDmode)))
return false;
@ -9215,7 +9209,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (/* ??? Assume floating point reg based on mode? */
(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
&& (mode == DFmode || mode == DDmode)))
&& !avoiding_indexed_address_p (mode))
{
@ -9271,7 +9265,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (/* ??? Assume floating point reg based on mode? */
(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
&& (mode == DFmode || mode == DDmode))))
{
rtx reg = gen_reg_rtx (Pmode);
@ -10063,7 +10057,7 @@ rs6000_legitimize_reload_address (rtx x, machine_mode mode,
&& mode != PTImode
&& (mode != DImode || TARGET_POWERPC64)
&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
|| (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
|| (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
{
#if TARGET_MACHO
if (flag_pic)
@ -10244,7 +10238,7 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
return 1;
if (!FLOAT128_2REG_P (mode)
&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
&& ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| TARGET_POWERPC64
|| (mode != DFmode && mode != DDmode)
|| (TARGET_E500_DOUBLE && mode != DDmode))
@ -10476,7 +10470,7 @@ rs6000_conditional_register_usage (void)
= call_really_used_regs[13] = 1;
/* Conditionally disable FPRs. */
if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
if (TARGET_SOFT_FLOAT)
for (i = 32; i < 64; i++)
fixed_regs[i] = call_used_regs[i]
= call_really_used_regs[i] = 1;
@ -11445,7 +11439,7 @@ rs6000_member_type_forces_blk (const_tree field, machine_mode mode)
#define USE_FP_FOR_ARG_P(CUM,MODE) \
(SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
&& (CUM)->fregno <= FP_ARG_MAX_REG \
&& TARGET_HARD_FLOAT && TARGET_FPRS)
&& TARGET_HARD_FLOAT)
/* Nonzero if we can use an AltiVec register to pass this arg. */
#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
@ -11971,7 +11965,7 @@ is_complex_IBM_long_double (machine_mode mode)
static bool
abi_v4_pass_in_fpr (machine_mode mode)
{
if (!TARGET_FPRS || !TARGET_HARD_FLOAT)
if (!TARGET_HARD_FLOAT)
return false;
if (TARGET_SINGLE_FLOAT && mode == SFmode)
return true;
@ -12071,7 +12065,6 @@ rs6000_function_arg_boundary (machine_mode mode, const_tree type)
if (DEFAULT_ABI == ABI_V4
&& (GET_MODE_SIZE (mode) == 8
|| (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& !is_complex_IBM_long_double (mode)
&& FLOAT128_2REG_P (mode))))
return 64;
@ -12524,7 +12517,7 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
cum->words = align_words + n_words;
if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
{
/* _Decimal128 must be passed in an even/odd float register pair.
This assumes that the register number is odd when fregno is
@ -13016,7 +13009,7 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
/* For the SPE, we need to crxor CR6 always. */
if (TARGET_SPE_ABI)
return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
else if (TARGET_HARD_FLOAT && TARGET_FPRS)
else if (TARGET_HARD_FLOAT)
return GEN_INT (cum->call_cookie
| ((cum->fregno == FP_ARG_MIN_REG)
? CALL_V4_SET_FP_ARGS
@ -13652,7 +13645,7 @@ setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
anything. */
if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
if (TARGET_HARD_FLOAT && TARGET_FPRS
if (TARGET_HARD_FLOAT
&& next_cum.fregno <= FP_ARG_V4_MAX_REG
&& cfun->va_list_fpr_size)
{
@ -13741,7 +13734,7 @@ setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
/* Save FP registers if needed. */
if (DEFAULT_ABI == ABI_V4
&& TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_HARD_FLOAT
&& ! no_rtl
&& next_cum.fregno <= FP_ARG_V4_MAX_REG
&& cfun->va_list_fpr_size)
@ -14112,9 +14105,7 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
/* _Decimal32 varargs are located in the second word of the 64-bit
FP register for 32-bit binaries. */
if (TARGET_32BIT
&& TARGET_HARD_FLOAT && TARGET_FPRS
&& mode == SDmode)
if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
t = fold_build_pointer_plus_hwi (t, size);
/* Args are passed right-aligned. */
@ -19506,7 +19497,7 @@ init_float128_ibm (machine_mode mode)
set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
if (!TARGET_HARD_FLOAT)
{
set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
@ -19515,6 +19506,7 @@ init_float128_ibm (machine_mode mode)
set_optab_libfunc (ge_optab, mode, "__gcc_qge");
set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
set_optab_libfunc (le_optab, mode, "__gcc_qle");
set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
@ -19525,9 +19517,6 @@ init_float128_ibm (machine_mode mode)
set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
}
if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
}
else
{
@ -24593,187 +24582,9 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
/* First, the compare. */
compare_result = gen_reg_rtx (comp_mode);
/* E500 FP compare instructions on the GPRs. Yuck! */
if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
&& FLOAT_MODE_P (mode))
{
rtx cmp, or_result, compare_result2;
machine_mode op_mode = GET_MODE (op0);
bool reverse_p;
if (op_mode == VOIDmode)
op_mode = GET_MODE (op1);
/* First reverse the condition codes that aren't directly supported. */
switch (code)
{
case NE:
case UNLT:
case UNLE:
case UNGT:
case UNGE:
code = reverse_condition_maybe_unordered (code);
reverse_p = true;
break;
case EQ:
case LT:
case LE:
case GT:
case GE:
reverse_p = false;
break;
default:
gcc_unreachable ();
}
/* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
This explains the following mess. */
switch (code)
{
case EQ:
switch (op_mode)
{
case SFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstsfeq_gpr (compare_result, op0, op1)
: gen_cmpsfeq_gpr (compare_result, op0, op1);
break;
case DFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstdfeq_gpr (compare_result, op0, op1)
: gen_cmpdfeq_gpr (compare_result, op0, op1);
break;
case TFmode:
case IFmode:
case KFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tsttfeq_gpr (compare_result, op0, op1)
: gen_cmptfeq_gpr (compare_result, op0, op1);
break;
default:
gcc_unreachable ();
}
break;
case GT:
case GE:
switch (op_mode)
{
case SFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstsfgt_gpr (compare_result, op0, op1)
: gen_cmpsfgt_gpr (compare_result, op0, op1);
break;
case DFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstdfgt_gpr (compare_result, op0, op1)
: gen_cmpdfgt_gpr (compare_result, op0, op1);
break;
case TFmode:
case IFmode:
case KFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tsttfgt_gpr (compare_result, op0, op1)
: gen_cmptfgt_gpr (compare_result, op0, op1);
break;
default:
gcc_unreachable ();
}
break;
case LT:
case LE:
switch (op_mode)
{
case SFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstsflt_gpr (compare_result, op0, op1)
: gen_cmpsflt_gpr (compare_result, op0, op1);
break;
case DFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstdflt_gpr (compare_result, op0, op1)
: gen_cmpdflt_gpr (compare_result, op0, op1);
break;
case TFmode:
case IFmode:
case KFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tsttflt_gpr (compare_result, op0, op1)
: gen_cmptflt_gpr (compare_result, op0, op1);
break;
default:
gcc_unreachable ();
}
break;
default:
gcc_unreachable ();
}
/* Synthesize LE and GE from LT/GT || EQ. */
if (code == LE || code == GE)
{
emit_insn (cmp);
compare_result2 = gen_reg_rtx (CCFPmode);
/* Do the EQ. */
switch (op_mode)
{
case SFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstsfeq_gpr (compare_result2, op0, op1)
: gen_cmpsfeq_gpr (compare_result2, op0, op1);
break;
case DFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tstdfeq_gpr (compare_result2, op0, op1)
: gen_cmpdfeq_gpr (compare_result2, op0, op1);
break;
case TFmode:
case IFmode:
case KFmode:
cmp = (flag_finite_math_only && !flag_trapping_math)
? gen_tsttfeq_gpr (compare_result2, op0, op1)
: gen_cmptfeq_gpr (compare_result2, op0, op1);
break;
default:
gcc_unreachable ();
}
emit_insn (cmp);
/* OR them together. */
or_result = gen_reg_rtx (CCFPmode);
cmp = gen_e500_cr_ior_compare (or_result, compare_result,
compare_result2);
compare_result = or_result;
}
code = reverse_p ? NE : EQ;
emit_insn (cmp);
}
/* IEEE 128-bit support in VSX registers when we do not have hardware
support. */
else if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
{
rtx libfunc = NULL_RTX;
bool check_nan = false;
@ -24890,7 +24701,7 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
CLOBBERs to match cmptf_internal2 pattern. */
if (comp_mode == CCFPmode && TARGET_XL_COMPAT
&& FLOAT128_IBM_P (GET_MODE (op0))
&& TARGET_HARD_FLOAT && TARGET_FPRS)
&& TARGET_HARD_FLOAT)
emit_insn (gen_rtx_PARALLEL (VOIDmode,
gen_rtvec (10,
gen_rtx_SET (compare_result,
@ -24925,7 +24736,6 @@ rs6000_generate_compare (rtx cmp, machine_mode mode)
if (FLOAT_MODE_P (mode)
&& (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
&& !flag_finite_math_only
&& !(TARGET_HARD_FLOAT && !TARGET_FPRS)
&& (code == LE || code == GE
|| code == UNEQ || code == LTGT
|| code == UNGT || code == UNLT))
@ -25287,23 +25097,6 @@ rs6000_emit_sCOND (machine_mode mode, rtx operands[])
condition_rtx = rs6000_generate_compare (operands[1], mode);
cond_code = GET_CODE (condition_rtx);
if (FLOAT_MODE_P (mode)
&& !TARGET_FPRS && TARGET_HARD_FLOAT)
{
rtx t;
PUT_MODE (condition_rtx, SImode);
t = XEXP (condition_rtx, 0);
gcc_assert (cond_code == NE || cond_code == EQ);
if (cond_code == NE)
emit_insn (gen_e500_flip_gt_bit (t, t));
emit_insn (gen_move_from_CR_gt_bit (result, t));
return;
}
if (cond_code == NE
|| cond_code == GE || cond_code == LE
|| cond_code == GEU || cond_code == LEU
@ -25394,26 +25187,6 @@ output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
code = reverse_condition (code);
}
if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
{
/* The efscmp/tst* instructions twiddle bit 2, which maps nicely
to the GT bit. */
switch (code)
{
case EQ:
/* Opposite of GT. */
code = GT;
break;
case NE:
code = UNLE;
break;
default:
gcc_unreachable ();
}
}
switch (code)
{
/* Not all of these are actually distinct opcodes, but
@ -25937,9 +25710,6 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
return 0;
}
else if (TARGET_HARD_FLOAT && !TARGET_FPRS
&& SCALAR_FLOAT_MODE_P (compare_mode))
return 0;
is_against_zero = op1 == CONST0_RTX (compare_mode);
@ -36643,9 +36413,9 @@ rs6000_elf_file_end (void)
{
int fp;
if (TARGET_DF_FPR | TARGET_DF_SPE)
if (TARGET_DF_FPR)
fp = 1;
else if (TARGET_SF_FPR | TARGET_SF_SPE)
else if (TARGET_SF_FPR)
fp = 3;
else
fp = 2;
@ -37716,8 +37486,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (1);
return true;
}
else if (FLOAT_MODE_P (mode)
&& TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
{
*total = rs6000_cost->fp;
return false;
@ -38855,7 +38624,7 @@ rs6000_complex_function_value (machine_mode mode)
|| (mode == TCmode && TARGET_IEEEQUAD)))
regno = ALTIVEC_ARG_RETURN;
else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
regno = FP_ARG_RETURN;
else
@ -38976,10 +38745,10 @@ rs6000_function_value (const_tree valtype,
|| POINTER_TYPE_P (valtype))
mode = TARGET_32BIT ? SImode : DImode;
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
&& !FLOAT128_VECTOR_P (mode)
&& ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
regno = FP_ARG_RETURN;
@ -39014,11 +38783,11 @@ rs6000_libcall_value (machine_mode mode)
if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
&& TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_HARD_FLOAT
&& ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
regno = FP_ARG_RETURN;
/* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
@ -39064,7 +38833,7 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
{
if (TARGET_ALTIVEC)
pressure_classes[n++] = ALTIVEC_REGS;
if (TARGET_HARD_FLOAT && TARGET_FPRS)
if (TARGET_HARD_FLOAT)
pressure_classes[n++] = FLOAT_REGS;
}
pressure_classes[n++] = CR_REGS;
@ -44008,7 +43777,7 @@ static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
static void
rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
if (!TARGET_HARD_FLOAT)
{
#ifdef RS6000_GLIBC_ATOMIC_FENV
if (atomic_hold_decl == NULL_TREE)

38
gcc/config/rs6000/rs6000.h
View File

@ -449,8 +449,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define FLOAT128_IBM_P(MODE) \
((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
|| (TARGET_HARD_FLOAT && TARGET_FPRS \
&& ((MODE) == IFmode || (MODE) == ICmode)))
|| (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
/* Helper macros to say whether a 128-bit floating point type can go in a
single vector register, or whether it needs paired scalar values. */
@ -573,7 +572,6 @@ extern int rs6000_vector_align[];
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
#define TARGET_FPRS 1
#define TARGET_E500_SINGLE 0
#define TARGET_E500_DOUBLE 0
#define CHECK_E500_OPTIONS do { } while (0)
@ -724,39 +722,26 @@ extern int rs6000_vector_align[];
|| rs6000_cpu == PROCESSOR_PPC8548)
/* Whether SF/DF operations are supported on the E500. */
#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
&& !TARGET_FPRS)
#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& !TARGET_FPRS && TARGET_E500_DOUBLE)
/* Whether SF/DF operations are supported by the normal floating point unit
(or the vector/scalar unit). */
#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
&& TARGET_SINGLE_FLOAT)
#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
&& TARGET_DOUBLE_FLOAT)
#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT)
#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
/* Whether SF/DF operations are supported by any hardware. */
#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
#define TARGET_SF_INSN TARGET_SF_FPR
#define TARGET_DF_INSN TARGET_DF_FPR
/* Which machine supports the various reciprocal estimate instructions. */
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
&& TARGET_FPRS && TARGET_SINGLE_FLOAT)
&& TARGET_SINGLE_FLOAT)
#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
&& TARGET_DOUBLE_FLOAT \
#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
&& TARGET_PPC_GFXOPT && TARGET_FPRS \
&& TARGET_SINGLE_FLOAT)
&& TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT)
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
&& TARGET_DOUBLE_FLOAT \
#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
&& (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
/* Conditions to allow TOC fusion for loading/storing integers. */
@ -771,7 +756,6 @@ extern int rs6000_vector_align[];
&& (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64 \
&& TARGET_HARD_FLOAT \
&& TARGET_FPRS \
&& TARGET_SINGLE_FLOAT \
&& TARGET_DOUBLE_FLOAT)
@ -1875,7 +1859,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define FUNCTION_VALUE_REGNO_P(N) \
((N) == GP_ARG_RETURN \
|| (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
&& TARGET_HARD_FLOAT && TARGET_FPRS) \
&& TARGET_HARD_FLOAT) \
|| (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
@ -1887,7 +1871,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
|| (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
|| (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
&& TARGET_HARD_FLOAT && TARGET_FPRS))
&& TARGET_HARD_FLOAT))
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should

262
gcc/config/rs6000/rs6000.md
View File

@ -372,22 +372,18 @@
; Any hardware-supported floating-point mode
(define_mode_iterator FP [
(SF "TARGET_HARD_FLOAT
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
(DF "TARGET_HARD_FLOAT
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
(TF "TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE)
&& TARGET_LONG_DOUBLE_128")
(IF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")
(SF "TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT || TARGET_E500_SINGLE)")
(DF "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)")
(TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(KF "TARGET_FLOAT128_TYPE")
(DD "TARGET_DFP")
(TD "TARGET_DFP")])
; Any fma capable floating-point mode.
(define_mode_iterator FMA_F [
(SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
(DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
(SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
(DF "(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| VECTOR_UNIT_VSX_P (DFmode)")
(V2SF "TARGET_PAIRED_FLOAT")
(V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
@ -402,11 +398,11 @@
(define_mode_iterator FMOVE64X [DI DF DD])
(define_mode_iterator FMOVE128 [(TF "TARGET_LONG_DOUBLE_128")
(IF "FLOAT128_IBM_P (IFmode)")
(TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
(TD "TARGET_HARD_FLOAT")])
(define_mode_iterator FMOVE128_FPR [(TF "FLOAT128_2REG_P (TFmode)")
(IF "FLOAT128_2REG_P (IFmode)")
(TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
(TD "TARGET_HARD_FLOAT")])
; Iterators for 128 bit types for direct move
(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
@ -426,7 +422,7 @@
; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
(DF "")
(SD "TARGET_HARD_FLOAT && TARGET_FPRS")
(SD "TARGET_HARD_FLOAT")
(DD "")])
; Convert REAL_VALUE to the appropriate bits
@ -618,7 +614,7 @@
(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
(DF "TARGET_FCFID")])
(define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
(define_mode_attr E500_CONVERT [(SF "0")
(DF "TARGET_E500_DOUBLE")])
(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
@ -4650,7 +4646,7 @@
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand")
(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
"TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
{
if (HONOR_SNANS (SFmode))
operands[1] = force_reg (SFmode, operands[1]);
@ -4659,8 +4655,7 @@
(define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,wb")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !HONOR_SNANS (SFmode)"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !HONOR_SNANS (SFmode)"
"@
#
fmr %0,%1
@ -4680,8 +4675,7 @@
(define_insn "*extendsfdf2_snan"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wy")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& HONOR_SNANS (SFmode)"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && HONOR_SNANS (SFmode)"
"@
frsp %0,%1
xsrsp %x0,%x1"
@ -4690,13 +4684,13 @@
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
"TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
"")
(define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
frsp %0,%1
xsrsp %x0,%x1"
@ -4715,7 +4709,6 @@
(set (match_operand:SI 0 "gpc_reg_operand" "")
(match_dup 6))]
"TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE)
&& (!FLOAT128_IEEE_P (<MODE>mode)
|| (TARGET_POWERPC64 && TARGET_DIRECT_MOVE))"
{
@ -4757,7 +4750,7 @@
(match_dup 5))
(match_dup 3)
(match_dup 4)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
"TARGET_HARD_FLOAT && <TARGET_FLOAT>
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
@ -5096,7 +5089,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wK")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wK")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
"@
lfiwax %0,%y1
lxsiwax %x0,%y1
@ -5113,7 +5106,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wi"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP> && can_create_pseudo_p ()"
"#"
""
@ -5156,8 +5149,7 @@
(sign_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
(clobber (match_scratch:DI 2 "=wi"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP>"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
@ -5180,7 +5172,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wJwK")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wJwK")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
"@
lfiwzx %0,%y1
lxsiwzx %x0,%y1
@ -5192,8 +5184,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wi"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
&& <SI_CONVERT_FP>"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
@ -5235,8 +5226,7 @@
(zero_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
(clobber (match_scratch:DI 2 "=wi"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
&& <SI_CONVERT_FP>"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
@ -5268,8 +5258,7 @@
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])]
"TARGET_HARD_FLOAT
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
"TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
"
{
if (TARGET_E500_DOUBLE)
@ -5311,7 +5300,7 @@
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
"! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"#"
""
[(pc)]
@ -5342,19 +5331,12 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (!TARGET_FPRS
|| (TARGET_FPRS
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
"
{
if (!TARGET_FPRS)
{
if (!REG_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
}
else if (TARGET_LFIWZX && TARGET_FCFIDUS)
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
@ -5377,8 +5359,7 @@
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
"TARGET_HARD_FLOAT
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
"TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
"
{
if (TARGET_E500_DOUBLE)
@ -5418,7 +5399,7 @@
(use (match_operand:DF 3 "gpc_reg_operand" "d"))
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
"! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& !(TARGET_FCFID && TARGET_POWERPC64)"
"#"
""
@ -5551,7 +5532,7 @@
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
"TARGET_HARD_FLOAT && (<TARGET_FLOAT> || <E500_CONVERT>)"
"
{
if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
@ -5578,7 +5559,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
&& TARGET_STFIWX && can_create_pseudo_p ()
&& !TARGET_VSX_SMALL_INTEGER"
@ -5622,8 +5603,7 @@
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& !TARGET_VSX_SMALL_INTEGER"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_VSX_SMALL_INTEGER"
"#"
""
[(pc)]
@ -5644,15 +5624,13 @@
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
&& TARGET_FCFID"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"")
(define_insn "*fix_trunc<mode>di2_fctidz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
&& TARGET_FCFID"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"@
fctidz %0,%1
xscvdpsxds %x0,%x1"
@ -5703,8 +5681,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT
&& ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
|| <E500_CONVERT>)"
&& ((<TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX) || <E500_CONVERT>)"
"
{
if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
@ -5718,7 +5695,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ
&& TARGET_STFIWX && can_create_pseudo_p ()
&& !TARGET_VSX_SMALL_INTEGER"
"#"
@ -5759,7 +5736,7 @@
(define_insn "fixuns_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCTIDUZ"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCTIDUZ"
"@
fctiduz %0,%1
xscvdpuxds %x0,%x1"
@ -5812,8 +5789,7 @@
(define_insn "*fctiw<u>z_<mode>_smallint"
[(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_VSX_SMALL_INTEGER"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
"@
fctiw<u>z %0,%1
xscvdp<su>xws %x0,%x1"
@ -5825,8 +5801,7 @@
[(set (match_operand:SI 0 "memory_operand" "=Z")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
(clobber (match_scratch:SI 2 "=wa"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_VSX_SMALL_INTEGER"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
"#"
"&& reload_completed"
[(set (match_dup 2)
@ -5843,7 +5818,7 @@
(unspec:DI [(fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
fctiwz %0,%1
xscvdpsxws %x0,%x1"
@ -5854,7 +5829,7 @@
(unspec:DI [(unsigned_fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWUZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ"
"@
fctiwuz %0,%1
xscvdpuxws %x0,%x1"
@ -5866,7 +5841,7 @@
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
@ -5885,7 +5860,7 @@
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
&& !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
"#"
@ -5918,7 +5893,7 @@
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
&& can_create_pseudo_p ()"
"#"
@ -6038,19 +6013,12 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (!TARGET_FPRS
|| (TARGET_FPRS
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
|| (TARGET_DOUBLE_FLOAT && TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
"
{
if (!TARGET_FPRS)
{
if (!REG_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
}
else if (TARGET_FCFIDS && TARGET_LFIWAX)
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
@ -6073,16 +6041,10 @@
}
}")
(define_expand "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
"")
(define_insn "*floatdidf2_fpr"
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"@
fcfid %0,%1
xscvsxddp %x0,%x1"
@ -6097,7 +6059,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wi"))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
@ -6139,7 +6101,7 @@
(define_expand "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
"
{
@ -6161,7 +6123,7 @@
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
"@
fcfids %0,%1
@ -6172,7 +6134,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
(float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wi"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
"#"
"&& reload_completed"
@ -6193,8 +6155,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=d"))]
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
&& !TARGET_FCFIDS"
"TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_FCFIDS"
"#"
"&& reload_completed"
[(set (match_dup 2)
@ -6229,7 +6190,7 @@
(label_ref (match_operand:DI 2 "" ""))
(pc)))
(set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& !TARGET_FCFIDS"
"
{
@ -6240,14 +6201,14 @@
(define_expand "floatunsdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"")
(define_insn "floatunsdisf2_fcfidus"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
(unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"@
fcfidus %0,%1
@ -6258,7 +6219,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
(unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wi"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
"#"
"&& reload_completed"
@ -7209,7 +7170,7 @@
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
&& TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& (TARGET_ALLOW_SF_SUBREG
|| valid_sf_si_move (operands[0], operands[1], SFmode))"
"@
@ -7245,7 +7206,7 @@
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
&& TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
"@
lwz%U1%X1 %0,%1
lfiwzx %0,%y1
@ -7267,7 +7228,7 @@
(match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))
&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
&& TARGET_SOFT_FLOAT"
"@
mr %0,%1
mt%0 %1
@ -7446,7 +7407,7 @@
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
@ -7471,8 +7432,7 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
&& (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
|| (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@ -7485,7 +7445,7 @@
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
@ -7516,7 +7476,7 @@
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
"TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
"TARGET_POWERPC64 && TARGET_SOFT_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
@ -7549,8 +7509,7 @@
(define_insn_and_split "*mov<mode>_64bit_dm"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh")
(match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,wh,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
&& FLOAT128_2REG_P (<MODE>mode)
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
&& (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@ -7563,7 +7522,7 @@
(define_insn_and_split "*movtd_64bit_nodm"
[(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
(match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
&& (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))"
"#"
@ -7575,7 +7534,7 @@
(define_insn_and_split "*mov<mode>_32bit"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
(match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
"TARGET_HARD_FLOAT && !TARGET_POWERPC64
&& (FLOAT128_2REG_P (<MODE>mode)
|| int_reg_operand_not_pseudo (operands[0], <MODE>mode)
|| int_reg_operand_not_pseudo (operands[1], <MODE>mode))
@ -7590,7 +7549,7 @@
(define_insn_and_split "*mov<mode>_softfloat"
[(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
(match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
"(TARGET_SOFT_FLOAT || !TARGET_FPRS)
"TARGET_SOFT_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
@ -7602,8 +7561,7 @@
(define_expand "extenddf<mode>2"
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)
&& TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
@ -7642,7 +7600,7 @@
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
(use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
"!TARGET_VSX && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"!TARGET_VSX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
@ -7677,9 +7635,7 @@
(define_expand "extendsf<mode>2"
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE)
&& TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
@ -7695,9 +7651,7 @@
(define_expand "trunc<mode>df2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE)
&& TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
{
@ -7711,7 +7665,7 @@
(float_truncate:DF
(match_operand:IBM128 1 "gpc_reg_operand" "0,d")))]
"FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"@
#
fmr %0,%1"
@ -7727,7 +7681,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT
&& TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
&& TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"fadd %0,%1,%L1"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_d")])
@ -7735,9 +7689,7 @@
(define_expand "trunc<mode>sf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE)
&& TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
@ -7759,7 +7711,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:IBM128 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
@ -7773,9 +7725,7 @@
[(parallel [(set (match_operand:FLOAT128 0 "gpc_reg_operand")
(float:FLOAT128 (match_operand:SI 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
"TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE)
&& TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@ -7808,8 +7758,7 @@
(unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")]
UNSPEC_FIX_TRUNC_TF))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& FLOAT128_IBM_P (<MODE>mode)"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
[(set_attr "type" "fp")
(set_attr "length" "20")])
@ -7817,8 +7766,7 @@
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
rtx op0 = operands[0];
rtx op1 = operands[1];
@ -7848,7 +7796,7 @@
(clobber (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
operands[2] = gen_reg_rtx (DFmode);
operands[3] = gen_reg_rtx (DFmode);
@ -7863,7 +7811,7 @@
(clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
(clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
(clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
""
[(pc)]
@ -7945,9 +7893,7 @@
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode)
&& TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE))"
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
"
{
if (FLOAT128_IEEE_P (<MODE>mode))
@ -7987,7 +7933,7 @@
(define_insn "neg<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
(neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && FLOAT128_IBM_P (TFmode)"
"TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)"
"*
{
if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
@ -8002,9 +7948,7 @@
[(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
(abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
"FLOAT128_IEEE_P (<MODE>mode)
|| (FLOAT128_IBM_P (<MODE>mode)
&& TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE))"
|| (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
"
{
rtx label;
@ -8063,8 +8007,7 @@
(label_ref (match_operand 2 "" ""))
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LONG_DOUBLE_128"
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"
{
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
@ -9750,7 +9693,7 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@ -9766,7 +9709,7 @@
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@ -9782,7 +9725,7 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
"(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
"TARGET_SOFT_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@ -9798,7 +9741,7 @@
(match_operand:SF 3 "gpc_reg_operand" "r,r"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
"(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
"TARGET_SOFT_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@ -9814,7 +9757,7 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@ -9831,7 +9774,7 @@
(match_operand:DF 3 "gpc_reg_operand" "d,d"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
@ -12057,7 +12000,7 @@
(compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
(match_operand:IBM128 2 "gpc_reg_operand" "d")))]
"!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
&& TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
[(set_attr "type" "fpcompare")
(set_attr "length" "12")])
@ -12076,7 +12019,7 @@
(clobber (match_scratch:DF 10 "=d"))
(clobber (match_scratch:GPR 11 "=b"))]
"TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
&& TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 3) (match_dup 14))
@ -12144,15 +12087,6 @@
(const_string "mfcr")))
(set_attr "length" "8")])
;; Same as above, but get the GT bit.
(define_insn "move_from_CR_gt_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"mfcr %0\;rlwinm %0,%0,%D1,31,31"
[(set_attr "type" "mfcr")
(set_attr "length" "8")])
;; Same as above, but get the OV/ORDERED bit.
(define_insn "move_from_CR_ov_bit"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@ -13822,14 +13756,14 @@
(define_insn "rs6000_mffs"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"mffs %0")
(define_insn "rs6000_mtfsf"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
(match_operand:DF 1 "gpc_reg_operand" "d")]
UNSPECV_MTFSF)]
"TARGET_HARD_FLOAT && TARGET_FPRS"
"TARGET_HARD_FLOAT"
"mtfsf %0,%1")

170
gcc/config/rs6000/spe.md
View File

@ -31,7 +31,6 @@
(TSTTFGT_GPR 1015)
(CMPTFLT_GPR 1016)
(TSTTFLT_GPR 1017)
(E500_CR_IOR_COMPARE 1018)
])
;; Modes using a 64-bit register.
@ -43,59 +42,6 @@
;; DImode and TImode.
(define_mode_iterator DITI [DI TI])
(define_insn "*negsf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsneg %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*abssf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*nabssf2_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsnabs %0,%1"
[(set_attr "type" "fpsimple")])
(define_insn "*addsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsadd %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "*subsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efssub %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "*mulsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsmul %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "*divsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsdiv %0,%1,%2"
[(set_attr "type" "vecfdiv")])
;; Floating point conversion instructions.
(define_insn "spe_fixuns_truncdfsi2"
@ -112,20 +58,6 @@
"efdcfs %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_fixuns_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsctuiz %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_fix_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efsctsiz %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_fix_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
@ -133,13 +65,6 @@
"efdctsiz %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efscfui %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_floatunssidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
@ -147,13 +72,6 @@
"efdcfui %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"efscfsi %0,%1"
[(set_attr "type" "fp")])
(define_insn "spe_floatsidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
@ -3233,88 +3151,10 @@
"mfspefscr %0"
[(set_attr "type" "vecsimple")])
;; Flip the GT bit.
(define_insn "e500_flip_gt_bit"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
"!TARGET_FPRS && TARGET_HARD_FLOAT"
"*
{
return output_e500_flip_gt_bit (operands[0], operands[1]);
}"
[(set_attr "type" "cr_logical")])
;; MPC8540 single-precision FP instructions on GPRs.
;; We have 2 variants for each. One for IEEE compliant math and one
;; for non IEEE compliant math.
(define_insn "cmpsfeq_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1000))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& !(flag_finite_math_only && !flag_trapping_math)"
"efscmpeq %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "tstsfeq_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1001))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& flag_finite_math_only && !flag_trapping_math"
"efststeq %0,%1,%2"
[(set_attr "type" "veccmpsimple")])
(define_insn "cmpsfgt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1002))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& !(flag_finite_math_only && !flag_trapping_math)"
"efscmpgt %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "tstsfgt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1003))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& flag_finite_math_only && !flag_trapping_math"
"efststgt %0,%1,%2"
[(set_attr "type" "veccmpsimple")])
(define_insn "cmpsflt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1004))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& !(flag_finite_math_only && !flag_trapping_math)"
"efscmplt %0,%1,%2"
[(set_attr "type" "veccmp")])
(define_insn "tstsflt_gpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP
[(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r"))]
1005))]
"TARGET_HARD_FLOAT && !TARGET_FPRS
&& flag_finite_math_only && !flag_trapping_math"
"efststlt %0,%1,%2"
[(set_attr "type" "veccmpsimple")])
;; Same thing, but for double-precision.
(define_insn "cmpdfeq_gpr"
@ -3463,16 +3303,6 @@
[(set_attr "type" "veccmpsimple")
(set_attr "length" "20")])
;; Like cceq_ior_compare, but compare the GT bits.
(define_insn "e500_cr_ior_compare"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
(match_operand 2 "cc_reg_operand" "y")]
E500_CR_IOR_COMPARE))]
"TARGET_HARD_FLOAT && !TARGET_FPRS"
"cror 4*%0+gt,4*%1+gt,4*%2+gt"
[(set_attr "type" "cr_logical")])
;; Out-of-line prologues and epilogues.
(define_insn "*save_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"

2
gcc/config/rs6000/vsx.md
View File

@ -1984,7 +1984,7 @@
(float:V2DF
(fix:V2DI
(match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ"
"xvrdpiz %x0,%x1"