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Replace _rdrand_uXX with _rdrandXX_step.
gcc/ 2010-12-28 H.J. Lu <hongjiu.lu@intel.com> Uros Bizjak <ubizjak@gmail.com> * config/i386/i386-builtin-types.def (PUSHORT): New. (INT_FTYPE_PUSHORT): Likewise. (INT_FTYPE_PUNSIGNED): Likewise. (INT_FTYPE_PULONGLONG): Likewise. Remove "DEF_FUNCTION_TYPE (UINT16)". * config/i386/i386.c (ix86_builtins): Remove IX86_BUILTIN_RDRAND16, IX86_BUILTIN_RDRAND32 and IX86_BUILTIN_RDRAND64. Add IX86_BUILTIN_RDRAND16_STEP, IX86_BUILTIN_RDRAND32_STEP and IX86_BUILTIN_RDRAND64_STEP. (bdesc_special_args): Remove IX86_BUILTIN_RDRAND16, IX86_BUILTIN_RDRAND32 and IX86_BUILTIN_RDRAND64. (ix86_init_mmx_sse_builtins): Handle IX86_BUILTIN_RDRAND16_STEP, IX86_BUILTIN_RDRAND32_STEP and IX86_BUILTIN_RDRAND64_STEP. (ix86_expand_builtin): Likewise. (ix86_expand_special_args_builtin): Remove UINT16_FTYPE_VOID. * config/i386/i386.md (UNSPEC_RDRAND): New. (UNSPECV_RDRAND): Removed. (rdrand<mode>): Likewise. (rdrand<mode>_1): Also set FLAGS_REG. Replace UNSPECV_RDRAND with UNSPEC_RDRAND. * config/i386/immintrin.h (_rdrand_u16): Removed. (_rdrand_u32): Likewise. (_rdrand_u64): Likewise. (_rdrand16_step): New. (_rdrand32_step): Likewise. (_rdrand64_step): Likewise. * doc/extend.texi (__builtin_ia32_rdrand16): Removed. (__builtin_ia32_rdrand32): Likewise. (__builtin_ia32_rdrand64): Likewise. (__builtin_ia32_rdrand16_step): New. (__builtin_ia32_rdrand32_step): Likewise. (__builtin_ia32_rdrand64_step): Likewise. gcc/testsuite/ 2010-12-28 H.J. Lu <hongjiu.lu@intel.com> * gcc.target/i386/rdrand-1.c: Updated. * gcc.target/i386/rdrand-2.c: Likewise. * gcc.target/i386/rdrand-3.c: Likewise. Co-Authored-By: Uros Bizjak <ubizjak@gmail.com> From-SVN: r168298
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11c4a1c004
@ -1,3 +1,43 @@
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2010-12-28 H.J. Lu <hongjiu.lu@intel.com>
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Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386-builtin-types.def (PUSHORT): New.
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(INT_FTYPE_PUSHORT): Likewise.
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(INT_FTYPE_PUNSIGNED): Likewise.
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(INT_FTYPE_PULONGLONG): Likewise.
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Remove "DEF_FUNCTION_TYPE (UINT16)".
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* config/i386/i386.c (ix86_builtins): Remove
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IX86_BUILTIN_RDRAND16, IX86_BUILTIN_RDRAND32 and
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IX86_BUILTIN_RDRAND64. Add IX86_BUILTIN_RDRAND16_STEP,
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IX86_BUILTIN_RDRAND32_STEP and IX86_BUILTIN_RDRAND64_STEP.
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(bdesc_special_args): Remove IX86_BUILTIN_RDRAND16,
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IX86_BUILTIN_RDRAND32 and IX86_BUILTIN_RDRAND64.
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(ix86_init_mmx_sse_builtins): Handle IX86_BUILTIN_RDRAND16_STEP,
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IX86_BUILTIN_RDRAND32_STEP and IX86_BUILTIN_RDRAND64_STEP.
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(ix86_expand_builtin): Likewise.
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(ix86_expand_special_args_builtin): Remove UINT16_FTYPE_VOID.
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* config/i386/i386.md (UNSPEC_RDRAND): New.
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(UNSPECV_RDRAND): Removed.
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(rdrand<mode>): Likewise.
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(rdrand<mode>_1): Also set FLAGS_REG. Replace UNSPECV_RDRAND
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with UNSPEC_RDRAND.
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* config/i386/immintrin.h (_rdrand_u16): Removed.
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(_rdrand_u32): Likewise.
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(_rdrand_u64): Likewise.
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(_rdrand16_step): New.
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(_rdrand32_step): Likewise.
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(_rdrand64_step): Likewise.
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* doc/extend.texi (__builtin_ia32_rdrand16): Removed.
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(__builtin_ia32_rdrand32): Likewise.
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(__builtin_ia32_rdrand64): Likewise.
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(__builtin_ia32_rdrand16_step): New.
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(__builtin_ia32_rdrand32_step): Likewise.
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(__builtin_ia32_rdrand64_step): Likewise.
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2010-12-28 Sebastian Pop <sebastian.pop@amd.com>
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* Makefile.in (graphite.o): Add dependence on DIAGNOSTIC_H.
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@ -107,6 +107,7 @@ DEF_POINTER_TYPE (PCVOID, VOID, CONST)
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DEF_POINTER_TYPE (PVOID, VOID)
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DEF_POINTER_TYPE (PDOUBLE, DOUBLE)
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DEF_POINTER_TYPE (PFLOAT, FLOAT)
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DEF_POINTER_TYPE (PUSHORT, USHORT)
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DEF_POINTER_TYPE (PINT, INT)
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DEF_POINTER_TYPE (PULONGLONG, ULONGLONG)
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DEF_POINTER_TYPE (PUNSIGNED, UNSIGNED)
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@ -128,7 +129,6 @@ DEF_POINTER_TYPE (PCV8SF, V8SF, CONST)
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DEF_FUNCTION_TYPE (FLOAT128)
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DEF_FUNCTION_TYPE (UINT64)
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DEF_FUNCTION_TYPE (UNSIGNED)
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DEF_FUNCTION_TYPE (UINT16)
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DEF_FUNCTION_TYPE (VOID)
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DEF_FUNCTION_TYPE (PVOID)
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@ -203,6 +203,9 @@ DEF_FUNCTION_TYPE (VOID, PCVOID)
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DEF_FUNCTION_TYPE (VOID, PVOID)
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DEF_FUNCTION_TYPE (VOID, UINT64)
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DEF_FUNCTION_TYPE (VOID, UNSIGNED)
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DEF_FUNCTION_TYPE (INT, PUSHORT)
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DEF_FUNCTION_TYPE (INT, PUNSIGNED)
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DEF_FUNCTION_TYPE (INT, PULONGLONG)
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DEF_FUNCTION_TYPE (DI, V2DI, INT)
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DEF_FUNCTION_TYPE (DOUBLE, V2DF, INT)
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@ -24142,9 +24142,9 @@ enum ix86_builtins
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IX86_BUILTIN_WRGSBASE64,
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/* RDRND instructions. */
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IX86_BUILTIN_RDRAND16,
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IX86_BUILTIN_RDRAND32,
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IX86_BUILTIN_RDRAND64,
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IX86_BUILTIN_RDRAND16_STEP,
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IX86_BUILTIN_RDRAND32_STEP,
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IX86_BUILTIN_RDRAND64_STEP,
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/* F16C instructions. */
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IX86_BUILTIN_CVTPH2PS,
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@ -24435,11 +24435,6 @@ static const struct builtin_description bdesc_special_args[] =
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{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
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{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
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{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
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/* RDRND */
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{ OPTION_MASK_ISA_RDRND, CODE_FOR_rdrandhi, "__builtin_ia32_rdrand16", IX86_BUILTIN_RDRAND16, UNKNOWN, (int) UINT16_FTYPE_VOID },
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{ OPTION_MASK_ISA_RDRND, CODE_FOR_rdrandsi, "__builtin_ia32_rdrand32", IX86_BUILTIN_RDRAND32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
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{ OPTION_MASK_ISA_RDRND | OPTION_MASK_ISA_64BIT, CODE_FOR_rdranddi, "__builtin_ia32_rdrand64", IX86_BUILTIN_RDRAND64, UNKNOWN, (int) UINT64_FTYPE_VOID },
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};
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/* Builtins with variable number of arguments. */
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@ -25448,6 +25443,15 @@ ix86_init_mmx_sse_builtins (void)
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def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128",
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V2DI_FTYPE_V2DI_V2DI_INT, IX86_BUILTIN_PCLMULQDQ128);
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/* RDRND */
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def_builtin (OPTION_MASK_ISA_RDRND, "__builtin_ia32_rdrand16_step",
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INT_FTYPE_PUSHORT, IX86_BUILTIN_RDRAND16_STEP);
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def_builtin (OPTION_MASK_ISA_RDRND, "__builtin_ia32_rdrand32_step",
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INT_FTYPE_PUNSIGNED, IX86_BUILTIN_RDRAND32_STEP);
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def_builtin (OPTION_MASK_ISA_RDRND | OPTION_MASK_ISA_64BIT,
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"__builtin_ia32_rdrand64_step", INT_FTYPE_PULONGLONG,
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IX86_BUILTIN_RDRAND64_STEP);
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/* MMX access to the vec_init patterns. */
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def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si",
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V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI);
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@ -26703,7 +26707,6 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
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break;
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case UINT64_FTYPE_VOID:
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case UNSIGNED_FTYPE_VOID:
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case UINT16_FTYPE_VOID:
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nargs = 0;
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klass = load;
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memory = 0;
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@ -27215,6 +27218,51 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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return target;
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}
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case IX86_BUILTIN_RDRAND16_STEP:
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icode = CODE_FOR_rdrandhi_1;
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mode0 = HImode;
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goto rdrand_step;
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case IX86_BUILTIN_RDRAND32_STEP:
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icode = CODE_FOR_rdrandsi_1;
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mode0 = SImode;
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goto rdrand_step;
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case IX86_BUILTIN_RDRAND64_STEP:
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icode = CODE_FOR_rdranddi_1;
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mode0 = DImode;
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rdrand_step:
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op0 = gen_reg_rtx (mode0);
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emit_insn (GEN_FCN (icode) (op0));
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op1 = gen_reg_rtx (SImode);
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emit_move_insn (op1, CONST1_RTX (SImode));
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/* Emit SImode conditional move. */
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if (mode0 == HImode)
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{
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op2 = gen_reg_rtx (SImode);
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emit_insn (gen_zero_extendhisi2 (op2, op0));
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}
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else if (mode0 == SImode)
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op2 = op0;
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else
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op2 = gen_rtx_SUBREG (SImode, op0, 0);
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pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG),
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const0_rtx);
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emit_insn (gen_rtx_SET (VOIDmode, op1,
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gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1)));
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emit_move_insn (target, op1);
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arg0 = CALL_EXPR_ARG (exp, 0);
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op1 = expand_normal (arg0);
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if (!address_operand (op1, VOIDmode))
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op1 = copy_addr_to_reg (op1);
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emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
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return target;
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default:
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break;
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}
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@ -232,6 +232,9 @@
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;; For BMI support
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UNSPEC_BEXTR
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;; For RDRAND support
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UNSPEC_RDRAND
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])
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(define_c_enum "unspecv" [
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@ -265,7 +268,6 @@
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UNSPECV_RDGSBASE
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UNSPECV_WRFSBASE
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UNSPECV_WRGSBASE
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UNSPECV_RDRAND
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UNSPECV_SPLIT_STACK_RETURN
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])
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@ -18284,36 +18286,13 @@
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[(set_attr "type" "other")
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(set_attr "prefix_extra" "2")])
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(define_expand "rdrand<mode>"
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[(set (match_operand:SWI248 0 "register_operand" "=r")
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(unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))]
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"TARGET_RDRND"
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{
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rtx retry_label, insn, ccc;
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retry_label = gen_label_rtx ();
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emit_label (retry_label);
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/* Generate rdrand. */
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emit_insn (gen_rdrand<mode>_1 (operands[0]));
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/* Retry if the carry flag isn't valid. */
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ccc = gen_rtx_REG (CCCmode, FLAGS_REG);
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ccc = gen_rtx_EQ (VOIDmode, ccc, const0_rtx);
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ccc = gen_rtx_IF_THEN_ELSE (VOIDmode, ccc, pc_rtx,
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gen_rtx_LABEL_REF (VOIDmode, retry_label));
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insn = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, ccc));
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JUMP_LABEL (insn) = retry_label;
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DONE;
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})
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(define_insn "rdrand<mode>_1"
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[(set (match_operand:SWI248 0 "register_operand" "=r")
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(unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))]
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(unspec:SWI248 [(const_int 0)] UNSPEC_RDRAND))
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(set (reg:CCC FLAGS_REG)
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(unspec:CCC [(const_int 0)] UNSPEC_RDRAND))]
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"TARGET_RDRND"
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"rdrand %0"
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"rdrand\t%0"
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[(set_attr "type" "other")
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(set_attr "prefix_extra" "1")])
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#endif
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#ifdef __RDRND__
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extern __inline unsigned short
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extern __inline int
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_rdrand_u16 (void)
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_rdrand16_step (unsigned short *__P)
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{
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return __builtin_ia32_rdrand16 ();
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return __builtin_ia32_rdrand16_step (__P);
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}
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extern __inline unsigned int
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extern __inline int
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_rdrand_u32 (void)
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_rdrand32_step (unsigned int *__P)
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{
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return __builtin_ia32_rdrand32 ();
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return __builtin_ia32_rdrand32_step (__P);
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}
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#endif /* __RDRND__ */
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@ -132,11 +132,11 @@ _writegsbase_u64 (unsigned long long __B)
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#endif /* __FSGSBASE__ */
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#ifdef __RDRND__
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extern __inline unsigned long long
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extern __inline int
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_rdrand_u64 (void)
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_rdrand64_step (unsigned long long *__P)
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{
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return __builtin_ia32_rdrand64 ();
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return __builtin_ia32_rdrand64_step (__P);
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}
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#endif /* __RDRND__ */
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#endif /* __x86_64__ */
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@ -9381,9 +9381,9 @@ used. All of them generate the machine instruction that is part of the
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name.
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@smallexample
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unsigned short __builtin_ia32_rdrand16 (void)
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unsigned int __builtin_ia32_rdrand32 (void)
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unsigned long long __builtin_ia32_rdrand64 (void)
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unsigned int __builtin_ia32_rdrand16_step (unsigned short *)
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unsigned int __builtin_ia32_rdrand32_step (unsigned int *)
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unsigned int __builtin_ia32_rdrand64_step (unsigned long long *)
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@end smallexample
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The following built-in functions are available when @option{-msse4a} is used.
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@ -1,3 +1,9 @@
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2010-12-28 H.J. Lu <hongjiu.lu@intel.com>
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* gcc.target/i386/rdrand-1.c: Updated.
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* gcc.target/i386/rdrand-2.c: Likewise.
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* gcc.target/i386/rdrand-3.c: Likewise.
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2010-12-28 Nicola Pero <nicola.pero@meta-innovation.com>
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* objc.dg/class-extension-4.m: New.
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@ -1,12 +1,12 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mrdrnd " } */
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/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)ax" } } */
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/* { dg-final { scan-assembler "jnc\[ \t]+" } } */
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/* { dg-options "-O2 -mrdrnd -dp" } */
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/* { dg-final { scan-assembler-times "rdrandhi_1" 1 } } */
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/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
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#include <immintrin.h>
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unsigned short
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read_rdrand16 (void)
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int
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foo (unsigned short *x)
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{
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return _rdrand_u16 ();
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return _rdrand16_step (x);
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}
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@ -1,12 +1,12 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mrdrnd " } */
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/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)eax" } } */
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/* { dg-final { scan-assembler "jnc\[ \t]+" } } */
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/* { dg-options "-O2 -mrdrnd -dp" } */
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/* { dg-final { scan-assembler-times "rdrandsi_1" 1 } } */
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/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
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#include <immintrin.h>
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unsigned int
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read_rdrand32 (void)
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int
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foo (unsigned int *x)
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{
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return _rdrand_u32 ();
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return _rdrand32_step (x);
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}
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@ -1,13 +1,13 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target lp64 } */
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/* { dg-options "-O2 -mrdrnd " } */
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/* { dg-final { scan-assembler "rdrand\[ \t]+(%|)rax" } } */
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/* { dg-final { scan-assembler "jnc\[ \t]+" } } */
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/* { dg-options "-O2 -mrdrnd -dp" } */
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/* { dg-final { scan-assembler-times "rdranddi_1" 1 } } */
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/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
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#include <immintrin.h>
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unsigned long long
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read_rdrand64 (void)
|
||||
int
|
||||
foo (unsigned long long *x)
|
||||
{
|
||||
return _rdrand_u64 ();
|
||||
return _rdrand64_step (x);
|
||||
}
|
||||
|
Loading…
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Reference in New Issue
Block a user