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alpha.md (extzv): Don't reject register operands.

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* alpha.md (extzv): Don't reject register operands.  Fix
mode of operand 1.

From-SVN: r18676
This commit is contained in:
Richard Henderson 1998-03-18 08:21:14 -08:00 committed by Richard Henderson
parent 99d1a24c9b
commit 10a2523226
2 changed files with 18 additions and 14 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
Wed Mar 18 16:20:30 1998 Richard Henderson <rth@cygnus.com>
* alpha.md (extzv): Don't reject register operands. Fix
mode of operand 1.
Wed Mar 18 16:14:23 1998 Richard Henderson <rth@cygnus.com>
* dbxout.c (dbxout_function_end): Fix last change. The correct

27
gcc/config/alpha/alpha.md
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@ -4873,28 +4873,27 @@
(define_expand "extzv"
[(set (match_operand:DI 0 "register_operand" "")
(zero_extract:DI (match_operand:QI 1 "memory_operand" "")
(zero_extract:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")
(match_operand:DI 3 "immediate_operand" "")))]
""
"
{
/* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
if (INTVAL (operands[3]) % 8 != 0
|| (INTVAL (operands[2]) != 16
&& INTVAL (operands[2]) != 32
&& INTVAL (operands[2]) != 64))
/* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
if (INTVAL (operands[2]) % 8 != 0 || INTVAL (operands[3]) % 8 != 0)
FAIL;
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
if (GET_CODE (operands[1]) != MEM)
FAIL;
if (GET_CODE (operands[1]) == MEM)
{
/* Fail 8 bit fields, falling back on a simple byte load. */
if (INTVAL (operands[2]) == 8)
FAIL;
alpha_expand_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]) / 8,
INTVAL (operands[3]) / 8, 0);
DONE;
alpha_expand_unaligned_load (operands[0], operands[1],
INTVAL (operands[2]) / 8,
INTVAL (operands[3]) / 8, 0);
DONE;
}
}")
(define_expand "insv"