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re PR middle-end/17886 (variable rotate and unsigned long long rotate should be better optimized)
PR 17886 * expmed.c (expand_shift): Move logic to reverse rotation direction when rotating by constants ... * optabs.c (expand_binop): ... here. * config/i386/i386.md (rotrdi3): Handle 32-bit mode. (ix86_rotrdi3): New pattern. (rotldi3): Handle 32-bit mode. (ix86_rotldi3): New pattern. From-SVN: r104761
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Mark Mitchell
Mark Mitchell
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@ -1,3 +1,14 @@
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2005-09-28 Mark Mitchell <mark@codesourcery.com>
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PR 17886
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* expmed.c (expand_shift): Move logic to reverse rotation
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direction when rotating by constants ...
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* optabs.c (expand_binop): ... here.
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* config/i386/i386.md (rotrdi3): Handle 32-bit mode.
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(ix86_rotrdi3): New pattern.
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(rotldi3): Handle 32-bit mode.
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(ix86_rotldi3): New pattern.
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2005-09-29 Alan Modra <amodra@bigpond.net.au>
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PR target/24102
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@ -12004,13 +12004,49 @@
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;; Rotate instructions
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(define_expand "rotldi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
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[(set (match_operand:DI 0 "shiftdi_operand" "")
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(rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
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(match_operand:QI 2 "nonmemory_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
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""
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{
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if (TARGET_64BIT)
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{
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ix86_expand_binary_operator (ROTATE, DImode, operands);
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DONE;
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}
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if (!const_1_to_31_operand (operands[2], VOIDmode))
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FAIL;
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emit_insn (gen_ix86_rotldi3 (operands[0], operands[1], operands[2]));
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DONE;
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})
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;; Implement rotation using two double-precision shift instructions
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;; and a scratch register.
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(define_insn_and_split "ix86_rotldi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(rotate:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:QI 2 "const_1_to_31_operand" "I")))
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(clobber (reg:CC FLAGS_REG))
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(clobber (match_scratch:SI 3 "=&r"))]
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"!TARGET_64BIT"
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""
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"&& reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(parallel
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[(set (match_dup 4)
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(ior:SI (ashift:SI (match_dup 4) (match_dup 2))
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(lshiftrt:SI (match_dup 5)
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(minus:QI (const_int 32) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 5)
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(ior:SI (ashift:SI (match_dup 5) (match_dup 2))
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(lshiftrt:SI (match_dup 3)
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(minus:QI (const_int 32) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])]
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"split_di (operands, 1, operands + 4, operands + 5);")
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(define_insn "*rotlsi3_1_one_bit_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
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@ -12192,12 +12228,48 @@
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(set_attr "mode" "QI")])
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(define_expand "rotrdi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
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(match_operand:QI 2 "nonmemory_operand" "")))
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[(set (match_operand:DI 0 "shiftdi_operand" "")
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(rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
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(match_operand:QI 2 "nonmemory_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
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""
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{
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if (TARGET_64BIT)
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{
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ix86_expand_binary_operator (ROTATERT, DImode, operands);
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DONE;
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}
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if (!const_1_to_31_operand (operands[2], VOIDmode))
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FAIL;
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emit_insn (gen_ix86_rotrdi3 (operands[0], operands[1], operands[2]));
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DONE;
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})
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;; Implement rotation using two double-precision shift instructions
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;; and a scratch register.
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(define_insn_and_split "ix86_rotrdi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(rotatert:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:QI 2 "const_1_to_31_operand" "I")))
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(clobber (reg:CC FLAGS_REG))
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(clobber (match_scratch:SI 3 "=&r"))]
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"!TARGET_64BIT"
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""
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"&& reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(parallel
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[(set (match_dup 4)
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(ior:SI (ashiftrt:SI (match_dup 4) (match_dup 2))
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(ashift:SI (match_dup 5)
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(minus:QI (const_int 32) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (match_dup 5)
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(ior:SI (ashiftrt:SI (match_dup 5) (match_dup 2))
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(ashift:SI (match_dup 3)
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(minus:QI (const_int 32) (match_dup 2)))))
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(clobber (reg:CC FLAGS_REG))])]
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"split_di (operands, 1, operands + 4, operands + 5);")
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(define_insn "*rotrdi3_1_one_bit_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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13
gcc/expmed.c
13
gcc/expmed.c
@ -2237,19 +2237,6 @@ expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
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temp = expand_binop (mode,
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left ? rotl_optab : rotr_optab,
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shifted, op1, target, unsignedp, methods);
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/* If we don't have the rotate, but we are rotating by a constant
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that is in range, try a rotate in the opposite direction. */
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if (temp == 0 && GET_CODE (op1) == CONST_INT
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&& INTVAL (op1) > 0
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&& (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
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temp = expand_binop (mode,
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left ? rotr_optab : rotl_optab,
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shifted,
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GEN_INT (GET_MODE_BITSIZE (mode)
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- INTVAL (op1)),
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target, unsignedp, methods);
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}
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else if (unsignedp)
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temp = expand_binop (mode,
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19
gcc/optabs.c
19
gcc/optabs.c
@ -1049,6 +1049,7 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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|| binoptab->code == ROTATERT);
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rtx entry_last = get_last_insn ();
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rtx last;
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bool first_pass_p;
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class = GET_MODE_CLASS (mode);
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@ -1098,6 +1099,8 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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}
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}
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retry:
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/* If we can do it with a three-operand insn, do so. */
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if (methods != OPTAB_MUST_WIDEN
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@ -1183,6 +1186,22 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
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delete_insns_since (last);
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}
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/* If we were trying to rotate by a constant value, and that didn't
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work, try rotating the other direction before falling back to
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shifts and bitwise-or. */
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if (first_pass_p
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&& (binoptab == rotl_optab || binoptab == rotr_optab)
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&& class == MODE_INT
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&& GET_CODE (op1) == CONST_INT
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&& INTVAL (op1) > 0
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&& (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode))
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{
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first_pass_p = false;
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op1 = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1));
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binoptab = binoptab == rotl_optab ? rotr_optab : rotl_optab;
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goto retry;
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}
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/* If this is a multiply, see if we can do a widening operation that
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takes operands of this mode and makes a wider mode. */
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