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pdp11.md: Change length attribute to be in bytes.
* config/pdp11/pdp11.md: Change length attribute to be in bytes. * config/pdp11/pdp11.c (output_jump): Ditto. From-SVN: r165902
This commit is contained in:
Paul Koning
Paul Koning
parent
a5cd07463d
commit
0f237806af
@ -1,3 +1,8 @@
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2010-10-24 Paul Koning <ni1d@arrl.net>
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* config/pdp11/pdp11.md: Change length attribute to be in bytes.
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* config/pdp11/pdp11.c (output_jump): Ditto.
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2010-10-24 Ian Lance Taylor <iant@google.com>
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* config/i386/i386.c (ix86_va_start): Remove extraneous blank
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@ -1222,13 +1222,13 @@ output_jump (enum rtx_code code, int inv, int length)
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switch (length)
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{
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case 1:
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case 2:
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sprintf(buf, "%s %%l1", inv ? neg : pos);
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return buf;
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case 3:
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case 6:
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sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x);
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@ -64,15 +64,16 @@
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;; default is arith
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(define_attr "type" "unknown,arith,fp" (const_string "arith"))
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;; length default is 1 word each
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(define_attr "length" "" (const_int 1))
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;; length default is 2 bytes each
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(define_attr "length" "" (const_int 2))
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;; a user's asm statement
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(define_asm_attributes
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[(set_attr "type" "unknown")
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; all bets are off how long it is - make it 256, forces long jumps
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; whenever jumping around it !!!
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(set_attr "length" "256")])
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; length for asm is the max length per statement. That would be
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; 5 words, for a floating point instruction with a literal constant
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; argument.
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(set_attr "length" "10")])
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;; define function units
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@ -97,7 +98,7 @@
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else
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return \"{cmpd|cmpf} %0, %1\;cfcc\";
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}"
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[(set_attr "length" "2,2,3,3,6")])
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[(set_attr "length" "4,4,6,6,12")])
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(define_insn "*cmphi"
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[(set (cc0)
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@ -111,7 +112,7 @@
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tst %0
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cmp %0,%1
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cmp %0,%1"
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[(set_attr "length" "1,1,2,2,2,3")])
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[(set_attr "length" "2,2,4,4,4,6")])
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(define_insn "*cmpqi"
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[(set (cc0)
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@ -125,7 +126,7 @@
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tstb %0
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cmpb %0,%1
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cmpb %0,%1"
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[(set_attr "length" "1,1,2,2,2,3")])
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[(set_attr "length" "2,2,4,4,4,6")])
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;; sob instruction - we need an assembler which can make this instruction
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@ -148,7 +149,7 @@
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static int labelcount = 0;
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static char buf[1000];
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if (get_attr_length (insn) == 1)
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if (get_attr_length (insn) == 2)
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return \"sob %0, %l1\";
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/* emulate sob */
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@ -170,8 +171,8 @@
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(ge (minus (match_dup 0)
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(pc))
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(const_int 0)))
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(const_int 4)
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(const_int 1)))])
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(const_int 8)
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(const_int 2)))])
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;; These control RTL generation for conditional jump insns
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;; and match them for register allocation.
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@ -229,12 +230,12 @@
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"* return output_jump(GET_CODE (operands[0]), 0, get_attr_length(insn));"
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[(set (attr "length") (if_then_else (ior (le (minus (match_dup 1)
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(pc))
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(const_int -128))
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(const_int -256))
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(ge (minus (match_dup 1)
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(pc))
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(const_int 128)))
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(const_int 3)
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(const_int 1)))])
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(const_int 256)))
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(const_int 6)
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(const_int 2)))])
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;; These match inverted jump insns for register allocation.
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@ -249,12 +250,12 @@
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"* return output_jump(GET_CODE (operands[0]), 1, get_attr_length(insn));"
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[(set (attr "length") (if_then_else (ior (le (minus (match_dup 1)
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(pc))
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(const_int -128))
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(const_int -256))
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(ge (minus (match_dup 1)
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(pc))
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(const_int 128)))
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(const_int 3)
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(const_int 1)))])
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(const_int 256)))
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(const_int 6)
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(const_int 2)))])
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;; Move instructions
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@ -264,7 +265,7 @@
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""
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"* return output_move_quad (operands);"
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;; what's the mose expensive code - say twice movsi = 16
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[(set_attr "length" "16,16,16")])
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[(set_attr "length" "32,32,32")])
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(define_insn "movsi"
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[(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m")
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@ -273,7 +274,7 @@
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"* return output_move_double (operands);"
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;; what's the most expensive code ? - I think 8!
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;; we could split it up and make several sub-cases...
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[(set_attr "length" "2,3,4,8,8")])
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[(set_attr "length" "4,6,8,16,16")])
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(define_insn "movhi"
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[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
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@ -286,11 +287,11 @@
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return \"mov %1, %0\";
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}"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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(define_insn "movqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=g")
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(match_operand:QI 1 "general_operand" "g"))]
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[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
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(match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
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""
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"*
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{
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@ -299,7 +300,7 @@
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return \"movb %1, %0\";
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}"
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[(set_attr "length" "1")])
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[(set_attr "length" "2,4,4,6")])
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;; do we have to supply all these moves? e.g. to
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;; NO_LOAD_FPU_REGs ?
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@ -314,14 +315,14 @@
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else
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return output_move_quad (operands); "
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;; just a guess..
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[(set_attr "length" "1,1,5,5,16")])
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[(set_attr "length" "2,2,10,10,32")])
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(define_insn "movsf"
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[(set (match_operand:SF 0 "general_operand" "=g,r,g")
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(match_operand:SF 1 "general_operand" "r,rmF,g"))]
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"TARGET_FPU"
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"* return output_move_double (operands);"
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[(set_attr "length" "8,8,8")])
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[(set_attr "length" "16,16,16")])
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;; maybe fiddle a bit with move_ratio, then
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;; let constraints only accept a register ...
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@ -362,7 +363,7 @@
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"(TARGET_BCOPY_BUILTIN)"
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"* return output_block_move (operands);"
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;;; just a guess
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[(set_attr "length" "40")])
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[(set_attr "length" "80")])
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@ -385,7 +386,7 @@
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else
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return \"{stcdf|movfo} %1, %0\";
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"
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[(set_attr "length" "3,1,2")])
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[(set_attr "length" "6,2,4")])
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(define_expand "truncsihi2"
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@ -400,11 +401,11 @@
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;;- zero extension instructions
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "general_operand" "=r")
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(zero_extend:HI (match_operand:QI 1 "general_operand" "0")))]
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[(set (match_operand:HI 0 "general_operand" "=rR,Q")
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(zero_extend:HI (match_operand:QI 1 "general_operand" "0,0")))]
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""
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"bic $0177400, %0"
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[(set_attr "length" "2")])
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[(set_attr "length" "4,6")])
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(define_expand "zero_extendhisi2"
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[(set (subreg:HI
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@ -429,7 +430,7 @@
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mov %1, -(sp)\;{ldcfd|movof} (sp)+,%0
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{ldcfd|movof} %1, %0
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{ldcfd|movof} %1, %0"
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[(set_attr "length" "2,1,2")])
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[(set_attr "length" "4,2,4")])
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;; does movb sign extend in register-to-register move?
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(define_insn "extendqihi2"
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@ -437,7 +438,7 @@
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(sign_extend:HI (match_operand:QI 1 "general_operand" "rR,Q")))]
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""
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"movb %1, %0"
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[(set_attr "length" "1,2")])
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[(set_attr "length" "2,4")])
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(define_insn "extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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@ -456,7 +457,7 @@
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return \"\";
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}"
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[(set_attr "length" "2,3")])
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[(set_attr "length" "4,6")])
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;; maybe we have to use define_expand to say that we have the instruction,
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;; unconditionally, and then match dependent on CPU type:
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@ -513,7 +514,7 @@
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gcc_unreachable ();
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}
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}"
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[(set_attr "length" "5,3,3")])
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[(set_attr "length" "10,6,6")])
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(define_insn ""
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@ -545,7 +546,7 @@
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return \"\";
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}"
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[(set_attr "length" "6")])
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[(set_attr "length" "12")])
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;; make float to int and vice versa
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;; using the cc_status.flag field we could probably cut down
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@ -576,14 +577,14 @@
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else
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return \"setl\;{ldcld|movif} %1, %0\;seti\";
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"
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[(set_attr "length" "5,3,4")])
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[(set_attr "length" "10,6,8")])
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(define_insn "floathidf2"
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[(set (match_operand:DF 0 "register_operand" "=a,a")
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(float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))]
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"TARGET_FPU"
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"{ldcid|movif} %1, %0"
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[(set_attr "length" "1,2")])
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[(set_attr "length" "2,4")])
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;; cut float to int
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(define_insn "fix_truncdfsi2"
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@ -605,14 +606,14 @@
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else
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return \"setl\;{stcdl|movfi} %1, %0\;seti\";
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"
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[(set_attr "length" "5,3,4")])
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[(set_attr "length" "10,6,8")])
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(define_insn "fix_truncdfhi2"
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[(set (match_operand:HI 0 "general_operand" "=rR,Q")
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(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))]
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"TARGET_FPU"
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"{stcdi|movfi} %1, %0"
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[(set_attr "length" "1,2")])
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[(set_attr "length" "2,4")])
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;;- arithmetic instructions
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@ -624,7 +625,7 @@
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(match_operand:DF 2 "general_operand" "fR,Q,F")))]
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"TARGET_FPU"
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"{addd|addf} %2, %0"
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[(set_attr "length" "1,2,5")])
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[(set_attr "length" "2,4,10")])
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
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@ -674,7 +675,7 @@
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return \"\";
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}"
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[(set_attr "length" "3,5,6,8,3,1,5,5,3,8")])
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[(set_attr "length" "6,10,12,16,6,2,10,10,6,16")])
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(define_insn "addhi3"
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[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
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@ -693,7 +694,7 @@
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return \"add %2, %0\";
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}"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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(define_insn "addqi3"
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[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
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@ -712,7 +713,7 @@
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return \"add %2, %0\";
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}"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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;;- subtract instructions
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@ -726,7 +727,7 @@
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(match_operand:DF 2 "general_operand" "fR,Q")))]
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"TARGET_FPU"
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"{subd|subf} %2, %0"
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[(set_attr "length" "1,2")])
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[(set_attr "length" "2,4")])
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "general_operand" "=r,r,o,o")
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@ -760,7 +761,7 @@
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return \"\";
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}"
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;; offsettable memory addresses always are expensive!!!
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[(set_attr "length" "3,5,6,8")])
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[(set_attr "length" "6,10,12,16")])
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(define_insn "subhi3"
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[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
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@ -773,7 +774,7 @@
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return \"sub %2, %0\";
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}"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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(define_insn "subqi3"
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[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
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@ -786,7 +787,7 @@
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return \"sub %2, %0\";
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}"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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;;;;- and instructions
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;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn.
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@ -837,7 +838,7 @@
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return \"\";
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}"
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[(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
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[(set_attr "length" "4,8,8,12,4,4,8,6,6,12")])
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(define_insn "andhi3"
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[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
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@ -845,7 +846,7 @@
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(not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))]
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""
|
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"bic %2, %0"
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[(set_attr "length" "1,2,2,3")])
|
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[(set_attr "length" "2,4,4,6")])
|
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|
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(define_insn "andqi3"
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[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
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@ -853,7 +854,7 @@
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(not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))]
|
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""
|
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"bicb %2, %0"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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|
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;;- Bit set (inclusive or) instructions
|
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(define_insn "iorsi3"
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@ -902,7 +903,7 @@
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return \"\";
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}"
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[(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
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[(set_attr "length" "4,8,8,12,4,4,8,6,6,12")])
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(define_insn "iorhi3"
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[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
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@ -910,7 +911,7 @@
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(match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
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""
|
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"bis %2, %0"
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[(set_attr "length" "1,2,2,3")])
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[(set_attr "length" "2,4,4,6")])
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|
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(define_insn "iorqi3"
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[(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
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@ -945,7 +946,7 @@
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}
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}"
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[(set_attr "length" "2")])
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[(set_attr "length" "4")])
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|
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(define_insn "xorhi3"
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[(set (match_operand:HI 0 "general_operand" "=rR,Q")
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@ -953,7 +954,7 @@
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(match_operand:HI 2 "register_operand" "r,r")))]
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"TARGET_40_PLUS"
|
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"xor %2, %0"
|
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[(set_attr "length" "1,2")])
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[(set_attr "length" "2,4")])
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|
||||
;;- one complement instructions
|
||||
|
||||
@ -962,7 +963,7 @@
|
||||
(not:HI (match_operand:HI 1 "general_operand" "0,0")))]
|
||||
""
|
||||
"com %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
(define_insn "one_cmplqi2"
|
||||
[(set (match_operand:QI 0 "general_operand" "=rR,rR")
|
||||
@ -971,7 +972,7 @@
|
||||
"@
|
||||
comb %0
|
||||
movb %1, %0\; comb %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;;- arithmetic shift instructions
|
||||
(define_insn "ashlsi3"
|
||||
@ -980,7 +981,7 @@
|
||||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||||
"TARGET_40_PLUS"
|
||||
"ashc %2,%0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;; Arithmetic right shift on the pdp works by negating the shift count.
|
||||
(define_expand "ashrsi3"
|
||||
@ -1002,7 +1003,7 @@
|
||||
(const_int 1)))]
|
||||
""
|
||||
"asl %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;; and another possibility for asr is << -1
|
||||
;; might cause problems since -1 can also be encoded as 65535!
|
||||
@ -1015,7 +1016,7 @@
|
||||
(const_int -1)))]
|
||||
""
|
||||
"asr %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;; lsr
|
||||
(define_insn ""
|
||||
@ -1024,7 +1025,7 @@
|
||||
(const_int 1)))]
|
||||
""
|
||||
"clc\;ror %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
@ -1047,7 +1048,7 @@
|
||||
|
||||
return \"\";
|
||||
}
|
||||
[(set_attr "length" "5")])
|
||||
[(set_attr "length" "10")])
|
||||
|
||||
;; shift is by arbitrary count is expensive,
|
||||
;; shift by one cheap - so let's do that, if
|
||||
@ -1070,7 +1071,7 @@
|
||||
return \"\";
|
||||
}"
|
||||
;; longest is 4
|
||||
[(set (attr "length") (const_int 4))])
|
||||
[(set (attr "length") (const_int 8))])
|
||||
|
||||
;; aslb
|
||||
(define_insn ""
|
||||
@ -1091,8 +1092,8 @@
|
||||
}"
|
||||
;; set attribute length ( match_dup 2 & 7 ) *(1 or 2) !!!
|
||||
[(set_attr_alternative "length"
|
||||
[(const_int 7)
|
||||
(const_int 14)])])
|
||||
[(const_int 14)
|
||||
(const_int 28)])])
|
||||
|
||||
;;; asr
|
||||
;(define_insn ""
|
||||
@ -1101,7 +1102,7 @@
|
||||
; (const_int 1)))]
|
||||
; ""
|
||||
; "asr %0"
|
||||
; [(set_attr "length" "1,2")])
|
||||
; [(set_attr "length" "2,4")])
|
||||
|
||||
;; asrb
|
||||
(define_insn ""
|
||||
@ -1121,14 +1122,14 @@
|
||||
return \"\";
|
||||
}"
|
||||
[(set_attr_alternative "length"
|
||||
[(const_int 7)
|
||||
(const_int 14)])])
|
||||
[(const_int 14)
|
||||
(const_int 28)])])
|
||||
|
||||
;; the following is invalid - too complex!!! - just say 14 !!!
|
||||
; [(set (attr "length") (plus (and (match_dup 2)
|
||||
; (const_int 7))
|
||||
; (const_int 14))
|
||||
; (and (match_dup 2)
|
||||
; (const_int 7))))])
|
||||
; (const_int 14))))])
|
||||
|
||||
|
||||
|
||||
@ -1152,7 +1153,7 @@
|
||||
|
||||
return \"ash %2,%0\";
|
||||
}"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;; Arithmetic right shift on the pdp works by negating the shift count.
|
||||
(define_expand "ashrhi3"
|
||||
@ -1180,7 +1181,7 @@
|
||||
(abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
|
||||
"TARGET_FPU"
|
||||
"{absd|absf} %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
(define_insn "abshi2"
|
||||
[(set (match_operand:HI 0 "general_operand" "=r,o")
|
||||
@ -1200,7 +1201,7 @@
|
||||
|
||||
return \"\";
|
||||
}"
|
||||
[(set_attr "length" "3,5")])
|
||||
[(set_attr "length" "6,10")])
|
||||
|
||||
|
||||
;; define expand abshi - is much better !!! - but
|
||||
@ -1244,7 +1245,7 @@
|
||||
(neg:DF (match_operand:DF 1 "register_operand" "0,0")))]
|
||||
"TARGET_FPU"
|
||||
"{negd|negf} %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
(define_insn "negsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
@ -1267,21 +1268,21 @@
|
||||
|
||||
return \"\";
|
||||
}
|
||||
[(set_attr "length" "5")])
|
||||
[(set_attr "length" "10")])
|
||||
|
||||
(define_insn "neghi2"
|
||||
[(set (match_operand:HI 0 "general_operand" "=rR,Q")
|
||||
(neg:HI (match_operand:HI 1 "general_operand" "0,0")))]
|
||||
""
|
||||
"neg %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
(define_insn "negqi2"
|
||||
[(set (match_operand:QI 0 "general_operand" "=rR,Q")
|
||||
(neg:QI (match_operand:QI 1 "general_operand" "0,0")))]
|
||||
""
|
||||
"negb %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
|
||||
;; Unconditional and other jump instructions
|
||||
@ -1289,8 +1290,20 @@
|
||||
[(set (pc)
|
||||
(label_ref (match_operand 0 "" "")))]
|
||||
""
|
||||
"jmp %l0"
|
||||
[(set_attr "length" "2")])
|
||||
"*
|
||||
{
|
||||
if (get_attr_length (insn) == 2)
|
||||
return \"br %l0\";
|
||||
return \"jmp %l0\";
|
||||
}"
|
||||
[(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
|
||||
(pc))
|
||||
(const_int -256))
|
||||
(ge (minus (match_dup 0)
|
||||
(pc))
|
||||
(const_int 256)))
|
||||
(const_int 4)
|
||||
(const_int 2)))])
|
||||
|
||||
(define_insn ""
|
||||
[(set (pc)
|
||||
@ -1298,14 +1311,14 @@
|
||||
(clobber (const_int 1))]
|
||||
""
|
||||
"jmp %l0"
|
||||
[(set_attr "length" "2")])
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
(define_insn "tablejump"
|
||||
[(set (pc) (match_operand:HI 0 "general_operand" "rR,Q"))
|
||||
(use (label_ref (match_operand 1 "" "")))]
|
||||
""
|
||||
"jmp %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;; indirect jump - let's be conservative!
|
||||
;; allow only register_operand, even though we could also
|
||||
@ -1326,7 +1339,7 @@
|
||||
;;- Don't use operand 1 for most machines.
|
||||
""
|
||||
"jsr pc, %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;;- jump to subroutine
|
||||
(define_insn "call_value"
|
||||
@ -1338,7 +1351,7 @@
|
||||
;;- Don't use operand 2 for most machines.
|
||||
""
|
||||
"jsr pc, %1"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;;- nop instruction
|
||||
(define_insn "nop"
|
||||
@ -1355,7 +1368,7 @@
|
||||
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
|
||||
"TARGET_FPU"
|
||||
"{muld|mulf} %2, %0"
|
||||
[(set_attr "length" "1,2,5")])
|
||||
[(set_attr "length" "2,4,10")])
|
||||
|
||||
;; 16 bit result multiply:
|
||||
;; currently we multiply only into odd registers, so we don't use two
|
||||
@ -1369,7 +1382,7 @@
|
||||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||||
"TARGET_40_PLUS"
|
||||
"mul %2, %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;; 32 bit result
|
||||
(define_expand "mulhisi3"
|
||||
@ -1389,7 +1402,7 @@
|
||||
(match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||||
"TARGET_40_PLUS"
|
||||
"mul %2, %0"
|
||||
[(set_attr "length" "1,2")])
|
||||
[(set_attr "length" "2,4")])
|
||||
|
||||
;(define_insn "mulhisi3"
|
||||
; [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
|
||||
@ -1398,7 +1411,7 @@
|
||||
; (match_operand:HI 2 "general_operand" "rR,Qi")))]
|
||||
; "TARGET_40_PLUS"
|
||||
; "mul %2, %0"
|
||||
; [(set_attr "length" "1,2")])
|
||||
; [(set_attr "length" "2,4")])
|
||||
|
||||
;;- divide
|
||||
(define_insn "divdf3"
|
||||
@ -1407,7 +1420,7 @@
|
||||
(match_operand:DF 2 "general_operand" "fR,Q,F")))]
|
||||
"TARGET_FPU"
|
||||
"{divd|divf} %2, %0"
|
||||
[(set_attr "length" "1,2,5")])
|
||||
[(set_attr "length" "2,4,10")])
|
||||
|
||||
|
||||
(define_expand "divhi3"
|
||||
@ -1425,7 +1438,7 @@
|
||||
(match_operand:HI 2 "general_operand" "g")))]
|
||||
"TARGET_40_PLUS"
|
||||
"div %2,%0"
|
||||
[(set_attr "length" "2")])
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
(define_expand "modhi3"
|
||||
[(set (subreg:HI (match_dup 1) 2)
|
||||
@ -1442,7 +1455,7 @@
|
||||
(match_operand:HI 2 "general_operand" "g")))]
|
||||
"TARGET_40_PLUS"
|
||||
"div %2,%0"
|
||||
[(set_attr "length" "2")])
|
||||
[(set_attr "length" "4")])
|
||||
|
||||
;(define_expand "divmodhi4"
|
||||
; [(parallel [(set (subreg:HI (match_dup 1) 0)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user