mirror of
git://gcc.gnu.org/git/gcc.git
synced 2024-12-19 23:19:40 +08:00
rs6000.md: Use predicate altivec_register_operand for altivec_lvx* and altivec_stvx*.
2002-02-12 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md: Use predicate altivec_register_operand
for altivec_lvx* and altivec_stvx*.
("*movv4si_internal"): Add constraint for loading from GPRs.
("*movv8hi_internal1"): Same.
("*movv16qi_internal1"): Same.
("*movv4sf_internal1"): Same.
* config/rs6000/rs6000.c (altivec_register_operand): New.
* config/rs6000/rs6000.h (PREDICATE_CODES): Add
altivec_register_operand.
From-SVN: r49719
This commit is contained in:
Aldy Hernandez
Aldy Hernandez
parent
b007569d7c
commit
0ec4e2a87f
@ -1,3 +1,17 @@
|
||||
2002-02-12 Aldy Hernandez <aldyh@redhat.com>
|
||||
|
||||
* config/rs6000/rs6000.md: Use predicate altivec_register_operand
|
||||
for altivec_lvx* and altivec_stvx*.
|
||||
("*movv4si_internal"): Add constraint for loading from GPRs.
|
||||
("*movv8hi_internal1"): Same.
|
||||
("*movv16qi_internal1"): Same.
|
||||
("*movv4sf_internal1"): Same.
|
||||
|
||||
* config/rs6000/rs6000.c (altivec_register_operand): New.
|
||||
|
||||
* config/rs6000/rs6000.h (PREDICATE_CODES): Add
|
||||
altivec_register_operand.
|
||||
|
||||
2002-02-13 Hans-Peter Nilsson <hp@bitrange.com>
|
||||
|
||||
* config/mmix/mmix.c (mmix_assemble_integer) <case 4>: Don't
|
||||
|
||||
@ -710,6 +710,19 @@ count_register_operand (op, mode)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Returns 1 if op is an altivec register. */
|
||||
int
|
||||
altivec_register_operand (op, mode)
|
||||
rtx op;
|
||||
enum machine_mode mode ATTRIBUTE_UNUSED;
|
||||
{
|
||||
|
||||
return (register_operand (op, mode)
|
||||
&& (GET_CODE (op) != REG
|
||||
|| REGNO (op) > FIRST_PSEUDO_REGISTER
|
||||
|| ALTIVEC_REGNO_P (REGNO (op))));
|
||||
}
|
||||
|
||||
int
|
||||
xer_operand (op, mode)
|
||||
rtx op;
|
||||
|
||||
@ -2762,6 +2762,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
|
||||
GT, LEU, LTU, GEU, GTU}}, \
|
||||
{"boolean_operator", {AND, IOR, XOR}}, \
|
||||
{"boolean_or_operator", {IOR, XOR}}, \
|
||||
{"altivec_register_operand", {REG}}, \
|
||||
{"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
|
||||
|
||||
/* uncomment for disabling the corresponding default options */
|
||||
|
||||
@ -13871,28 +13871,28 @@
|
||||
|
||||
;; Generic LVX load instruction.
|
||||
(define_insn "altivec_lvx_4si"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=v")
|
||||
[(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
|
||||
(match_operand:V4SI 1 "memory_operand" "m"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"lvx %0,%y1"
|
||||
[(set_attr "type" "vecload")])
|
||||
|
||||
(define_insn "altivec_lvx_8hi"
|
||||
[(set (match_operand:V8HI 0 "register_operand" "=v")
|
||||
[(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
|
||||
(match_operand:V8HI 1 "memory_operand" "m"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"lvx %0,%y1"
|
||||
[(set_attr "type" "vecload")])
|
||||
|
||||
(define_insn "altivec_lvx_16qi"
|
||||
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
||||
[(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
|
||||
(match_operand:V16QI 1 "memory_operand" "m"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"lvx %0,%y1"
|
||||
[(set_attr "type" "vecload")])
|
||||
|
||||
(define_insn "altivec_lvx_4sf"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
||||
[(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
|
||||
(match_operand:V4SF 1 "memory_operand" "m"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"lvx %0,%y1"
|
||||
@ -13901,28 +13901,28 @@
|
||||
;; Generic STVX store instruction.
|
||||
(define_insn "altivec_stvx_4si"
|
||||
[(set (match_operand:V4SI 0 "memory_operand" "=m")
|
||||
(match_operand:V4SI 1 "register_operand" "v"))]
|
||||
(match_operand:V4SI 1 "altivec_register_operand" "v"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"stvx %1,%y0"
|
||||
[(set_attr "type" "vecstore")])
|
||||
|
||||
(define_insn "altivec_stvx_8hi"
|
||||
[(set (match_operand:V8HI 0 "memory_operand" "=m")
|
||||
(match_operand:V8HI 1 "register_operand" "v"))]
|
||||
(match_operand:V8HI 1 "altivec_register_operand" "v"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"stvx %1,%y0"
|
||||
[(set_attr "type" "vecstore")])
|
||||
|
||||
(define_insn "altivec_stvx_16qi"
|
||||
[(set (match_operand:V16QI 0 "memory_operand" "=m")
|
||||
(match_operand:V16QI 1 "register_operand" "v"))]
|
||||
(match_operand:V16QI 1 "altivec_register_operand" "v"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"stvx %1,%y0"
|
||||
[(set_attr "type" "vecstore")])
|
||||
|
||||
(define_insn "altivec_stvx_4sf"
|
||||
[(set (match_operand:V4SF 0 "memory_operand" "=m")
|
||||
(match_operand:V4SF 1 "register_operand" "v"))]
|
||||
(match_operand:V4SF 1 "altivec_register_operand" "v"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"stvx %1,%y0"
|
||||
[(set_attr "type" "vecstore")])
|
||||
@ -13935,14 +13935,16 @@
|
||||
"{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
|
||||
|
||||
(define_insn "*movv4si_internal"
|
||||
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v")
|
||||
(match_operand:V4SI 1 "input_operand" "v,m,v"))]
|
||||
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,m")
|
||||
(match_operand:V4SI 1 "input_operand" "v,m,v,r"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"@
|
||||
stvx %1,%y0
|
||||
lvx %0,%y1
|
||||
vor %0,%1,%1"
|
||||
[(set_attr "type" "altivec")])
|
||||
vor %0,%1,%1
|
||||
stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0"
|
||||
[(set_attr "type" "altivec")
|
||||
(set_attr "length" "*,*,*,16")])
|
||||
|
||||
(define_expand "movv8hi"
|
||||
[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
|
||||
@ -13951,14 +13953,16 @@
|
||||
"{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
|
||||
|
||||
(define_insn "*movv8hi_internal1"
|
||||
[(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v")
|
||||
(match_operand:V8HI 1 "input_operand" "v,m,v"))]
|
||||
[(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,m")
|
||||
(match_operand:V8HI 1 "input_operand" "v,m,v,r"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"@
|
||||
stvx %1,%y0
|
||||
lvx %0,%y1
|
||||
vor %0,%1,%1"
|
||||
[(set_attr "type" "altivec")])
|
||||
vor %0,%1,%1
|
||||
stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0"
|
||||
[(set_attr "type" "altivec")
|
||||
(set_attr "length" "*,*,*,16")])
|
||||
|
||||
(define_expand "movv16qi"
|
||||
[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
|
||||
@ -13967,14 +13971,16 @@
|
||||
"{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
|
||||
|
||||
(define_insn "*movv16qi_internal1"
|
||||
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v")
|
||||
(match_operand:V16QI 1 "input_operand" "v,m,v"))]
|
||||
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,m")
|
||||
(match_operand:V16QI 1 "input_operand" "v,m,v,r"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"@
|
||||
stvx %1,%y0
|
||||
lvx %0,%y1
|
||||
vor %0,%1,%1"
|
||||
[(set_attr "type" "altivec")])
|
||||
vor %0,%1,%1
|
||||
stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0"
|
||||
[(set_attr "type" "altivec")
|
||||
(set_attr "length" "*,*,*,16")])
|
||||
|
||||
(define_expand "movv4sf"
|
||||
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
|
||||
@ -13983,14 +13989,16 @@
|
||||
"{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
|
||||
|
||||
(define_insn "*movv4sf_internal1"
|
||||
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v")
|
||||
(match_operand:V4SF 1 "input_operand" "v,m,v"))]
|
||||
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,m")
|
||||
(match_operand:V4SF 1 "input_operand" "v,m,v,r"))]
|
||||
"TARGET_ALTIVEC"
|
||||
"@
|
||||
stvx %1,%y0
|
||||
lvx %0,%y1
|
||||
vor %0,%1,%1"
|
||||
[(set_attr "type" "altivec")])
|
||||
vor %0,%1,%1
|
||||
stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0"
|
||||
[(set_attr "type" "altivec")
|
||||
(set_attr "length" "*,*,*,16")])
|
||||
|
||||
(define_insn "*set_vrsave_internal"
|
||||
[(match_parallel 0 "vrsave_operation"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user