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mips.h (PTF_AVOID_BRANCHLIKELY): New macro.
gcc/ * config/mips/mips.h (PTF_AVOID_BRANCHLIKELY): New macro. (mips_cpu_info): Add tune_flags. (GENERATE_BRANCHLIKELY): Remove TARGET_SR71K check. * config/mips/mips.c (mips_cpu_info_table): Add tune_flags fields. Remove end marker. (override_options): Remove deprecation code. Use branch-likely instructions for optimize_size or if the tuning flags do not suggest otherwise. Tweak warning. (mips_matching_cpu_name_p, mips_parse_cpu): Use ARRAY_SIZE. From-SVN: r128848
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
da2ce74a2e
commit
0da4c1ea84
@ -1,3 +1,15 @@
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2007-09-27 Richard Sandiford <rsandifo@nildram.co.uk>
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* config/mips/mips.h (PTF_AVOID_BRANCHLIKELY): New macro.
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(mips_cpu_info): Add tune_flags.
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(GENERATE_BRANCHLIKELY): Remove TARGET_SR71K check.
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* config/mips/mips.c (mips_cpu_info_table): Add tune_flags fields.
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Remove end marker.
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(override_options): Remove deprecation code. Use branch-likely
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instructions for optimize_size or if the tuning flags do not
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suggest otherwise. Tweak warning.
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(mips_matching_cpu_name_p, mips_parse_cpu): Use ARRAY_SIZE.
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2007-09-27 Matthias Klose <doko@ubuntu.com>
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* config/i386/t-linux64 (MULTILIB_OSDIRNAMES): Use ../lib32 as the
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@ -753,94 +753,96 @@ const struct attribute_spec mips_attribute_table[] =
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options correctly. */
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const struct mips_cpu_info mips_cpu_info_table[] = {
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/* Entries for generic ISAs */
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{ "mips1", PROCESSOR_R3000, 1 },
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{ "mips2", PROCESSOR_R6000, 2 },
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{ "mips3", PROCESSOR_R4000, 3 },
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{ "mips4", PROCESSOR_R8000, 4 },
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{ "mips32", PROCESSOR_4KC, 32 },
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{ "mips32r2", PROCESSOR_M4K, 33 },
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{ "mips64", PROCESSOR_5KC, 64 },
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{ "mips1", PROCESSOR_R3000, 1, 0 },
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{ "mips2", PROCESSOR_R6000, 2, 0 },
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{ "mips3", PROCESSOR_R4000, 3, 0 },
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{ "mips4", PROCESSOR_R8000, 4, 0 },
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/* Prefer not to use branch-likely instructions for generic MIPS32rX
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and MIPS64rX code. The instructions were officially deprecated
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in revisions 2 and earlier, but revision 3 is likely to downgrade
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that to a recommendation to avoid the instructions in code that
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isn't tuned to a specific processor. */
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{ "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
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{ "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
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{ "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
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/* MIPS I */
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{ "r3000", PROCESSOR_R3000, 1 },
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{ "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
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{ "r3900", PROCESSOR_R3900, 1 },
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{ "r3000", PROCESSOR_R3000, 1, 0 },
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{ "r2000", PROCESSOR_R3000, 1, 0 }, /* = r3000 */
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{ "r3900", PROCESSOR_R3900, 1, 0 },
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/* MIPS II */
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{ "r6000", PROCESSOR_R6000, 2 },
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{ "r6000", PROCESSOR_R6000, 2, 0 },
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/* MIPS III */
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{ "r4000", PROCESSOR_R4000, 3 },
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{ "vr4100", PROCESSOR_R4100, 3 },
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{ "vr4111", PROCESSOR_R4111, 3 },
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{ "vr4120", PROCESSOR_R4120, 3 },
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{ "vr4130", PROCESSOR_R4130, 3 },
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{ "vr4300", PROCESSOR_R4300, 3 },
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{ "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
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{ "r4600", PROCESSOR_R4600, 3 },
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{ "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
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{ "r4650", PROCESSOR_R4650, 3 },
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{ "r4000", PROCESSOR_R4000, 3, 0 },
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{ "vr4100", PROCESSOR_R4100, 3, 0 },
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{ "vr4111", PROCESSOR_R4111, 3, 0 },
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{ "vr4120", PROCESSOR_R4120, 3, 0 },
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{ "vr4130", PROCESSOR_R4130, 3, 0 },
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{ "vr4300", PROCESSOR_R4300, 3, 0 },
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{ "r4400", PROCESSOR_R4000, 3, 0 }, /* = r4000 */
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{ "r4600", PROCESSOR_R4600, 3, 0 },
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{ "orion", PROCESSOR_R4600, 3, 0 }, /* = r4600 */
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{ "r4650", PROCESSOR_R4650, 3, 0 },
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/* MIPS IV */
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{ "r8000", PROCESSOR_R8000, 4 },
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{ "vr5000", PROCESSOR_R5000, 4 },
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{ "vr5400", PROCESSOR_R5400, 4 },
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{ "vr5500", PROCESSOR_R5500, 4 },
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{ "rm7000", PROCESSOR_R7000, 4 },
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{ "rm9000", PROCESSOR_R9000, 4 },
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{ "r8000", PROCESSOR_R8000, 4, 0 },
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{ "vr5000", PROCESSOR_R5000, 4, 0 },
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{ "vr5400", PROCESSOR_R5400, 4, 0 },
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{ "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
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{ "rm7000", PROCESSOR_R7000, 4, 0 },
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{ "rm9000", PROCESSOR_R9000, 4, 0 },
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/* MIPS32 */
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{ "4kc", PROCESSOR_4KC, 32 },
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{ "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
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{ "4kp", PROCESSOR_4KP, 32 },
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{ "4ksc", PROCESSOR_4KC, 32 },
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{ "4kc", PROCESSOR_4KC, 32, 0 },
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{ "4km", PROCESSOR_4KC, 32, 0 }, /* = 4kc */
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{ "4kp", PROCESSOR_4KP, 32, 0 },
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{ "4ksc", PROCESSOR_4KC, 32, 0 },
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/* MIPS32 Release 2 */
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{ "m4k", PROCESSOR_M4K, 33 },
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{ "4kec", PROCESSOR_4KC, 33 },
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{ "4kem", PROCESSOR_4KC, 33 },
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{ "4kep", PROCESSOR_4KP, 33 },
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{ "4ksd", PROCESSOR_4KC, 33 },
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{ "m4k", PROCESSOR_M4K, 33, 0 },
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{ "4kec", PROCESSOR_4KC, 33, 0 },
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{ "4kem", PROCESSOR_4KC, 33, 0 },
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{ "4kep", PROCESSOR_4KP, 33, 0 },
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{ "4ksd", PROCESSOR_4KC, 33, 0 },
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{ "24kc", PROCESSOR_24KC, 33 },
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{ "24kf2_1", PROCESSOR_24KF2_1, 33 },
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{ "24kf", PROCESSOR_24KF2_1, 33 },
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{ "24kf1_1", PROCESSOR_24KF1_1, 33 },
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{ "24kfx", PROCESSOR_24KF1_1, 33 },
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{ "24kx", PROCESSOR_24KF1_1, 33 },
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{ "24kc", PROCESSOR_24KC, 33, 0 },
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{ "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
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{ "24kf", PROCESSOR_24KF2_1, 33, 0 },
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{ "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
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{ "24kfx", PROCESSOR_24KF1_1, 33, 0 },
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{ "24kx", PROCESSOR_24KF1_1, 33, 0 },
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{ "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
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{ "24kef2_1", PROCESSOR_24KF2_1, 33 },
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{ "24kef", PROCESSOR_24KF2_1, 33 },
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{ "24kef1_1", PROCESSOR_24KF1_1, 33 },
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{ "24kefx", PROCESSOR_24KF1_1, 33 },
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{ "24kex", PROCESSOR_24KF1_1, 33 },
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{ "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP */
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{ "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
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{ "24kef", PROCESSOR_24KF2_1, 33, 0 },
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{ "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
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{ "24kefx", PROCESSOR_24KF1_1, 33, 0 },
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{ "24kex", PROCESSOR_24KF1_1, 33, 0 },
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{ "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
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{ "34kf2_1", PROCESSOR_24KF2_1, 33 },
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{ "34kf", PROCESSOR_24KF2_1, 33 },
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{ "34kf1_1", PROCESSOR_24KF1_1, 33 },
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{ "34kfx", PROCESSOR_24KF1_1, 33 },
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{ "34kx", PROCESSOR_24KF1_1, 33 },
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{ "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP */
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{ "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
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{ "34kf", PROCESSOR_24KF2_1, 33, 0 },
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{ "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
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{ "34kfx", PROCESSOR_24KF1_1, 33, 0 },
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{ "34kx", PROCESSOR_24KF1_1, 33, 0 },
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{ "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
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{ "74kf2_1", PROCESSOR_74KF2_1, 33 },
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{ "74kf", PROCESSOR_74KF2_1, 33 },
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{ "74kf1_1", PROCESSOR_74KF1_1, 33 },
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{ "74kfx", PROCESSOR_74KF1_1, 33 },
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{ "74kx", PROCESSOR_74KF1_1, 33 },
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{ "74kf3_2", PROCESSOR_74KF3_2, 33 },
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{ "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2 */
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{ "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
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{ "74kf", PROCESSOR_74KF2_1, 33, 0 },
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{ "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
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{ "74kfx", PROCESSOR_74KF1_1, 33, 0 },
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{ "74kx", PROCESSOR_74KF1_1, 33, 0 },
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{ "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
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/* MIPS64 */
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{ "5kc", PROCESSOR_5KC, 64 },
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{ "5kf", PROCESSOR_5KF, 64 },
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{ "20kc", PROCESSOR_20KC, 64 },
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{ "sb1", PROCESSOR_SB1, 64 },
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{ "sb1a", PROCESSOR_SB1A, 64 },
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{ "sr71000", PROCESSOR_SR71000, 64 },
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/* End marker */
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{ 0, 0, 0 }
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{ "5kc", PROCESSOR_5KC, 64, 0 },
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{ "5kf", PROCESSOR_5KF, 64, 0 },
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{ "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
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{ "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
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{ "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
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{ "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
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};
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/* Default costs. If these are used for a processor we should look
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@ -6042,29 +6044,19 @@ override_options (void)
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{
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/* If neither -mbranch-likely nor -mno-branch-likely was given
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on the command line, set MASK_BRANCHLIKELY based on the target
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architecture.
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By default, we enable use of Branch Likely instructions on
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all architectures which support them with the following
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exceptions: when creating MIPS32 or MIPS64 code, and when
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tuning for architectures where their use tends to hurt
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performance.
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The MIPS32 and MIPS64 architecture specifications say "Software
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is strongly encouraged to avoid use of Branch Likely
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instructions, as they will be removed from a future revision
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of the [MIPS32 and MIPS64] architecture." Therefore, we do not
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issue those instructions unless instructed to do so by
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-mbranch-likely. */
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architecture and tuning flags. Annulled delay slots are a
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size win, so we only consider the process-specific tuning
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for !optimize_size. */
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if (ISA_HAS_BRANCHLIKELY
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&& !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
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&& !(TUNE_MIPS5500 || TUNE_SB1))
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&& (optimize_size
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|| (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
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target_flags |= MASK_BRANCHLIKELY;
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else
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target_flags &= ~MASK_BRANCHLIKELY;
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}
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if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
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warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
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else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
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warning (0, "the %qs architecture does not support branch-likely"
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" instructions", mips_arch_info->name);
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/* The effect of -mabicalls isn't defined for the EABI. */
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if (mips_abi == ABI_EABI && TARGET_ABICALLS)
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@ -11456,7 +11448,7 @@ mips_matching_cpu_name_p (const char *canonical, const char *given)
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static const struct mips_cpu_info *
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mips_parse_cpu (const char *cpu_string)
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{
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const struct mips_cpu_info *p;
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unsigned int i;
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const char *s;
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/* In the past, we allowed upper-case CPU names, but it doesn't
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@ -11482,9 +11474,9 @@ mips_parse_cpu (const char *cpu_string)
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if (strcasecmp (cpu_string, "default") == 0)
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return 0;
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for (p = mips_cpu_info_table; p->name != 0; p++)
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if (mips_matching_cpu_name_p (p->name, cpu_string))
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return p;
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for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
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if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
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return mips_cpu_info_table + i;
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return 0;
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}
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@ -11496,11 +11488,11 @@ mips_parse_cpu (const char *cpu_string)
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static const struct mips_cpu_info *
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mips_cpu_info_from_isa (int isa)
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{
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const struct mips_cpu_info *p;
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unsigned int i;
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for (p = mips_cpu_info_table; p->name != 0; p++)
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if (p->isa == isa)
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return p;
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for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
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if (mips_cpu_info_table[i].isa == isa)
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return mips_cpu_info_table + i;
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return 0;
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}
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@ -97,6 +97,14 @@ struct mips_rtx_cost_data
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#define ABI_EABI 3
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#define ABI_O64 4
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/* Masks that affect tuning.
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PTF_AVOID_BRANCHLIKELY
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Set if it is usually not profitable to use branch-likely instructions
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for this target, typically because the branches are always predicted
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taken and so incur a large overhead when not taken. */
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#define PTF_AVOID_BRANCHLIKELY 0x1
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/* Information about one recognized processor. Defined here for the
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benefit of TARGET_CPU_CPP_BUILTINS. */
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struct mips_cpu_info {
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@ -112,6 +120,9 @@ struct mips_cpu_info {
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/* The ISA level that the processor implements. */
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int isa;
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/* A mask of PTF_* values. */
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unsigned int tune_flags;
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};
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/* Enumerates the setting of the -mcode-readable option. */
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@ -706,9 +717,7 @@ extern enum mips_code_readable_setting mips_code_readable;
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#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
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&& ISA_HAS_COND_TRAP)
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#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
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&& !TARGET_SR71K \
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&& !TARGET_MIPS16)
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#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
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/* True if the ABI can only work with 64-bit integer registers. We
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generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
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