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mn10300: fp insn cleanup
Delete integer-mode abssf2, negsf2; these will be handled by the middle-end now. Delete unnecessary expanders. From-SVN: r168673
This commit is contained in:
Richard Henderson
Richard Henderson
parent
c157b3f0d2
commit
0d9e23f4ee
@ -1,5 +1,10 @@
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2011-01-11 Richard Henderson <rth@redhat.com>
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* config/mn10300/mn10300.md (absdf2, negdf2): Remove.
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(abssf2, negsf2): Define only for hardware fp.
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(sqrtsf2): Reformat.
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(addsf3, subsf3, mulsf3): Merge expander and insn.
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* config/mn10300/mn10300.h (ARG_PIONTER_CFA_OFFSET): New.
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(DEBUGGER_AUTO_OFFSET): Remove.
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(DEBUGGER_ARG_OFFSET): Remove.
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@ -2577,74 +2577,8 @@
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;; ----------------------------------------------------------------------
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;; FP INSTRUCTIONS
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;; ----------------------------------------------------------------------
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;;
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;; The mn103 series does not have floating point instructions, but since
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;; FP values are held in integer regs, we can clear the high bit easily
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;; which gives us an efficient inline floating point absolute value.
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;;
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;; Similarly for negation of a FP value.
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;;
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(define_expand "absdf2"
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[(set (match_operand:DF 0 "register_operand")
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(abs:DF (match_operand:DF 1 "register_operand")))]
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""
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"
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{
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rtx target, result, insns;
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start_sequence ();
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target = operand_subword (operands[0], 1, 1, DFmode);
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result = expand_binop (SImode, and_optab,
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operand_subword_force (operands[1], 1, DFmode),
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GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
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gcc_assert (result);
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if (result != target)
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emit_move_insn (result, target);
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emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
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operand_subword_force (operands[1], 0, DFmode));
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insns = get_insns ();
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end_sequence ();
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emit_insn (insns);
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DONE;
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}")
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(define_expand "abssf2"
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[(set (match_operand:SF 0 "register_operand")
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(abs:SF (match_operand:SF 1 "register_operand")))]
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""
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"
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{
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rtx result;
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rtx target;
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if (TARGET_AM33_2)
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{
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emit_insn (gen_abssf2_am33_2 (operands[0], operands[1]));
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DONE;
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}
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target = operand_subword_force (operands[0], 0, SFmode);
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result = expand_binop (SImode, and_optab,
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operand_subword_force (operands[1], 0, SFmode),
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GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
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gcc_assert (result);
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if (result != target)
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emit_move_insn (result, target);
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/* Make a place for REG_EQUAL. */
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emit_move_insn (operands[0], operands[0]);
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DONE;
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}")
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(define_insn "abssf2_am33_2"
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(define_insn "abssf2"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
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"TARGET_AM33_2"
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@ -2655,67 +2589,7 @@
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(const_int 17) (const_int 14)))]
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)
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(define_expand "negdf2"
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[(set (match_operand:DF 0 "register_operand")
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(neg:DF (match_operand:DF 1 "register_operand")))]
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""
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"
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{
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rtx target, result, insns;
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start_sequence ();
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target = operand_subword (operands[0], 1, 1, DFmode);
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result = expand_binop (SImode, xor_optab,
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operand_subword_force (operands[1], 1, DFmode),
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GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
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target, 0, OPTAB_WIDEN);
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gcc_assert (result);
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if (result != target)
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emit_move_insn (result, target);
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emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
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operand_subword_force (operands[1], 0, DFmode));
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insns = get_insns ();
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end_sequence ();
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emit_insn (insns);
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DONE;
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}")
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(define_expand "negsf2"
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[(set (match_operand:SF 0 "register_operand")
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(neg:SF (match_operand:SF 1 "register_operand")))]
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""
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"
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{
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rtx result;
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rtx target;
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if (TARGET_AM33_2)
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{
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emit_insn (gen_negsf2_am33_2 (operands[0], operands[1]));
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DONE;
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}
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target = operand_subword_force (operands[0], 0, SFmode);
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result = expand_binop (SImode, xor_optab,
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operand_subword_force (operands[1], 0, SFmode),
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GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
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target, 0, OPTAB_WIDEN);
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gcc_assert (result);
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if (result != target)
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emit_move_insn (result, target);
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/* Make a place for REG_EQUAL. */
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emit_move_insn (operands[0], operands[0]);
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DONE;
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}")
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(define_insn "negsf2_am33_2"
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(define_insn "negsf2"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
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"TARGET_AM33_2"
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@ -2727,27 +2601,22 @@
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)
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(define_expand "sqrtsf2"
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[(parallel [(set (match_operand:SF 0 "register_operand" "")
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(sqrt:SF (match_operand:SF 1 "register_operand" "")))
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(clobber (reg:CC_FLOAT CC_REG))
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])
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]
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[(set (match_operand:SF 0 "register_operand" "")
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(sqrt:SF (match_operand:SF 1 "register_operand" "")))]
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"TARGET_AM33_2 && flag_unsafe_math_optimizations"
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"
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{
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rtx scratch = gen_reg_rtx (SFmode);
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emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
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emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
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scratch));
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DONE;
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}")
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{
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rtx scratch = gen_reg_rtx (SFmode);
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emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
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emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
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scratch));
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DONE;
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})
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(define_insn "rsqrtsf2"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
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(sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
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(clobber (reg:CC_FLOAT CC_REG))
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]
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(clobber (reg:CC_FLOAT CC_REG))]
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"TARGET_AM33_2"
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"@
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frsqrt %0
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@ -2756,22 +2625,11 @@
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(const_int 4753) (const_int 2327)))]
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)
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(define_expand "addsf3"
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[(parallel [(set (match_operand:SF 0 "register_operand")
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(plus:SF (match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "nonmemory_operand")))
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(clobber (reg:CC_FLOAT CC_REG))])
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]
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"TARGET_AM33_2"
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""
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)
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(define_insn "*addsf3_internal"
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(define_insn "addsf3"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(plus:SF (match_operand:SF 1 "register_operand" "%0,f")
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(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
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(clobber (reg:CC_FLOAT CC_REG))
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]
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(clobber (reg:CC_FLOAT CC_REG))]
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"TARGET_AM33_2"
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"@
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fadd %2, %0
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@ -2781,26 +2639,14 @@
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(const_int 17) (const_int 14))
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(if_then_else (eq_attr "cpu" "am34")
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(const_int 17) (const_int 25))
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])
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]
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])]
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)
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(define_expand "subsf3"
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[(parallel [(set (match_operand:SF 0 "register_operand")
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(minus:SF (match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "nonmemory_operand")))
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(clobber (reg:CC_FLOAT CC_REG))])
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]
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"TARGET_AM33_2"
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""
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)
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(define_insn "*subsf3_internal"
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(define_insn "subsf3"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(minus:SF (match_operand:SF 1 "register_operand" "0,f")
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(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
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(clobber (reg:CC_FLOAT CC_REG))
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]
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(clobber (reg:CC_FLOAT CC_REG))]
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"TARGET_AM33_2"
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"@
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fsub %2, %0
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@ -2810,21 +2656,10 @@
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(const_int 17) (const_int 14))
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(if_then_else (eq_attr "cpu" "am34")
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(const_int 17) (const_int 25))
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])
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]
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])]
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)
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(define_expand "mulsf3"
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[(parallel [(set (match_operand:SF 0 "register_operand")
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(mult:SF (match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "nonmemory_operand")))
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(clobber (reg:CC_FLOAT CC_REG))])
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]
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"TARGET_AM33_2"
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""
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)
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(define_insn "*mulsf3_internal"
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(define_insn "mulsf3"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(mult:SF (match_operand:SF 1 "register_operand" "%0,f")
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(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
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@ -2839,16 +2674,14 @@
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(const_int 17) (const_int 14))
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(if_then_else (eq_attr "cpu" "am34")
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(const_int 17) (const_int 25))
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])
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]
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])]
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)
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(define_insn "divsf3"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(div:SF (match_operand:SF 1 "register_operand" "0,f")
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(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
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(clobber (reg:CC_FLOAT CC_REG))
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]
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(clobber (reg:CC_FLOAT CC_REG))]
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"TARGET_AM33_2"
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"@
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fdiv %2, %0
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@ -2858,8 +2691,7 @@
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(const_int 2531) (const_int 1216))
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(if_then_else (eq_attr "cpu" "am34")
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(const_int 2531) (const_int 1317))
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])
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]
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])]
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)
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(define_insn "fmasf4"
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