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aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
gcc/ChangeLog: 2014-04-22 Vidya Praveen <vidyapraveen@arm.com> * aarch64.md (float<GPI:mode><GPF:mode>2): Remove. (floatuns<GPI:mode><GPF:mode>2): Remove. (<optab><fcvt_target><GPF:mode>2): New pattern for equal width float and floatuns conversions. (<optab><fcvt_iesize><GPF:mode>2): New pattern for inequal width float and floatuns conversions. * iterators.md (fcvt_target, FCVT_TARGET): Support SF and DF modes. (w1,w2): New mode attributes for inequal width conversions. gcc/testsuite/ChangeLog: 2014-04-22 Vidya Praveen <vidyapraveen@arm.com> * gcc.target/aarch64/vect_cvtf_1.c: New. From-SVN: r209620
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Vidya Praveen
Vidya Praveen
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@ -1,3 +1,14 @@
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2014-04-22 Vidya Praveen <vidyapraveen@arm.com>
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* aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
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(floatuns<GPI:mode><GPF:mode>2): Remove.
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(<optab><fcvt_target><GPF:mode>2): New pattern for equal width float
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and floatuns conversions.
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(<optab><fcvt_iesize><GPF:mode>2): New pattern for inequal width float
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and floatuns conversions.
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* iterators.md (fcvt_target, FCVT_TARGET): Support SF and DF modes.
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(w1,w2): New mode attributes for inequal width conversions.
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2014-04-22 Renlin Li <Renlin.Li@arm.com>
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* config/aarch64/aarch64.c (aarch64_print_operand_address): Adjust
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@ -3299,20 +3299,24 @@
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[(set_attr "type" "f_cvtf2i")]
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)
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(define_insn "float<GPI:mode><GPF:mode>2"
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[(set (match_operand:GPF 0 "register_operand" "=w")
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(float:GPF (match_operand:GPI 1 "register_operand" "r")))]
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"TARGET_FLOAT"
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"scvtf\\t%<GPF:s>0, %<GPI:w>1"
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[(set_attr "type" "f_cvti2f")]
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(define_insn "<optab><fcvt_target><GPF:mode>2"
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[(set (match_operand:GPF 0 "register_operand" "=w,w")
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(FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
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""
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"@
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<su_optab>cvtf\t%<GPF:s>0, %<s>1
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<su_optab>cvtf\t%<GPF:s>0, %<w1>1"
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[(set_attr "simd" "yes,no")
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(set_attr "fp" "no,yes")
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(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")]
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)
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(define_insn "floatuns<GPI:mode><GPF:mode>2"
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(define_insn "<optab><fcvt_iesize><GPF:mode>2"
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[(set (match_operand:GPF 0 "register_operand" "=w")
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(unsigned_float:GPF (match_operand:GPI 1 "register_operand" "r")))]
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(FLOATUORS:GPF (match_operand:<FCVT_IESIZE> 1 "register_operand" "r")))]
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"TARGET_FLOAT"
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"ucvtf\\t%<GPF:s>0, %<GPI:w>1"
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[(set_attr "type" "f_cvt")]
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"<su_optab>cvtf\t%<GPF:s>0, %<w2>1"
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[(set_attr "type" "f_cvti2f")]
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)
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;; -------------------------------------------------------------------
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@ -293,6 +293,10 @@
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;; 32-bit version and "%x0" in the 64-bit version.
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(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
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;; For inequal width int to float conversion
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(define_mode_attr w1 [(SF "w") (DF "x")])
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(define_mode_attr w2 [(SF "x") (DF "w")])
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;; For constraints used in scalar immediate vector moves
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(define_mode_attr hq [(HI "h") (QI "q")])
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@ -558,8 +562,12 @@
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(define_mode_attr atomic_sfx
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[(QI "b") (HI "h") (SI "") (DI "")])
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(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")])
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(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")])
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(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
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(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
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;; for the inequal width integer to fp conversions
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(define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
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(define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
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(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
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(V4HI "V8HI") (V8HI "V4HI")
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@ -1,3 +1,7 @@
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2014-04-22 Vidya Praveen <vidyapraveen@arm.com>
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* gcc.target/aarch64/vect_cvtf_1.c: New.
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2014-04-22 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/60823
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95
gcc/testsuite/gcc.target/aarch64/cvtf_1.c
Normal file
95
gcc/testsuite/gcc.target/aarch64/cvtf_1.c
Normal file
@ -0,0 +1,95 @@
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/* { dg-do run } */
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/* { dg-options "-save-temps -fno-inline -O1" } */
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#define FCVTDEF(ftype,itype) \
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void \
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cvt_##itype##_to_##ftype (itype a, ftype b)\
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{\
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ftype c;\
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c = (ftype) a;\
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if ( (c - b) > 0.00001) abort();\
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}
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#define force_simd_for_float(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
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#define force_simd_for_double(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
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#define FCVTDEF_SISD(ftype,itype) \
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void \
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cvt_##itype##_to_##ftype##_sisd (itype a, ftype b)\
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{\
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ftype c;\
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force_simd_for_##ftype(a);\
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c = (ftype) a;\
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if ( (c - b) > 0.00001) abort();\
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}
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#define FCVT(ftype,itype,ival,fval) cvt_##itype##_to_##ftype (ival, fval);
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#define FCVT_SISD(ftype,itype,ival,fval) cvt_##itype##_to_##ftype##_sisd (ival, fval);
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typedef int int32_t;
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typedef unsigned int uint32_t;
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typedef long long int int64_t;
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typedef unsigned long long int uint64_t;
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extern void abort();
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FCVTDEF (float, int32_t)
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/* { dg-final { scan-assembler "scvtf\ts\[0-9\]+,\ w\[0-9\]+" } } */
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FCVTDEF (float, uint32_t)
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/* { dg-final { scan-assembler "ucvtf\ts\[0-9\]+,\ w\[0-9\]+" } } */
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FCVTDEF (double, int32_t)
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/* "scvtf\td\[0-9\]+,\ w\[0-9\]+" */
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FCVTDEF (double, uint32_t)
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/* "ucvtf\td\[0-9\]+,\ w\[0-9\]+" */
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FCVTDEF (float, int64_t)
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/* "scvtf\ts\[0-9\]+,\ x\[0-9\]+" */
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FCVTDEF (float, uint64_t)
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/* "ucvtf\ts\[0-9\]+,\ x\[0-9\]+" */
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FCVTDEF (double, int64_t)
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/* { dg-final { scan-assembler "scvtf\td\[0-9\]+,\ x\[0-9\]+" } } */
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FCVTDEF (double, uint64_t)
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/* { dg-final { scan-assembler "ucvtf\td\[0-9\]+,\ x\[0-9\]+" } } */
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FCVTDEF_SISD (float, int32_t)
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/* { dg-final { scan-assembler "scvtf\ts\[0-9\]+,\ s\[0-9\]+" } } */
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FCVTDEF_SISD (double, int64_t)
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/* { dg-final { scan-assembler "scvtf\td\[0-9\]+,\ d\[0-9\]+" } } */
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FCVTDEF_SISD (float, uint32_t)
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/* { dg-final { scan-assembler "ucvtf\ts\[0-9\]+,\ s\[0-9\]+" } } */
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FCVTDEF_SISD (double, uint64_t)
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/* { dg-final { scan-assembler "ucvtf\td\[0-9\]+,\ d\[0-9\]+" } } */
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FCVTDEF_SISD (float, int64_t)
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/* { dg-final { scan-assembler-times "scvtf\ts\[0-9\]+,\ x\[0-9\]+" 2 } } */
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FCVTDEF_SISD (float, uint64_t)
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/* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\]+,\ x\[0-9\]+" 2 } } */
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FCVTDEF_SISD (double, int32_t)
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/* { dg-final { scan-assembler-times "scvtf\td\[0-9\]+,\ w\[0-9\]+" 2 } } */
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FCVTDEF_SISD (double, uint32_t)
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/* { dg-final { scan-assembler-times "ucvtf\td\[0-9\]+,\ w\[0-9\]+" 2 } } */
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int32_t ival = -1234;
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int64_t llival = -13031303L;
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uint32_t uival = 1234;
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uint64_t ullival = 13031303L;
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int main ()
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{
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float x;
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double y;
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FCVT (float, int32_t, ival, -1234.0);
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FCVT (float, uint32_t, uival, 1234.0);
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FCVT (float, int64_t, llival, -13031303.0);
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FCVT (float, uint64_t, ullival, 13031303.0);
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FCVT (double, int32_t, ival, -1234.0);
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FCVT (double, uint32_t, uival, 1234.0);
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FCVT (double, int64_t, llival, -13031303.0);
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FCVT (double, uint64_t, ullival, 13031303.0);
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FCVT_SISD (float, int32_t, ival, -1234.0);
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FCVT_SISD (double, int64_t, llival, -13031303.0);
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FCVT_SISD (float, uint32_t, uival, 1234.0);
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FCVT_SISD (double, uint64_t, ullival, 13031303.0);
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return 0;
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}
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/* { dg-final { cleanup-saved-temps } } */
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