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re PR target/65697 (__atomic memory barriers not strong enough for __sync builtins)

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PR target/65697
	* gcc.target/aarch64/sync-comp-swap.c: New.
	* gcc.target/aarch64/sync-comp-swap.x: New.
	* gcc.target/aarch64/sync-op-acquire.c: New.
	* gcc.target/aarch64/sync-op-acquire.x: New.
	* gcc.target/aarch64/sync-op-full.c: New.
	* gcc.target/aarch64/sync-op-full.x: New.
	* gcc.target/aarch64/sync-op-release.c: New.
	* gcc.target/aarch64/sync-op-release.x: New.

From-SVN: r223986
This commit is contained in:
Matthew Wahab 2015-06-01 15:24:37 +00:00 committed by Matthew Wahab
parent ab876106eb
commit 0bf5151468
9 changed files with 142 additions and 0 deletions
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12
gcc/testsuite/ChangeLog
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@ -1,3 +1,15 @@
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
PR target/65697
* gcc.target/aarch64/sync-comp-swap.c: New.
* gcc.target/aarch64/sync-comp-swap.x: New.
* gcc.target/aarch64/sync-op-acquire.c: New.
* gcc.target/aarch64/sync-op-acquire.x: New.
* gcc.target/aarch64/sync-op-full.c: New.
* gcc.target/aarch64/sync-op-full.x: New.
* gcc.target/aarch64/sync-op-release.c: New.
* gcc.target/aarch64/sync-op-release.x: New.
2015-06-01 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/arm/thumb-ltu.c (foo): Predefined.

8
gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c Normal file
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/* { dg-do compile } */
/* { dg-options "-O2 -fno-ipa-icf" } */
#include "sync-comp-swap.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */
/* { dg-final { scan-assembler-times "dmb\tish" 2 } } */

13
gcc/testsuite/gcc.target/aarch64/sync-comp-swap.x Normal file
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int v = 0;
int
sync_bool_compare_swap (int a, int b)
{
return __sync_bool_compare_and_swap (&v, &a, &b);
}
int
sync_val_compare_swap (int a, int b)
{
return __sync_val_compare_and_swap (&v, &a, &b);
}

8
gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c Normal file
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/* { dg-do compile } */
/* { dg-options "-O2" } */
#include "sync-op-acquire.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 1 } } */
/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */

7
gcc/testsuite/gcc.target/aarch64/sync-op-acquire.x Normal file
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int v;
int
sync_lock_test_and_set (int a)
{
return __sync_lock_test_and_set (&v, a);
}

8
gcc/testsuite/gcc.target/aarch64/sync-op-full.c Normal file
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/* { dg-do compile } */
/* { dg-options "-O2" } */
#include "sync-op-full.x"
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 12 } } */
/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 12 } } */
/* { dg-final { scan-assembler-times "dmb\tish" 12 } } */

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gcc/testsuite/gcc.target/aarch64/sync-op-full.x Normal file
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int v = 0;
int
sync_fetch_and_add (int a)
{
return __sync_fetch_and_add (&v, a);
}
int
sync_fetch_and_sub (int a)
{
return __sync_fetch_and_sub (&v, a);
}
int
sync_fetch_and_and (int a)
{
return __sync_fetch_and_and (&v, a);
}
int
sync_fetch_and_nand (int a)
{
return __sync_fetch_and_nand (&v, a);
}
int
sync_fetch_and_xor (int a)
{
return __sync_fetch_and_xor (&v, a);
}
int
sync_fetch_and_or (int a)
{
return __sync_fetch_and_or (&v, a);
}
int
sync_add_and_fetch (int a)
{
return __sync_add_and_fetch (&v, a);
}
int
sync_sub_and_fetch (int a)
{
return __sync_sub_and_fetch (&v, a);
}
int
sync_and_and_fetch (int a)
{
return __sync_and_and_fetch (&v, a);
}
int
sync_nand_and_fetch (int a)
{
return __sync_nand_and_fetch (&v, a);
}
int
sync_xor_and_fetch (int a)
{
return __sync_xor_and_fetch (&v, a);
}
int
sync_or_and_fetch (int a)
{
return __sync_or_and_fetch (&v, a);
}

6
gcc/testsuite/gcc.target/aarch64/sync-op-release.c Normal file
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/* { dg-do compile } */
/* { dg-options "-O2" } */
#include "sync-op-release.x"
/* { dg-final { scan-assembler-times "stlr" 1 } } */

7
gcc/testsuite/gcc.target/aarch64/sync-op-release.x Normal file
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int v;
void
sync_lock_release (void)
{
__sync_lock_release (&v);
}