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[PATCH, GCC/ARM, 5/10] Clear VFP registers with VSCCLRM
This patch adds a new pattern for the VSCCLRM instruction. cmse_clear_registers () is then modified to use the new VSCCLRM instruction when targeting Armv8.1-M Mainline, thus, making the Armv8-M register clearing code specific to Armv8-M. Since the VSCCLRM instruction mandates VPR in the register list, the pattern is encoded with a parallel which only requires an unspecified VUNSPEC_CLRM_VPR constant modelling the APSR clearing. Other expression in the parallel are expected to be set expression for clearing the VFP registers. *** gcc/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm-protos.h (clear_operation_p): Adapt prototype. * config/arm/arm.c (clear_operation_p): Extend to be able to check a clear_vfp_multiple pattern based on a new vfp parameter. (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when targeting Armv8.1-M Mainline. (cmse_nonsecure_entry_clear_before_return): Clear VFP registers unconditionally when targeting Armv8.1-M Mainline architecture. Check whether VFP registers are available before looking call_used_regs for a VFP register. * config/arm/predicates.md (clear_multiple_operation): Adapt to change of prototype of clear_operation_p. (clear_vfp_multiple_operation): New predicate. * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec. * config/arm/vfp.md (clear_vfp_multiple): New define_insn. *** gcc/testsuite/ChangeLog *** 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com> 2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com> * gcc.target/arm/cmse/bitfield-1.c: Add check for VSCCLRM. * gcc.target/arm/cmse/bitfield-2.c: Likewise. * gcc.target/arm/cmse/bitfield-3.c: Likewise. * gcc.target/arm/cmse/cmse-1.c: Likewise. * gcc.target/arm/cmse/struct-1.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise. * gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.
This commit is contained in:
Mihail Ionescu
parent
9722215a02
commit
0b1c7b27a7
@ -1,6 +1,24 @@
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2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
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2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
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* config/arm/arm.c (clear_operation_p): Extend to be able to check a
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clear_vfp_multiple pattern based on a new vfp parameter.
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(cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
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targeting Armv8.1-M Mainline.
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(cmse_nonsecure_entry_clear_before_return): Clear VFP registers
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unconditionally when targeting Armv8.1-M Mainline architecture. Check
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whether VFP registers are available before looking call_used_regs for a
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VFP register.
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* config/arm/predicates.md (clear_multiple_operation): Adapt to change
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of prototype of clear_operation_p.
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(clear_vfp_multiple_operation): New predicate.
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* config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
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* config/arm/vfp.md (clear_vfp_multiple): New define_insn.
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2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
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2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/arm/arm-protos.h (clear_operation_p): Declare.
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* config/arm/arm.c (clear_operation_p): New function.
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(cmse_clear_registers): Generate clear_multiple instruction pattern if
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@ -83,7 +83,7 @@ extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
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extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
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extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
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bool, bool);
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extern bool clear_operation_p (rtx);
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extern bool clear_operation_p (rtx, bool);
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extern int arm_const_double_rtx (rtx);
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extern int vfp3_const_double_rtx (rtx);
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extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
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@ -13709,8 +13709,9 @@ ldm_stm_operation_p (rtx op, bool load, machine_mode mode,
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return true;
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}
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/* Checks whether OP is a valid parallel pattern for a CLRM insn. To be a
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valid CLRM pattern, OP must have the following form:
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/* Checks whether OP is a valid parallel pattern for a CLRM (if VFP is false)
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or VSCCLRM (otherwise) insn. To be a valid CLRM pattern, OP must have the
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following form:
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[(set (reg:SI <N>) (const_int 0))
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(set (reg:SI <M>) (const_int 0))
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@ -13722,22 +13723,35 @@ ldm_stm_operation_p (rtx op, bool load, machine_mode mode,
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Any number (including 0) of set expressions is valid, the volatile unspec is
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optional. All registers but SP and PC are allowed and registers must be in
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strict increasing order. */
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strict increasing order.
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To be a valid VSCCLRM pattern, OP must have the following form:
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[(unspec_volatile [(const_int 0)]
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VUNSPEC_VSCCLRM_VPR)
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(set (reg:SF <N>) (const_int 0))
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(set (reg:SF <M>) (const_int 0))
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...
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]
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As with CLRM, any number (including 0) of set expressions is valid, however
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the volatile unspec is mandatory here. Any VFP single-precision register is
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accepted but all registers must be consecutive and in increasing order. */
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bool
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clear_operation_p (rtx op)
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clear_operation_p (rtx op, bool vfp)
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{
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HOST_WIDE_INT i;
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unsigned regno, last_regno;
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rtx elt, reg, zero;
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machine_mode mode;
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HOST_WIDE_INT count = XVECLEN (op, 0);
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HOST_WIDE_INT i, first_set = vfp ? 1 : 0;
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machine_mode expected_mode = vfp ? E_SFmode : E_SImode;
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for (i = 0; i < count; i++)
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for (i = first_set; i < count; i++)
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{
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elt = XVECEXP (op, 0, i);
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if (GET_CODE (elt) == UNSPEC_VOLATILE)
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if (!vfp && GET_CODE (elt) == UNSPEC_VOLATILE)
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{
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if (XINT (elt, 1) != VUNSPEC_CLRM_APSR
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|| XVECLEN (elt, 0) != 1
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@ -13756,17 +13770,26 @@ clear_operation_p (rtx op)
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reg = SET_DEST (elt);
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regno = REGNO (reg);
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mode = GET_MODE (reg);
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zero = SET_SRC (elt);
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if (!REG_P (reg)
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|| GET_MODE (reg) != SImode
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|| regno == SP_REGNUM
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|| regno == PC_REGNUM
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|| (i != 0 && regno <= last_regno)
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|| GET_MODE (reg) != expected_mode
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|| zero != CONST0_RTX (SImode))
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return false;
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if (vfp)
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{
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if (i != 1 && regno != last_regno + 1)
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return false;
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}
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else
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{
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if (regno == SP_REGNUM || regno == PC_REGNUM)
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return false;
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if (i != 0 && regno <= last_regno)
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return false;
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}
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last_regno = REGNO (reg);
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}
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@ -18112,6 +18135,43 @@ cmse_clear_registers (sbitmap to_clear_bitmap, uint32_t *padding_bits_to_clear,
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auto_sbitmap core_regs_bitmap (to_clear_bitmap_size);
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auto_sbitmap to_clear_core_bitmap (to_clear_bitmap_size);
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for (i = FIRST_VFP_REGNUM; i <= maxregno; i += nb_regs)
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{
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/* Find next register to clear and exit if none. */
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for (; i <= maxregno && !bitmap_bit_p (to_clear_bitmap, i); i++);
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if (i > maxregno)
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break;
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/* Compute number of consecutive registers to clear. */
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for (j = i; j <= maxregno && bitmap_bit_p (to_clear_bitmap, j);
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j++);
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nb_regs = j - i;
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/* Create VSCCLRM RTX pattern. */
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par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nb_regs + 1));
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vunspec_vec = gen_rtvec (1, gen_int_mode (0, SImode));
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vunspec = gen_rtx_UNSPEC_VOLATILE (SImode, vunspec_vec,
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VUNSPEC_VSCCLRM_VPR);
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XVECEXP (par, 0, 0) = vunspec;
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/* Insert VFP register clearing RTX in the pattern. */
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start_sequence ();
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for (k = 1, j = i; j <= maxregno && k < nb_regs + 1; j++)
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{
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if (!bitmap_bit_p (to_clear_bitmap, j))
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continue;
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reg = gen_rtx_REG (SFmode, j);
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set = gen_rtx_SET (reg, const0_rtx);
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XVECEXP (par, 0, k++) = set;
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emit_use (reg);
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}
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use_seq = get_insns ();
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end_sequence ();
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emit_insn_after (use_seq, emit_insn (par));
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}
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/* Get set of core registers to clear. */
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bitmap_clear (core_regs_bitmap);
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bitmap_set_range (core_regs_bitmap, R0_REGNUM,
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@ -18156,49 +18216,50 @@ cmse_clear_registers (sbitmap to_clear_bitmap, uint32_t *padding_bits_to_clear,
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end_sequence ();
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emit_insn_after (use_seq, emit_insn (par));
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minregno = FIRST_VFP_REGNUM;
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}
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/* If not marked for clearing, clearing_reg already does not contain
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any secret. */
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if (clearing_regno <= maxregno
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&& bitmap_bit_p (to_clear_bitmap, clearing_regno))
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else
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{
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emit_move_insn (clearing_reg, const0_rtx);
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emit_use (clearing_reg);
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bitmap_clear_bit (to_clear_bitmap, clearing_regno);
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}
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for (regno = minregno; regno <= maxregno; regno++)
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{
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if (!bitmap_bit_p (to_clear_bitmap, regno))
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continue;
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if (IS_VFP_REGNUM (regno))
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/* If not marked for clearing, clearing_reg already does not contain
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any secret. */
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if (clearing_regno <= maxregno
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&& bitmap_bit_p (to_clear_bitmap, clearing_regno))
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{
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/* If regno is an even vfp register and its successor is also to
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be cleared, use vmov. */
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if (TARGET_VFP_DOUBLE
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&& VFP_REGNO_OK_FOR_DOUBLE (regno)
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&& bitmap_bit_p (to_clear_bitmap, regno + 1))
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emit_move_insn (clearing_reg, const0_rtx);
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emit_use (clearing_reg);
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bitmap_clear_bit (to_clear_bitmap, clearing_regno);
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}
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for (regno = minregno; regno <= maxregno; regno++)
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{
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if (!bitmap_bit_p (to_clear_bitmap, regno))
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continue;
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if (IS_VFP_REGNUM (regno))
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{
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emit_move_insn (gen_rtx_REG (DFmode, regno),
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CONST1_RTX (DFmode));
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emit_use (gen_rtx_REG (DFmode, regno));
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regno++;
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/* If regno is an even vfp register and its successor is also to
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be cleared, use vmov. */
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if (TARGET_VFP_DOUBLE
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&& VFP_REGNO_OK_FOR_DOUBLE (regno)
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&& bitmap_bit_p (to_clear_bitmap, regno + 1))
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{
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emit_move_insn (gen_rtx_REG (DFmode, regno),
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CONST1_RTX (DFmode));
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emit_use (gen_rtx_REG (DFmode, regno));
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regno++;
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}
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else
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{
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emit_move_insn (gen_rtx_REG (SFmode, regno),
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CONST1_RTX (SFmode));
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emit_use (gen_rtx_REG (SFmode, regno));
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}
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}
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else
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{
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emit_move_insn (gen_rtx_REG (SFmode, regno),
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CONST1_RTX (SFmode));
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emit_use (gen_rtx_REG (SFmode, regno));
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emit_move_insn (gen_rtx_REG (SImode, regno), clearing_reg);
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emit_use (gen_rtx_REG (SImode, regno));
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}
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}
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else
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{
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emit_move_insn (gen_rtx_REG (SImode, regno), clearing_reg);
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emit_use (gen_rtx_REG (SImode, regno));
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}
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}
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}
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@ -26397,7 +26458,8 @@ thumb1_expand_prologue (void)
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void
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cmse_nonsecure_entry_clear_before_return (void)
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{
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int regno, maxregno = TARGET_HARD_FLOAT ? LAST_VFP_REGNUM : IP_REGNUM;
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bool clear_vfpregs = TARGET_HARD_FLOAT || TARGET_HAVE_FPCXT_CMSE;
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int regno, maxregno = clear_vfpregs ? LAST_VFP_REGNUM : IP_REGNUM;
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uint32_t padding_bits_to_clear = 0;
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auto_sbitmap to_clear_bitmap (maxregno + 1);
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rtx r1_reg, result_rtl, clearing_reg = NULL_RTX;
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@ -26409,7 +26471,7 @@ cmse_nonsecure_entry_clear_before_return (void)
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/* If we are not dealing with -mfloat-abi=soft we will need to clear VFP
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registers. */
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if (TARGET_HARD_FLOAT)
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if (clear_vfpregs)
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{
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int float_bits = D7_VFP_REGNUM - FIRST_VFP_REGNUM + 1;
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@ -26438,7 +26500,9 @@ cmse_nonsecure_entry_clear_before_return (void)
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continue;
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if (IN_RANGE (regno, IP_REGNUM, PC_REGNUM))
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continue;
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if (call_used_or_fixed_reg_p (regno))
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if (call_used_or_fixed_reg_p (regno)
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&& (!IN_RANGE (regno, FIRST_VFP_REGNUM, LAST_VFP_REGNUM)
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|| TARGET_HARD_FLOAT))
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bitmap_set_bit (to_clear_bitmap, regno);
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}
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@ -548,7 +548,13 @@
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(define_special_predicate "clear_multiple_operation"
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(match_code "parallel")
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{
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return clear_operation_p (op);
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return clear_operation_p (op, /*vfp*/false);
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})
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(define_special_predicate "clear_vfp_multiple_operation"
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(match_code "parallel")
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{
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return clear_operation_p (op, /*vfp*/true);
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})
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(define_special_predicate "load_multiple_operation"
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@ -241,6 +241,8 @@
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VUNSPEC_APSR_WRITE ; Represent writing the APSR.
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VUNSPEC_VSTR_VLDR ; Represent the vstr/vldr instruction.
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VUNSPEC_CLRM_APSR ; Represent the clearing of APSR with clrm instruction.
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VUNSPEC_VSCCLRM_VPR ; Represent the clearing of VPR with vscclrm
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; instruction.
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])
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;; Enumerators for NEON unspecs.
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@ -1637,6 +1637,42 @@
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(set_attr "type" "load_4")]
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)
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;; The operands are validated through the clear_multiple_operation
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;; match_parallel predicate rather than through constraints so enable it only
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;; after reload.
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(define_insn "*clear_vfp_multiple"
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[(match_parallel 0 "clear_vfp_multiple_operation"
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[(unspec_volatile [(const_int 0)]
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VUNSPEC_VSCCLRM_VPR)])]
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"TARGET_HAVE_FPCXT_CMSE && use_cmse && reload_completed"
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{
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int num_regs = XVECLEN (operands[0], 0);
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char pattern[30];
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const char *regname;
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rtx reg;
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strcpy (pattern, \"vscclrm%?\\t{%|\");
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if (num_regs > 1)
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{
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reg = XEXP (XVECEXP (operands[0], 0, 1), 0);
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strcat (pattern, reg_names[REGNO (reg)]);
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if (num_regs > 2)
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{
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strcat (pattern, \"-%|\");
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reg = XEXP (XVECEXP (operands[0], 0, num_regs - 1), 0);
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strcat (pattern, reg_names[REGNO (reg)]);
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}
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strcat (pattern, \", \");
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}
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strcat (pattern, \"VPR}\");
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output_asm_insn (pattern, operands);
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return \"\";
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}
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[(set_attr "predicable" "yes")
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(set_attr "type" "mov_reg")]
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)
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(define_insn_and_split "*cmpsf_split_vfp"
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[(set (reg:CCFP CC_REGNUM)
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(compare:CCFP (match_operand:SF 0 "s_register_operand" "t")
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@ -1,6 +1,26 @@
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2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
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2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* gcc.target/arm/cmse/bitfield-1.c: Add check for VSCCLRM.
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* gcc.target/arm/cmse/bitfield-2.c: Likewise.
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* gcc.target/arm/cmse/bitfield-3.c: Likewise.
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* gcc.target/arm/cmse/cmse-1.c: Likewise.
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* gcc.target/arm/cmse/struct-1.c: Likewise.
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* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-13.c: Likewise.
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* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise.
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* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-7.c: Likewise.
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* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-8.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-13.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-7.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-8.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c: Likewise.
|
||||
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.
|
||||
|
||||
2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
|
||||
2020-01-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* gcc.target/arm/cmse/bitfield-1.c: Add check for CLRM.
|
||||
* gcc.target/arm/cmse/bitfield-2.c: Likewise.
|
||||
* gcc.target/arm/cmse/bitfield-3.c: Likewise.
|
||||
|
||||
@ -36,6 +36,7 @@ main (void)
|
||||
/* { dg-final { scan-assembler "movw\tr1, #1855" } } */
|
||||
/* { dg-final { scan-assembler "movt\tr1, 65535" } } */
|
||||
/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -33,6 +33,7 @@ main (void)
|
||||
/* { dg-final { scan-assembler "movw\tr1, #1919" } } */
|
||||
/* { dg-final { scan-assembler "movt\tr1, 2047" } } */
|
||||
/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -34,6 +34,7 @@ main (void)
|
||||
/* { dg-final { scan-assembler "movw\tr1, #65535" } } */
|
||||
/* { dg-final { scan-assembler "movt\tr1, 63" } } */
|
||||
/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -105,6 +105,7 @@ qux (int_nsfunc_t * callback)
|
||||
/* { dg-final { scan-assembler "bic" } } */
|
||||
/* { dg-final { scan-assembler "push\t\{r4, r5, r6" } } */
|
||||
/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "msr\tAPSR_nzcvq" { target { ! arm_cmse_clear_ok } } } } */
|
||||
|
||||
@ -10,21 +10,10 @@
|
||||
/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s1, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s4-s15, VPR\}" } } */
|
||||
|
||||
/* Now we check that we use the correct intrinsic to call. */
|
||||
/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
|
||||
|
||||
@ -6,22 +6,7 @@
|
||||
#include "../../../cmse-5.x"
|
||||
|
||||
/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s1-s15, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, ip, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -9,22 +9,7 @@
|
||||
/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
|
||||
|
||||
/* Now we check that we use the correct intrinsic to call. */
|
||||
/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
|
||||
|
||||
@ -11,20 +11,7 @@
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s2-s15, VPR\}" } } */
|
||||
|
||||
/* Now we check that we use the correct intrinsic to call. */
|
||||
/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
|
||||
|
||||
@ -9,18 +9,13 @@
|
||||
/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f64\td1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s1, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s4-s15, VPR\}" } } */
|
||||
|
||||
/* Now we check that we use the correct intrinsic to call. */
|
||||
/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
|
||||
|
||||
@ -6,15 +6,7 @@
|
||||
#include "../../../cmse-5.x"
|
||||
|
||||
/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s1-s15, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, ip, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -9,14 +9,7 @@
|
||||
/* { dg-final { scan-assembler "lsrs\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
|
||||
|
||||
/* Now we check that we use the correct intrinsic to call. */
|
||||
/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
|
||||
|
||||
@ -10,13 +10,7 @@
|
||||
/* { dg-final { scan-assembler "lsls\tr4, r4, #1" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r0, r1, r2, r3, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov\.f64\td0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s2-s15, VPR\}" } } */
|
||||
|
||||
/* Now we check that we use the correct intrinsic to call. */
|
||||
/* { dg-final { scan-assembler "bl\t__gnu_cmse_nonsecure_call" } } */
|
||||
|
||||
@ -7,6 +7,7 @@
|
||||
/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
|
||||
/* { dg-final { scan-assembler-not "vmov" } } */
|
||||
/* { dg-final { scan-assembler-not "vmsr" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -8,22 +8,7 @@
|
||||
/* { dg-final { scan-assembler "__acle_se_foo:" } } */
|
||||
/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
|
||||
/* { dg-final { scan-assembler-not "mov\tr0, lr" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts8, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts9, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts10, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts11, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts12, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts13, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts14, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f32\ts15, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -7,14 +7,7 @@
|
||||
|
||||
/* { dg-final { scan-assembler "__acle_se_foo:" } } */
|
||||
/* { dg-final { scan-assembler "vstr\tFPCXTNS, \\\[sp, #-4\\\]!" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td0, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td1, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td2, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td3, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td4, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td5, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td6, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vmov\.f64\td7, #1\.0" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
@ -29,6 +29,7 @@ main (void)
|
||||
/* { dg-final { scan-assembler "movs\tr1, #255" } } */
|
||||
/* { dg-final { scan-assembler "movt\tr1, 65535" } } */
|
||||
/* { dg-final { scan-assembler "ands\tr0(, r0)?, r1" } } */
|
||||
/* { dg-final { scan-assembler "vscclrm\t\{s0-s15, VPR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "clrm\t\{r1, r2, r3, ip, APSR\}" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "vldr\tFPCXTNS, \\\[sp\\\], #4" { target arm_cmse_clear_ok } } } */
|
||||
/* { dg-final { scan-assembler "bxns" } } */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user